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add net_name=true in bus_tap.sym (so avoid setting it on instancs), add documentation for bus taps

This commit is contained in:
stefan schippers 2023-05-30 11:03:07 +02:00
parent 4a06176f0d
commit 5085301cd7
3 changed files with 59 additions and 37 deletions
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21
doc/xschem_man/tutorial_busses.html
View File

@ -89,6 +89,27 @@ xinv0 BB5 AA0 bf
Example of a more complex bus routing. main bus is a bundle of 2 buses: DATA_A[0..15] and DATA_B[0..15]
</p>
<img src="busses3.png">
<h2> BUS TAPS</h2>
<p>
A new symbol, <kbd>devices/bus_tap.sym</kbd> has been creted to make bus connections more flexible.
This is a 2 pin symbol, one pin must be connected to the bus wire, the other pin only defines the bus slice, indicating
only the range of bits and not the complete bus name: </p>
<img src="busses4.png">
<p>
As you see in the picture a <kbd>lab</kbd> attribute is given that specifies only a bit range, like
<kbd>[13]</kbd> or <kbd>[7:0]</kbd>. The net attached to the 'bus slice' end of the <kbd>bus_tap.sym</kbd>
will get the base name of the bus (<kbd>DATA</kbd> in the example) and the index, that is <kbd>DATA[13]</kbd>
In the example below the menu <kbd>Options-&gt;Show net names on symbol pins / floaters</kbd> has been enbled
to see (the pink texts) the resulting net names.
</p>
<img src="busses5.png">
<p>
A complete example <kbd>examples/test_bus_tap.sch</kbd> shows various possible <kbd>bus_tap.sym</kbd> use cases.
</p>
<img src="busses6.png">
<br>
<br>
<!-- end of slide -->
<div class="filler"></div>
</div>

1
xschem_library/devices/bus_tap.sym
View File

@ -3,6 +3,7 @@ v {xschem version=3.4.0 file_version=1.2
G {}
K {type=show_label
template="name=l1 lab=[0]"
net_name=true
format="* tap: @#0:net_name --> @#1:net_name"
verilog_format="// tap: @#0:net_name --> @#1:net_name"
vhdl_format="-- tap: @#0:net_name --> @#1:net_name"

74
xschem_library/examples/test_bus_tap.sch
View File

@ -105,71 +105,71 @@ lab=DOUT[15:0]}
N 1110 -1170 1110 -800 {
lab=DOUT[15:0]}
C {bus_tap.sym} 400 -390 3 0 {name=l1 lab=[3]
net_name=true}
}
C {bus_tap.sym} 290 -390 3 0 {name=l2 lab=[13]
net_name=true}
}
C {bus_tap.sym} 440 -390 1 0 {name=l3 lab=[7:4]
net_name=true}
}
C {bus_tap.sym} 320 -390 1 0 {name=l4 lab=[11:8]
net_name=true}
}
C {bus_tap.sym} 210 -390 1 0 {name=l5 lab=[3:0]
net_name=true}
}
C {bus_tap.sym} 510 -390 3 0 {name=l7 lab=[10]
net_name=true}
}
C {bus_tap.sym} 630 -390 3 0 {name=l8 lab=[0]
net_name=true}
}
C {res.sym} 620 -560 0 0 {name=R1
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {res.sym} 500 -560 0 0 {name=R2
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {res.sym} 390 -560 0 0 {name=R3
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {res.sym} 280 -560 0 0 {name=R4
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {res.sym} 220 -200 0 0 {name=R5[3:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {res.sym} 330 -200 0 0 {name=R6[3:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {res.sym} 450 -200 0 0 {name=R7[3:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {res.sym} 600 -200 0 0 {name=R8[3:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {lab_pin.sym} 190 -520 0 0 {name=p10 sig_type=std_logic lab=VCC
}
C {bus_tap.sym} 590 -390 1 0 {name=l6 lab=[15:12]
net_name=true}
}
C {lab_pin.sym} 280 -600 0 0 {name=p2 sig_type=std_logic lab=VCC
}
C {lab_pin.sym} 390 -600 0 0 {name=p3 sig_type=std_logic lab=VCC
@ -191,7 +191,7 @@ value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {lab_pin.sym} 170 -390 0 0 {name=p1 sig_type=std_logic lab=DATA[15:0]
}
C {res.sym} 840 -460 0 0 {name=R10[15:0]
@ -199,7 +199,7 @@ value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {title.sym} 160 -30 0 0 {name=l9
author="tcleval(Stefan Schippers[
@ -211,97 +211,97 @@ author="tcleval(Stefan Schippers[
C {lab_pin.sym} 170 -790 0 0 {name=p11 sig_type=std_logic lab=DIN[15..0]
}
C {bus_tap.sym} 270 -790 1 0 {name=l10 lab=0
net_name=true}
}
C {bus_tap.sym} 490 -790 1 0 {name=l11 lab=[4..1]
net_name=true}
}
C {res.sym} 500 -690 0 0 {name=R11[3:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {res.sym} 280 -690 0 0 {name=R12
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {lab_pin.sym} 280 -640 0 0 {name=p12 sig_type=std_logic lab=VSS
}
C {lab_pin.sym} 500 -640 0 0 {name=p13 sig_type=std_logic lab=VSS
}
C {bus_tap.sym} 690 -790 1 0 {name=l12 lab=5
net_name=true}
}
C {res.sym} 700 -690 0 0 {name=R13
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {lab_pin.sym} 700 -640 0 0 {name=p14 sig_type=std_logic lab=VSS
}
C {lab_pin.sym} 230 -980 0 0 {name=p15 sig_type=std_logic lab="CK , S1, ADD[3:0],ENAB"
}
C {bus_tap.sym} 270 -980 1 0 {name=l13 lab=[3:0]
net_name=true}
}
C {bus_tap.sym} 490 -980 1 0 {name=l14 lab=ENAB
net_name=true}
}
C {res.sym} 500 -880 0 0 {name=R15[3:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {res.sym} 280 -880 0 0 {name=R14
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {lab_pin.sym} 280 -830 0 0 {name=p16 sig_type=std_logic lab=VSS
}
C {lab_pin.sym} 500 -830 0 0 {name=p17 sig_type=std_logic lab=VSS
}
C {bus_tap.sym} 690 -980 1 0 {name=l15 lab=CK
net_name=true}
}
C {res.sym} 700 -880 0 0 {name=R16
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {lab_pin.sym} 700 -830 0 0 {name=p18 sig_type=std_logic lab=VSS
}
C {lab_pin.sym} 980 -790 0 0 {name=p19 sig_type=std_logic lab=DOUT
}
C {bus_tap.sym} 1130 -790 1 0 {name=l16 lab=[0]
net_name=true}
}
C {bus_tap.sym} 1300 -790 1 0 {name=l17 lab=[7:1]
net_name=true}
}
C {res.sym} 1310 -690 0 0 {name=R18[6:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {res.sym} 1140 -690 0 0 {name=R17
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {lab_pin.sym} 1140 -640 0 0 {name=p20 sig_type=std_logic lab=VSS
}
C {lab_pin.sym} 1310 -640 0 0 {name=p21 sig_type=std_logic lab=VSS
}
C {bus_tap.sym} 1500 -790 1 0 {name=l18 lab=[15:8]
net_name=true}
}
C {res.sym} 1510 -690 0 0 {name=R19[7:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
}
C {lab_pin.sym} 1510 -640 0 0 {name=p22 sig_type=std_logic lab=VSS
}
C {rom2_sa.sym} 830 -1110 0 0 {name=xsa[15:0]}
@ -313,4 +313,4 @@ C {lab_pin.sym} 680 -1090 0 0 {name=p28 lab=LDSAL}
C {lab_pin.sym} 680 -1070 0 0 {name=p29 lab=vcc}
C {lab_pin.sym} 680 -1050 0 0 {name=p30 lab=vss}
C {bus_tap.sym} 1120 -790 3 0 {name=l19 lab=[15:0]
net_name=true}
}