update circuit examples

tests/xschemtest.tcl

@@ -192,7 +192,7 @@ proc netlist_test {} {
   foreach {f t h} {
     rom8k.sch               spice      1998661799
     greycnt.sch             verilog    2899796185
-    autozero_comp.sch       spice      2431386309
+    autozero_comp.sch       spice       751826850
     loading.sch             vhdl       2975204502
     mos_power_ampli.sch     spice      1986885043
     hierarchical_tedax.sch  tedax       998070173

xschem_library/examples/classD_amp.sch

@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -30,8 +30,8 @@ L 2 1000 -540 1000 -340 {dash=2}
 L 2 950 -540 950 -340 {dash=2}
 L 2 880 -540 880 -340 {dash=2}
 L 2 890 -540 890 -340 {dash=2}
-L 3 30 -1220 370 -1220 {}
-L 3 900 -1220 1240 -1220 {}
+L 3 30 -1220 300 -1220 {}
+L 3 780 -1220 950 -1220 {}
 L 4 475 -210 480 -250 {}
 L 4 480 -250 485 -210 {}
 L 4 30 -865 30 -765 {dash=1}
@@ -173,8 +173,8 @@ B 2 600 -780 996 -635 {flags=image,unscaled
 alpha=0.6
 image_data=iVBORw0KGgoAAAANSUhEUgAAAYwAAACRCAYAAADQBo+7AAAABmJLR0QA/wD/AP+gvaeTAAAKEElEQVR4nO3d25ajKBgGUDOr3/+Vay66ssqmPCCC8JO9b3omB0NQ+AA1tSwAAAAA8KhX7wIA9Xx9fX1tPf56vQ7b+t779pxtD4DBbXX8OWFwJTCuhgvz+K93AQCIQWAAkEVgAJBFYAA09vWtdznuEhgADa2DInpoCAyAxl7fepfjLoEBQBaBAdBI9CWolMAAaChdioocIgIDgCwCA+Ah0U98CwwAsggMALIIDIAGIp/c3iMwABqJfs4iJTAAyCIwAB4WdblKYACQRWAAPCjyeQ2BAUCWP70LwPiirrfOJvLIlDkIDLLorPoS2rHMur8EBkBlsw6wnMMAGMjIsxOBAUCWJoExckICUGbYGYbQARhL05Peaaf/er1ee4+9TxKtn18/DjCTrf5t9IFy8xnG69vZY+nz638hitEbPNwx7JIUwKxyBswj6nIfxtYobO+xkSsPojDzISQHbjz2Wb5WdWUfzCd34DwSS1IAZHk8MCwxAcRkhvHt61vvckSl7mB+fnww0ftE+1bHm1OeKx12q+/3LsNss8jex8QIDAj+NfPxcNSOBcbK+ybCXh3EXqOsXZ5W3693/dGWffpXzfDcu2m5l3d59soiMBLpznu6kWx9Xu6BlFvWlgem0IA8e7980as8OW1WYOzQ8ZXrHbotjDD6g1Zy+7nHAiNi5zFjx/ekmUI3evlhz5X2+chVUqOt010Vuey9vX83zFVosK1n27g6mGseGOsCRR6l6fjuEbrw27pPfLp/LJn5O4dx0UzLLE+bdYnPsXBuPVA4u7Cj5PnIRroi80zTGcbRZaItP7c1o+V7Zqy/mb5LbekAYV1X6xl7yfNcd2fA1nyGkRbq6BrfSGYdLT9lxpmaY+G3dP9udfp7z28tZc943Dzp7jFqSeomB3C5SCPGCGUczVGdvdvNXps5el6bK1NjQNMsMFo3sJEOFrONeyLMOo/2aVr2kY7N3vbq4e7+jnDMjKRW39R0hnHWyEoKn65vnn3Ok4x8yo0cujqm63LrbK+tvN9/1pa0tXM121SzwDgq3N3RwXrbo3XQrULjUzqtyKH7iaPes2Wno/ee1Vfu87X6khnVHoANdw6j9AuO1FBLR8tH67n1Sjd+I4kYGlHKWdvdVYLc17doGyP1GS20mK0PFxjLUvYF71ZKi4MnYsc3ipGXqFIjly0C7aO+Vu0m3B9QWnfCUTqTGlPnT5UGB/Gl7XXk9htRy36x6wyjdGQR8QAz2yg3wmxDYPWjveRr3Ua6BcbWCa3ZG+UIHV9kPUM39/NmP4Zree/LsyugnizTyK7URcu2Mdw5jCidaI2rQ8w2rhO68zjad/brmLqfw4g2isg5F5HzGmvz96g/eF7XwFiPIiI0/LSMr8TV7Tkhfo/QgGd1X5Jan8sYeRq67pRyrgm/uuZoiarME0tU9gn81X1Jall+Rtq9y5Ejt5xXv4/Zxj1mG9DeEIExuic7IR1fOaELbXVfkorkqVnQOjSizLxGYomPZckbdOW8xjH0Q2AMLMr5nREJXez3+gTG4IyW7xG6tPCpS54CIwDr8vf0CN2SfXVWNvuf3gRGAL1HyDqq62a7vNcx8K+n98Uo9S8wLnh6Wah3UMxCPUIdAiPDeh38KTq5+9ThZ6vVZh0/PwTGRbmzjNLZiE6uDvVIzjkhx8c1AiPTepax1xndHdHo5O5Th9COwLggXZqqNeXVydWhHqEtgXFRzk93XOmwdHL35fww5N3t2z8gMIrd7UAERR3qEZ7jxwc70MnVoR7ht5ZXdJphPEgHV0ePehzlxik+09Vl7lbLqFMERoTGLCzqUI9wrOVP4YQPjNHDQgdXR+96zP3c0Y9HPkOr0AgfGG+1TkLX1LuTm4V6hOtahMY0gTESHVwd6hHuqR0arpKqTCdXx8j1aNmJSHLuHctlhlHJyB1cJOlBPVK9CgqiqjXTMMOoYKROLbL0ju23nmV62wsyiKLGTMMM44bWP0nxKdaBu3cwj9hB75XJscCo7s40BEYhs4o60nrcC42e9fxuXAYIzOBOaAiMAsLivrM6HHFGcTQDIp5Pbr+loSEwLhAUdZzVo/qF9kpCw0nvTMLivvXBGbUeo5Ybtlw9ES4wTszQyY1gpsCd4TvA25XQEBgHZurkehG4ML7c0HAOY4OgqGOmerx6snuG78xnWZ/T2HuNwEjM1Mn1MmMd5n6Xu3fSQk9nVwIKjBWN/R73KUB8R6EhMFZ0cnWoxzm5B+Vz7LVhgfFNJ3fPzPU383fLpQ5YFldJAZBJYACQRWAAkEVgAJBFYABT2rsJzdVe5QQGUGz0zrfGX5njh8CAilx+Oqat/SJErnMfBlDN3l9LTP8Mb9qBp+/bmhls/dXDvV8XeD+e8/zWnc3+wuI2MwygqvSXidcdb/rfaae8976SMmxtc+v53G0hMIBOcn7yPn1N+vranfnZ5306S1LALelMYGvZaL3EtNcJ51zRdPb/JWXfmtUIim1DVcrTJ6EcFHn8im9/s++D2b/fLIabYTx10Kz/EtwTnwcQnXMYQHcGbjEMN8M4kzMrsA5Zn2vWgVAzDJ1WH4IXWJaAM4xlcYKsB/UNhJphLMt5x2UWAtBGmMC4EgTvm2+EB0A9YQJjWbZ/CwaAZ4QKjLcrd4oSW8R9uvXDdzCDEIFxdTlq/d8a7XO+EjmvL/2ckvcB94QIjGXxe/ZRvFZyXrss1/djjyu2HGsQ9LLaZfk9e9Cgx7D1dw+2Hlu/9v3f6T7det3WdtPn0se2ynf0+r1jae9zjz4v/cytz3DJMlEMP8MoXY4q3Qblti5KOAv193vSpcSj/0/fnz53NsPJ2f76sa0ypo+XdvrCgkiGD4xlOW5UZ2GgQT7rTucZScl33AqquqWCtsIuSS3Lz9TeDGIMe0sv66Wlo1lgugRV2qGeHQ/p9nOPn73yX3n/+nOBG9KGlxMGpa8RNHOzf6G+4ZekaozGjOjG1aJTFxTQxtBLUjkd/dlVK3weAwRoY/gZRo7cYHmiLDynZKBw9XwD8GPoGQbx3LnPYWsb6/dsnaQ+uyfj6D1Hn5m+ruR7GaQwmylmGIxhLwhq3Cux9fz639L35LzuyveCmQ03w7AUENvVS1VHcTbzufK9hAizGiowNLT4ap0j2Fsi2nrsqDM/e0/tba8fdzwDDKjXjMb9HnwS5zCgkKCADjQ8gPH9cw5jq+Ner8Nurf0C8MGeHvGbYfylHoCRnV4ltXczUumNTOmVJ0dXqxx91nr76Xa3yn32HdaPH333Wo/tXcZ5diPaXlkBWss+6Z3TGZfcoLV2NsLeK0P6vpoj9dzyX/mee4Gw/vdom8IC6CHrPoyjTqv2Mkru6P/KdtLZyN5rS7Z/9XVpILzLWPtzAWorvnHvzg1aR+/NvZP2ytJWbhm3OuO7N2dd3fbZzWIAU4t+c1P08gPU0PzGvegdbfTyAwDAo/4HLBNKOj5NZq4AAAAASUVORK5CYII=}
 B 2 1060 -1310 2040 -1000 {flags=graph
-y1=-15.5725
-y2=188.527
+y1=0
+y2=210
 ypos1=2.19058
 ypos2=36.4765
 divy=5
@@ -214,7 +214,7 @@ T {10} 25 -850 0 1 0.2 0.2 {}
 T {10} 25 -1170 0 1 0.2 0.2 {}
 T {DRIVED} 135 -805 0 0 0.2 0.2 {}
 T {DRIVEU} 130 -1125 0 0 0.2 0.2 {}
-T {Class D amplifier } 410 -1250 0 0 1 1 {}
+T {Class D amplifier } 320 -1250 0 0 1 1 {}
 T {-10} 25 -780 0 1 0.2 0.2 {}
 T {-10} 25 -1100 0 1 0.2 0.2 {}
 N 460 -1020 460 -1000 {lab=#net1}
@@ -472,6 +472,7 @@ value="
 save all
 tran 100n 2000u uic
 write classD_amp.raw
+quit 0
 .endc
 "}
 C {simulator_commands_shown.sym} 680 -250 0 0 {name=COMMANDS1

xschem_library/examples/cmos_example.sch

@@ -362,6 +362,7 @@ value=".temp 30
   ac dec 10 1 1G
   remzerovec
   write cmos_example_ngspice.raw
+  quit 0
 .endc
 
 "}

xschem_library/examples/poweramp.sch

@@ -339,7 +339,6 @@ value="
 .option ITL4=20000 ITL5=0
 vvss vss 0 dc 0 
 .temp 30
-
 .param frequ=5k
 .param gain=45
 .option savecurrents
@@ -358,6 +357,7 @@ tran  8e-7 0.07 uic
 plot outp outm
 save p(r*) p(v*)
 write poweramp.raw
+quit 0
 .endc
 "}
 C {simulator_commands.sym} 1020 -870 0 0 {name=COMMANDS1

xschem_library/examples/test_jfet.sch

@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -112,6 +112,7 @@ VD D 0 dc 0
   save all
   dc VD 0 20 0.01 VG 0 -1 -0.1
   write test_jfet.raw
+  quit 0
 .endc
 "}
 C {noconn.sym} 340 -140 0 0 {name=l1}

xschem_library/ngspice/autozero_comp.sch

@@ -348,6 +348,7 @@ value="* .option SCALE=1e-6
     write autozero_comp.raw
     let run = run + 1
   end
+  quit 0
 .endc
 "}
 C {inv-2.sym} 160 -570 0 0 {name=x14 m=1 

xschem_library/ngspice/solar_panel.sch

@@ -280,9 +280,10 @@ value="tcleval(
   *   schematic: [xschem get current_name]
   tran .05u 1m uic
   write solar_panel.raw
-  exit
+  quit 0
 .endc
-)" 
+)
+" 
 
 net_name=true}
 C {code.sym} 20 -240 0 0 {name=MODELS value=".MODEL DIODE D(IS=1.139e-08 RS=0.99 CJO=9.3e-12 VJ=1.6 M=0.411 BV=30 EG=0.7 )