stefan schippers
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9fee9610ab
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vsource.sym and ammeter.sym: add "savecurrent=1|0|true|false" attribute do decide if a .save I(...) is to be printed in netlist. default is 1 for ammeter.sym and 0 for vsource.sym. Add "deltax deltay rot flip" optional parameters for xschem "copy_objects" command to make copy operation scriptable (lot more efficient than using clipboard)
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2023-10-02 12:11:05 +02:00 |
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stefan schippers
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ee67a23465
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revert a change in example schematic pcb_test1.sch so xschemtest will not report a false error
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2023-09-20 12:35:26 +02:00 |
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stefan schippers
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53207732b9
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minor doc/man updates, typo cleanups
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2023-09-19 23:59:01 +02:00 |
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stefan schippers
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75e99cae91
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update tier.tcl generator to handle unresolvable parameters
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2023-09-19 01:29:52 +02:00 |
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stefan schippers
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fd2be4a599
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update res.tcl generator to handle unresolvable parameters
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2023-09-19 00:08:42 +02:00 |
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stefan schippers
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bb6caaf501
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update tier.tcl generator and testbench
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2023-09-16 11:20:40 +02:00 |
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stefan schippers
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82f8afbb19
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optimize select_dangling_nets() a bit
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2023-09-15 11:01:33 +02:00 |
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stefan schippers
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19fbba5c60
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update docs about parametrized subcircuits, add braces around parameters (some ngspice version require them, some other can live without for simple non expression params), Update text example comp_ngspice.sch
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2023-07-13 21:13:56 +02:00 |
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stefan schippers
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a329c18bfb
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(propdel) remove unneeded exec flags
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2023-07-03 13:12:40 +02:00 |
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stefan schippers
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f8f7c4f230
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updated moude_bindings.tcl with Paul`s new version, updated noconn.sym (do not use *_ignore attributes, put comments in netlist about NC net)
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2023-06-30 09:11:04 +02:00 |
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stefan schippers
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810b814211
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added some comments in code / schematics
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2023-06-18 23:44:52 +02:00 |
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stefan schippers
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c97dfddd4e
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fix memory leak due to improper use of get_pin_and_attr()
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2023-06-17 10:14:55 +02:00 |
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stefan schippers
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3c16c4bf20
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separated @#pin:attr handling in translate() into *get_pin_attr(), replaced sscanf() with dedicated get_pin_and_attr() so we are able to handle stuff like "@#ADD[7:0]:net_name"
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2023-06-16 10:55:22 +02:00 |
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stefan schippers
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01806eaa10
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fix meaningless pin attributes on tier.tcl
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2023-06-15 09:05:15 +02:00 |
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stefan schippers
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eca52e1f4a
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added comp_65nm_read.sym example in inst_sch_select/inst_sch_select.sch, symbol with spice_sym_def attribute
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2023-06-12 18:22:40 +02:00 |
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stefan schippers
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910235749b
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small updates to solar_panel.sch test schematic
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2023-06-12 08:17:42 +02:00 |
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stefan schippers
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d56e3939d5
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updated xschem_library/examples/test_backannotated_subckt.sch; fix a potential segfault in proc fix_symbol
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2023-06-08 01:08:05 +02:00 |
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stefan schippers
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6f0e4e935f
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update generators/res.tcl
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2023-06-07 10:17:02 +02:00 |
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stefan schippers
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4d98cc7b41
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moved test_generators under generators/
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2023-06-07 09:51:11 +02:00 |
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stefan schippers
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3a42cfa64c
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added test_generators.sch example
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2023-06-07 09:38:11 +02:00 |
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stefan schippers
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e63818f980
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reverted solar_panel.sch (was changed for testing)
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2023-06-07 03:44:42 +02:00 |
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stefan schippers
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245993f034
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added attributes spice_ignore=short, verilog_ignore=short, .... that will transform the instance into a short in the current netlisting mode, shorting all pins to the same net. Works similarly as lvs_ignore=short, but does not need lvs_ignore global setting
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2023-06-07 03:41:49 +02:00 |
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stefan schippers
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38a28a3acb
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add lvs_ignore to context saved vars. Refactored some preprocessor macros SPICE_IGNORE_INST --> SPICE_IGNORE)
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2023-06-06 23:38:29 +02:00 |
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stefan schippers
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394db224d1
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added global tcl variable `lvs_ignore` that can be used to enable instance or symbol attributes `lvs_ignore=open` or `lvs_ignore=short` while netlisting, added `test_lvs_ignore.sch` example
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2023-06-06 15:22:45 +02:00 |
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stefan schippers
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ff216e8187
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function reset_flags() set flags on symbols and instances; call reset_flags before rebuilding connectivity to update cached values; add short.sym component that can be used to short two nets together (and remove the short using *_ignore=true); instcheck(): do not proces instances that have *_ignore=true set.
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2023-06-06 08:42:43 +02:00 |
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stefan schippers
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4f387f3bbe
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disable displaying backannotation data if `b` cursor is hidden or `Simulation->Live annotation with b cursor` is disabled. Use resolved_net() in translate() when displaying @spice_get_voltage so it will work on sub block ports
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2023-06-05 12:58:19 +02:00 |
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stefan schippers
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0244dc5e69
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add command xschem tab_list, returns window pathname and associated filename loaded
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2023-06-03 00:21:55 +02:00 |
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Stefan Schippers
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f5c592c889
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xschem resolved_net command: add [net] parameter; instcheck(): use inst[].lab instead of get_tok_value(inst[].prop_ptr, "lab",0)
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2023-06-01 18:00:47 +02:00 |
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Stefan Schippers
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f3f12da486
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updated test_extracted_netlist.sch example
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2023-06-01 16:02:40 +02:00 |
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stefan schippers
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60a6a76ac2
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update test_extracted_netlist.sch
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2023-06-01 11:36:47 +02:00 |
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stefan schippers
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39f2747149
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fix some errors found by Joanne in test_bus_tap.sch
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2023-05-31 00:14:22 +02:00 |
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stefan schippers
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5085301cd7
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add net_name=true in bus_tap.sym (so avoid setting it on instancs), add documentation for bus taps
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2023-05-30 11:03:07 +02:00 |
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stefan schippers
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4a06176f0d
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comments, more test_bus_tap examples
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2023-05-29 16:48:13 +02:00 |
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stefan schippers
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487b1eb202
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more flexible bus_tap syntax
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2023-05-29 09:17:06 +02:00 |
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stefan schippers
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6bbc60f8fb
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add more ".." bus notations: XX[4,2,8..1..3,12,23] and others. bus_tap.sym: if no "[n]" pattern is given assume it is the complete name of the slice (does not need bus basename)
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2023-05-28 15:30:40 +02:00 |
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stefan schippers
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5043b14921
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fix uninitialized wave_color due to regression after rainbow wave color enablement in double dc sweeps; more bus_tap.sym usage in examples; make bus_tap.sym work correctly for all netlist formats
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2023-05-27 23:36:10 +02:00 |
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Stefan Schippers
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cff9f7d169
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some bug fixes in resolved_net hashing, use some @#n:resolved_net labels in examples
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2023-05-27 21:48:21 +02:00 |
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stefan schippers
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cf61c253c5
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fix a bug in my_mstrcat if an empty string is appended; add resolved_net(n) function that returns the top-most hierarchy name of the net mapping to upper level port connections if any; add xschem resolved_net comand that returns the resolved_net of selected wire/label/pin; add @#n:resolved_net pattern in symbol texts that uses resolved_net
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2023-05-27 11:20:49 +02:00 |
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stefan schippers
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c3d7780150
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updated test_bus_tap.sch with more bus tapping cases
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2023-05-25 09:51:17 +02:00 |
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Stefan Schippers
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ba402e65c0
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remove unneeded variable in create_new_tab()
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2023-05-24 18:20:18 +02:00 |
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stefan schippers
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d3b99d3a76
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update n and p jfets, added pjfet simulation
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2023-05-24 10:02:26 +02:00 |
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stefan schippers
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608a144dd1
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fix tcl procedures using find_file to find a component: use find_file_first (return 1st match) , since find_file may return multiple matches; add njfet.sym, pjfet.sym and test_jfet.sch
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2023-05-24 08:43:05 +02:00 |
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Stefan Schippers
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1774ff4e3a
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allow @#n:pin_attr or @#pin_name:pin_attr in spice format string (print_spice_element), in addition to @#n (convergence to translate()
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2023-05-22 21:50:14 +02:00 |
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stefan schippers
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0f1bbd24c8
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devices/bus_tap.sym: remove format attr in symbol
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2023-05-22 11:52:51 +02:00 |
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stefan schippers
|
ade1aaf858
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(3) update examples/test_bus_tap.sch
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2023-05-22 08:51:23 +02:00 |
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stefan schippers
|
6de12e5a0f
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(2) update examples/test_bus_tap.sch
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2023-05-22 08:09:42 +02:00 |
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stefan schippers
|
8f63560737
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examples/test_bus_tap.sch: auto set show_pin_net_names=1
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2023-05-22 08:05:37 +02:00 |
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stefan schippers
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9715cf4a5c
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update examples/test_bus_tap.sch
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2023-05-22 07:45:23 +02:00 |
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stefan schippers
|
b68dd8c099
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when a bus label is edited correctly propagate list of instances to be redrawn if show net names on components is enabled (ie: propagate thru bus taps)
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2023-05-22 07:28:12 +02:00 |
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stefan schippers
|
a4d5ddb63f
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add examples/test_bus_tap.sch
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2023-05-22 00:49:54 +02:00 |