add command xschem tab_list, returns window pathname and associated filename loaded
This commit is contained in:
stefan schippers
parent
1ea1e835ae
commit
0244dc5e69
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@ -484,6 +484,8 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
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<li><kbd> abort_operation</kbd></li><pre>
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Resets UI state, unselect all and abort any pending operation </pre>
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<li><kbd> add_symbol_pin</kbd></li><pre>
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@ -972,7 +974,7 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
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<li><kbd> resolved_net [net]</kbd></li><pre>
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if 'net' is given return its topmost full hierarchy name
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else returns the topmost full hierarchy name of selected net/pin/label.
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Nets connected to I/O ports are mapped to upper level recursively</pre>
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Nets connected to I/O ports are mapped to upper level recursively </pre>
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<li><kbd> rotate</kbd></li><pre>
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Rotate selected objects around their centers </pre>
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<li><kbd> save</kbd></li><pre>
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@ -1103,6 +1105,8 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
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<li><kbd> symbols [n]</kbd></li><pre>
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if 'n' given list symbol with name or number 'n', else
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list all used symbols </pre>
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<li><kbd> tab_list</kbd></li><pre>
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list all windows / tabs with window pathname and associated filename </pre>
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<li><kbd> table_read [table_file]</kbd></li><pre>
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If a simulation raw file is lodaded unload from memory.
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else read a tabular file 'table_file'
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@ -33,7 +33,7 @@
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#define CAD_SPICE_NETLIST 1
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static int dbg_var = 0;
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static int parselabel_debug = 0;
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#include "xschem.h"
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/*
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@ -97,7 +97,7 @@ const char *expandlabel(const char *s, int *m)
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YY_BUFFER_STATE buf;
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my_free(_ALLOC_ID_, &dest_string.str); /* 30102004 delete 'memory' of previous execution */
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if(dbg_var >= 3) fprintf(errfp, "expandlabel(): entering\n");
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if(parselabel_debug >= 3) fprintf(errfp, "expandlabel(): entering\n");
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buf=yy_scan_string(s);
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yyparse();
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yy_delete_buffer(buf);
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@ -115,7 +115,7 @@ const char *expandlabel(const char *s, int *m)
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my_free(_ALLOC_ID_, &cmd);
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}
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if(dbg_var >= 3)
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if(parselabel_debug >= 3)
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fprintf(errfp, "expandlabel(): returning %s from %s mult=%d\n",dest_string.str, s, dest_string.m);
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if(dest_string.str)
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*m = dest_string.m;
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@ -170,7 +170,7 @@ ID_EXT_PARENTHESIS ([-~"#+/=_a-zA-Z][-#!@\\/:.=_+a-zA-Z0-9]*\([-~"#!@\\/:.=_+a-z
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/* this action resets initial condition at start of line. This is extremely useful if previously lexer
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* bailed out in the middle of some non INITIAL start condition due to yyparse() syntax errors */
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<mult,index>^. {
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if(dbg_var >= 3) fprintf(errfp, "yylex(): matched: ^[^*] |%s|, push back\n",yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): matched: ^[^*] |%s|, push back\n",yytext);
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yyless(0); /* push entire token back to input */
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BEGIN(INITIAL); /* reset parser */
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}
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@ -179,7 +179,7 @@ ID_EXT_PARENTHESIS ([-~"#+/=_a-zA-Z][-#!@\\/:.=_+a-zA-Z0-9]*\([-~"#!@\\/:.=_+a-z
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/* postfix multiplier */
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{INT} {
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sscanf(yytext, "%d",&yylval.val);
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if(dbg_var >= 3) fprintf(errfp, "yylex(): postmult B_NUM: |%s|\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): postmult B_NUM: |%s|\n", yytext);
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BEGIN(INITIAL);
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return B_NUM;
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}
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@ -189,35 +189,35 @@ ID_EXT_PARENTHESIS ([-~"#+/=_a-zA-Z][-#!@\\/:.=_+a-zA-Z0-9]*\([-~"#!@\\/:.=_+a-z
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<index>{
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{INT} {
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sscanf(yytext, "%d",&yylval.val);
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if(dbg_var >= 3) fprintf(errfp, "yylex(): B_IDXNUM: |%s|\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): B_IDXNUM: |%s|\n", yytext);
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return B_IDXNUM;
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}
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{DDOT} {
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if(dbg_var >= 3) fprintf(errfp, "yylex(): B_DOUBLEDOT: |%s|\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): B_DOUBLEDOT: |%s|\n", yytext);
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return B_DOUBLEDOT;
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}
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/* end vector node index "...]" */
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\] {
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if(dbg_var >= 3) fprintf(errfp, "yylex(): close bracket: %s\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): close bracket: %s\n", yytext);
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BEGIN(INITIAL);
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return yytext[0];
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}
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{NOTSP} {
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if(dbg_var >= 3) fprintf(errfp, "yylex(): idx character: |%s|\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): idx character: |%s|\n", yytext);
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return yytext[0];
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}
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/* recognize AA[aa:bb:33] or AA[33:cc:dd] or AA[aa..bb..11] .... */
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({IDX_ID}{DDOT}{IDX_ID_N}{DDOT}{IDX_ID_N})|({IDX_ID_N}{DDOT}{IDX_ID}{DDOT}{IDX_ID_N})|({IDX_ID_N}{DDOT}{IDX_ID_N}{DDOT}{IDX_ID}) {
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yylval.ptr.str=NULL;
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my_strdup(_ALLOC_ID_, &yylval.ptr.str, yytext);
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if(dbg_var >= 3) fprintf(errfp, "yylex(): B_NAME3: |%s|\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): B_NAME3: |%s|\n", yytext);
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return B_NAME;
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}
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({IDX_ID}{CLN}{IDX_ID_N}{CLN}{IDX_ID_N})|({IDX_ID_N}{CLN}{IDX_ID}{CLN}{IDX_ID_N})|({IDX_ID_N}{CLN}{IDX_ID_N}{CLN}{IDX_ID}) {
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yylval.ptr.str=NULL;
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my_strdup(_ALLOC_ID_, &yylval.ptr.str, yytext);
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if(dbg_var >= 3) fprintf(errfp, "yylex(): B_NAME2: |%s|\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): B_NAME2: |%s|\n", yytext);
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return B_NAME;
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}
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@ -225,7 +225,7 @@ ID_EXT_PARENTHESIS ([-~"#+/=_a-zA-Z][-#!@\\/:.=_+a-zA-Z0-9]*\([-~"#!@\\/:.=_+a-z
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({IDX_ID}{CLN}{IDX_ID_N})|({IDX_ID_N}{CLN}{IDX_ID})|({IDX_ID}{DDOT}{IDX_ID_N})|({IDX_ID_N}{DDOT}{IDX_ID}) {
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yylval.ptr.str=NULL;
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my_strdup(_ALLOC_ID_, &yylval.ptr.str, yytext);
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if(dbg_var >= 3) fprintf(errfp, "yylex(): B_NAME1: |%s|\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): B_NAME1: |%s|\n", yytext);
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return B_NAME;
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}
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} /* end <index> */
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@ -233,7 +233,7 @@ ID_EXT_PARENTHESIS ([-~"#+/=_a-zA-Z][-#!@\\/:.=_+a-zA-Z0-9]*\([-~"#!@\\/:.=_+a-z
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/* a comment, return as LINE token */
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^\*.* {
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yylval.ptr.str=NULL; /*19102004 */
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if(dbg_var >= 3) fprintf(errfp, "yylex(): B_LINE: |%s|\n",yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): B_LINE: |%s|\n",yytext);
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my_strdup(_ALLOC_ID_, &yylval.ptr.str, yytext); /* freed after use in expandlabel.y */
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BEGIN(INITIAL);
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return B_LINE;
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@ -241,7 +241,7 @@ ID_EXT_PARENTHESIS ([-~"#+/=_a-zA-Z][-#!@\\/:.=_+a-zA-Z0-9]*\([-~"#!@\\/:.=_+a-z
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/* prefix multiplier */
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{INT}/{MULTIP} {
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sscanf(yytext, "%d",&yylval.val);
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if(dbg_var >= 3) fprintf(errfp, "yylex(): premult B_NUM: |%s|\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): premult B_NUM: |%s|\n", yytext);
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BEGIN(INITIAL);
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return B_NUM;
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}
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@ -249,17 +249,17 @@ ID_EXT_PARENTHESIS ([-~"#+/=_a-zA-Z][-#!@\\/:.=_+a-zA-Z0-9]*\([-~"#!@\\/:.=_+a-z
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{INT} {
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yylval.ptr.str=NULL;
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my_strdup(_ALLOC_ID_, &yylval.ptr.str, yytext);
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if(dbg_var >= 3) fprintf(errfp, "yylex(): B_NAME4: |%s|\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): B_NAME4: |%s|\n", yytext);
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BEGIN(INITIAL);
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return B_NAME;
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}
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{SP} {
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if(dbg_var >= 3) fprintf(errfp, "yylex(): skipping: |%s|\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): skipping: |%s|\n", yytext);
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}
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/* comma separator between nodes: chop spaces "a,b , c" */
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{SP},{SP} {
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yylval.val=',';
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if(dbg_var >= 3) fprintf(errfp, "yylex(): comma: |%s|\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): comma: |%s|\n", yytext);
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BEGIN(INITIAL);
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return ',';
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}
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@ -268,30 +268,30 @@ ID_EXT_PARENTHESIS ([-~"#+/=_a-zA-Z][-#!@\\/:.=_+a-zA-Z0-9]*\([-~"#!@\\/:.=_+a-z
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{ID_NUM}|{ID_EXT_PARENTHESIS} {
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yylval.ptr.str=NULL;/*19102004 */
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my_strdup(_ALLOC_ID_, &yylval.ptr.str, yytext); /* freed after use in expandlabel.y */
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if(dbg_var >= 3) fprintf(errfp, "yylex(): B_NAME0: |%s|\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): B_NAME0: |%s|\n", yytext);
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BEGIN(INITIAL);
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return B_NAME;
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}
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/* start vector node index: "aa[" */
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\[ {
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if(dbg_var >= 3) fprintf(errfp, "yylex(): open bracket: %s\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): open bracket: %s\n", yytext);
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BEGIN(index);
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return yytext[0];
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}
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/* "*(aa,bb,cc)" or "*aaa" prefix multiplication*/
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{SP}\*{SP}/({ID}|[(]) {
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if(dbg_var >= 3) fprintf(errfp, "yylex(): pre *: |%s|\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): pre *: |%s|\n", yytext);
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BEGIN(INITIAL);
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return '*';
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}
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/* "*16" postfix multiplication */
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{MULTIP}/{INT} {
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if(dbg_var >= 3) fprintf(errfp, "yylex(): post *: |%s|\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): post *: |%s|\n", yytext);
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BEGIN(mult);
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return '*';
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}
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{NOTSP} {
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if(dbg_var >= 3) fprintf(errfp, "yylex(): character: |%s|\n", yytext);
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if(parselabel_debug >= 3) fprintf(errfp, "yylex(): character: |%s|\n", yytext);
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BEGIN(INITIAL);
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return yytext[0];
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}
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@ -3678,6 +3678,30 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
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else { cmd_found = 0;}
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break;
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case 't': /*----------------------------------------------*/
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/* tab_list
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* list all windows / tabs with window pathname and associated filename */
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if(!strcmp(argv[1], "tab_list"))
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{
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int i;
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Xschem_ctx *ctx, **save_xctx = get_save_xctx();
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int found = 0;
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for(i = 0; i < MAX_NEW_WINDOWS; ++i) {
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ctx = save_xctx[i];
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/* if only one schematic it is not yet saved in save_xctx */
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if(get_window_count() == 0 && i == 0) {
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ctx = xctx;
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}
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if(i == 0 ) {
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if(ctx) Tcl_AppendResult(interp, ".drw", " {", ctx->sch[ctx->currsch], "}\n", NULL);
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}
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else if(ctx) {
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Tcl_AppendResult(interp, get_window_path(i), " {", ctx->sch[ctx->currsch], "}\n", NULL);
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}
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}
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dbg(1, "check_loaded: return %d\n", found);
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return found;
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}
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/* table_read [table_file]
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* If a simulation raw file is lodaded unload from memory.
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* else read a tabular file 'table_file'
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@ -3702,7 +3726,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
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* 0.1 0.0 1.5 0.6
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* ... ... ... ...
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*/
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if(!strcmp(argv[1], "table_read"))
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else if(!strcmp(argv[1], "table_read"))
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{
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char f[PATH_MAX + 100];
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if(sch_waves_loaded() >= 0) {
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@ -3722,6 +3746,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
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}
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Tcl_ResetResult(interp);
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}
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/* test
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* testmode */
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else if(!strcmp(argv[1], "test"))
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19
src/xinit.c
19
src/xinit.c
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@ -77,6 +77,20 @@ static int client_msg(Display *disp, Window win, char *msg, /* {{{ */
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}
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}/*}}}*/
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Xschem_ctx **get_save_xctx(void)
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{
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return save_xctx;
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}
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char *get_window_path(int i)
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{
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return window_path[i];
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}
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int get_window_count(void)
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{
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return window_count;
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}
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static int window_state (Display *disp, Window win, char *arg) {/*{{{*/
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char arg_copy[256]; /* overflow safe */
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@ -1176,7 +1190,10 @@ int check_loaded(const char *f, char *win_path)
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ctx = save_xctx[i];
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dbg(1, "window_count=%d i=%d\n", window_count, i);
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/* if only one schematic it is not yet saved in save_xctx */
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if(window_count == 0 && i == 0) ctx = xctx;
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if(window_count == 0 && i == 0) {
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ctx = xctx;
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my_snprintf(window_path[0], S(window_path[0]), ".drw" );
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}
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if(ctx) {
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dbg(1, "%s <--> %s\n", ctx->sch[ctx->currsch], f);
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if(!strcmp(ctx->sch[ctx->currsch], f)) {
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@ -1333,6 +1333,9 @@ extern void mem_clear_undo(void);
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extern void load_schematic(int load_symbol, const char *fname, int reset_undo, int alert);
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/* check if filename already in an open window/tab */
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extern int check_loaded(const char *f, char *win_path);
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extern char *get_window_path(int i);
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extern int get_window_count(void);
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extern Xschem_ctx **get_save_xctx(void);
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extern void link_symbols_to_instances(int from);
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extern void load_ascii_string(char **ptr, FILE *fd);
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extern char *read_line(FILE *fp, int dbg_level);
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@ -1,33 +1,55 @@
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v {xschem version=3.0.0 file_version=1.2 }
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v {xschem version=3.4.0 file_version=1.2
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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N 600 -450 650 -450 {lab=B}
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N 690 -690 690 -670 {lab=D}
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N 510 -690 690 -690 {lab=D}
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N 190 -690 310 -690 {lab=VCC}
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N 190 -690 190 -670 {lab=VCC}
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N 690 -500 690 -480 {lab=C}
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N 690 -500 750 -500 {lab=C}
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N 810 -500 840 -500 {lab=OUT}
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N 840 -500 840 -440 {lab=OUT}
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N 690 -410 690 -400 {lab=E}
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N 780 -410 780 -400 {lab=E}
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N 690 -410 780 -410 {lab=E}
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N 510 -450 510 -400 {lab=#net1}
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N 510 -570 510 -530 {lab=#net2}
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N 420 -450 510 -450 {lab=#net1}
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N 370 -690 510 -690 {lab=D}
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N 690 -420 690 -410 {lab=E}
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N 510 -470 510 -450 {lab=#net1}
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N 190 -450 360 -450 {lab=IN}
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N 190 -450 190 -420 {lab=IN}
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N 840 -500 930 -500 {lab=OUT}
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N 510 -450 540 -450 {lab=#net1}
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N 510 -690 510 -630 {lab=D}
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N 690 -550 690 -500 {lab=C}
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B 2 770 -500 1570 -100 {flags=graph
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y1=-50
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y2=40
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ypos1=0
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ypos2=2
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divy=5
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subdivy=1
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unity=1
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x1=2
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x2=10.0002
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divx=5
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subdivx=8
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xlabmag=1.0
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ylabmag=1.0
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node="\\"out db20()\\""
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color=4
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dataset=-1
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unitx=1
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logx=1
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logy=0
|
||||
}
|
||||
N 450 -510 500 -510 {lab=B}
|
||||
N 540 -750 540 -730 {lab=D}
|
||||
N 360 -750 540 -750 {lab=D}
|
||||
N 40 -750 160 -750 {lab=VCC}
|
||||
N 40 -750 40 -730 {lab=VCC}
|
||||
N 540 -560 540 -540 {lab=C}
|
||||
N 540 -560 600 -560 {lab=C}
|
||||
N 660 -560 690 -560 {lab=OUT}
|
||||
N 690 -560 690 -500 {lab=OUT}
|
||||
N 540 -470 540 -460 {lab=E}
|
||||
N 630 -470 630 -460 {lab=E}
|
||||
N 540 -470 630 -470 {lab=E}
|
||||
N 360 -510 360 -460 {lab=#net1}
|
||||
N 360 -630 360 -590 {lab=#net2}
|
||||
N 270 -510 360 -510 {lab=#net1}
|
||||
N 220 -750 360 -750 {lab=D}
|
||||
N 540 -480 540 -470 {lab=E}
|
||||
N 360 -530 360 -510 {lab=#net1}
|
||||
N 40 -510 210 -510 {lab=IN}
|
||||
N 40 -510 40 -480 {lab=IN}
|
||||
N 690 -560 740 -560 {lab=OUT}
|
||||
N 360 -510 390 -510 {lab=#net1}
|
||||
N 360 -750 360 -690 {lab=D}
|
||||
N 540 -610 540 -560 {lab=C}
|
||||
C {title.sym} 160 -30 0 0 {name=l7 author="Stefan Schippers"}
|
||||
C {code_shown.sym} 30 -310 0 0 {name=CONTROL place=end value=".ac oct 1000 100 10G
|
||||
.control
|
||||
|
|
@ -43,43 +65,47 @@ C {code_shown.sym} 30 -310 0 0 {name=CONTROL place=end value=".ac oct 1000 100 1
|
|||
.endc
|
||||
|
||||
"}
|
||||
C {code.sym} 840 -250 0 0 {name=MODELS value=".model Q2N2219A NPN(Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
|
||||
+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10 Vceo=40 Icrating=800m mfg=Philips)
|
||||
C {code.sym} 590 -240 0 0 {name=MODELS value=".model Q2N2219A NPN(Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
|
||||
+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10 Vceo=40 Icrating=800m )
|
||||
"}
|
||||
C {ind.sym} 340 -690 1 0 {name=l1 value=10uH}
|
||||
C {vsource.sym} 190 -640 0 0 {name=v1 value=12}
|
||||
C {gnd.sym} 190 -610 0 0 {name=l11 lab=0}
|
||||
C {capa.sym} 430 -660 0 1 {name=C4 m=1 value=100nF footprint=1206 device="ceramic capacitor"}
|
||||
C {res.sym} 510 -500 0 0 {name=R1 value=6.8k footprint=1206 device=resistor m=1}
|
||||
C {npn.sym} 670 -450 0 0 {name=Q2 model=Q2N2219A device=Q2N5179 footprint=SOT23 area=1}
|
||||
C {res.sym} 510 -370 0 0 {name=R2 value=1.8k footprint=1206 device=resistor m=1}
|
||||
C {capa.sym} 780 -500 1 1 {name=C5 m=1 value=1nF footprint=1206 device="ceramic capacitor"}
|
||||
C {res.sym} 840 -410 0 0 {name=R3 value=120k footprint=1206 device=resistor m=1}
|
||||
C {gnd.sym} 840 -380 0 0 {name=l12 lab=0}
|
||||
C {res.sym} 690 -370 0 0 {name=R4 value=100 footprint=1206 device=resistor m=1}
|
||||
C {gnd.sym} 690 -340 0 0 {name=l13 lab=0}
|
||||
C {capa.sym} 390 -450 1 1 {name=C6 m=1 value=1nF footprint=1206 device="ceramic capacitor"}
|
||||
C {vsource.sym} 190 -390 0 0 {name=v2 value="dc 0 ac 1"}
|
||||
C {gnd.sym} 190 -360 0 0 {name=l14 lab=0}
|
||||
C {res.sym} 690 -640 0 0 {name=R5 value=330 footprint=1206 device=resistor m=1}
|
||||
C {capa.sym} 780 -370 0 1 {name=C7 m=1 value=100nF footprint=1206 device="ceramic capacitor"}
|
||||
C {gnd.sym} 780 -340 0 0 {name=l15 lab=0}
|
||||
C {gnd.sym} 510 -340 0 0 {name=l16 lab=0}
|
||||
C {gnd.sym} 430 -630 0 0 {name=l17 lab=0}
|
||||
C {lab_wire.sym} 270 -690 0 0 {name=l18 sig_type=std_logic lab=VCC}
|
||||
C {lab_wire.sym} 590 -690 0 0 {name=l19 sig_type=std_logic lab=D}
|
||||
C {lab_wire.sym} 630 -450 0 0 {name=l20 sig_type=std_logic lab=B}
|
||||
C {lab_wire.sym} 730 -410 0 0 {name=l21 sig_type=std_logic lab=E}
|
||||
C {opin.sym} 930 -500 0 0 {name=p2 lab=OUT}
|
||||
C {lab_wire.sym} 690 -510 0 0 {name=l22 sig_type=std_logic lab=C}
|
||||
C {lab_pin.sym} 190 -450 0 0 {name=l23 sig_type=std_logic lab=IN}
|
||||
C {ammeter.sym} 570 -450 3 0 {name=v3 current=8.9002e-05}
|
||||
C {ammeter.sym} 510 -600 0 0 {name=v4 current=0.001414}
|
||||
C {ammeter.sym} 690 -580 0 0 {name=v5 current=0.01657}
|
||||
C {spice_probe.sym} 860 -500 0 0 {name=p1 analysis=tran voltage=0.0000e+00}
|
||||
C {spice_probe.sym} 710 -500 0 0 {name=p3 analysis=tran voltage=6.533}
|
||||
C {spice_probe.sym} 190 -690 0 0 {name=p4 analysis=tran voltage=12}
|
||||
C {spice_probe.sym} 210 -450 0 0 {name=p5 analysis=tran voltage=0.0000e+00}
|
||||
C {spice_probe.sym} 630 -450 0 0 {name=p6 analysis=tran voltage=2.385}
|
||||
C {spice_probe.sym} 750 -410 0 0 {name=p7 analysis=tran voltage=1.666}
|
||||
C {spice_probe.sym} 470 -690 0 0 {name=p8 analysis=tran voltage=12}
|
||||
C {ind.sym} 190 -750 1 0 {name=l1 value=10uH}
|
||||
C {vsource.sym} 40 -700 0 0 {name=v1 value=12}
|
||||
C {gnd.sym} 40 -670 0 0 {name=l11 lab=0}
|
||||
C {capa.sym} 280 -720 0 1 {name=C4 m=1 value=100nF footprint=1206 device="ceramic capacitor"}
|
||||
C {res.sym} 360 -560 0 0 {name=R1 value=6.8k footprint=1206 device=resistor m=1}
|
||||
C {npn.sym} 520 -510 0 0 {name=Q2 model=Q2N2219A device=Q2N5179 footprint=SOT23 area=1}
|
||||
C {res.sym} 360 -430 0 0 {name=R2 value=1.8k footprint=1206 device=resistor m=1}
|
||||
C {capa.sym} 630 -560 1 1 {name=C5 m=1 value=1nF footprint=1206 device="ceramic capacitor"}
|
||||
C {res.sym} 690 -470 0 0 {name=R3 value=120k footprint=1206 device=resistor m=1}
|
||||
C {gnd.sym} 690 -440 0 0 {name=l12 lab=0}
|
||||
C {res.sym} 540 -430 0 0 {name=R4 value=100 footprint=1206 device=resistor m=1}
|
||||
C {gnd.sym} 540 -400 0 0 {name=l13 lab=0}
|
||||
C {capa.sym} 240 -510 1 1 {name=C6 m=1 value=1nF footprint=1206 device="ceramic capacitor"}
|
||||
C {vsource.sym} 40 -450 0 0 {name=v2 value="dc 0 ac 1"}
|
||||
C {gnd.sym} 40 -420 0 0 {name=l14 lab=0}
|
||||
C {res.sym} 540 -700 0 0 {name=R5 value=330 footprint=1206 device=resistor m=1}
|
||||
C {capa.sym} 630 -430 0 1 {name=C7 m=1 value=100nF footprint=1206 device="ceramic capacitor"}
|
||||
C {gnd.sym} 630 -400 0 0 {name=l15 lab=0}
|
||||
C {gnd.sym} 360 -400 0 0 {name=l16 lab=0}
|
||||
C {gnd.sym} 280 -690 0 0 {name=l17 lab=0}
|
||||
C {lab_wire.sym} 120 -750 0 0 {name=l18 sig_type=std_logic lab=VCC}
|
||||
C {lab_wire.sym} 440 -750 0 0 {name=l19 sig_type=std_logic lab=D}
|
||||
C {lab_wire.sym} 480 -510 0 0 {name=l20 sig_type=std_logic lab=B}
|
||||
C {lab_wire.sym} 580 -470 0 0 {name=l21 sig_type=std_logic lab=E}
|
||||
C {opin.sym} 740 -560 0 0 {name=p2 lab=OUT}
|
||||
C {lab_wire.sym} 540 -570 0 0 {name=l22 sig_type=std_logic lab=C}
|
||||
C {lab_pin.sym} 40 -510 0 0 {name=l23 sig_type=std_logic lab=IN}
|
||||
C {ammeter.sym} 420 -510 3 0 {name=v3 current=8.9002e-05}
|
||||
C {ammeter.sym} 360 -660 0 0 {name=v4 current=0.001414}
|
||||
C {ammeter.sym} 540 -640 0 0 {name=v5 current=0.01657}
|
||||
C {spice_probe.sym} 710 -560 0 0 {name=p1 analysis=tran voltage=0.0000e+00}
|
||||
C {spice_probe.sym} 560 -560 0 0 {name=p3 analysis=tran voltage=6.533}
|
||||
C {spice_probe.sym} 40 -750 0 0 {name=p4 analysis=tran voltage=12}
|
||||
C {spice_probe.sym} 60 -510 0 0 {name=p5 analysis=tran voltage=0.0000e+00}
|
||||
C {spice_probe.sym} 480 -510 0 0 {name=p6 analysis=tran voltage=2.385}
|
||||
C {spice_probe.sym} 600 -470 0 0 {name=p7 analysis=tran voltage=1.666}
|
||||
C {spice_probe.sym} 320 -750 0 0 {name=p8 analysis=tran voltage=12}
|
||||
C {launcher.sym} 1010 -80 0 0 {name=h5
|
||||
descr="load waves"
|
||||
tclcommand="xschem raw_read $netlist_dir/amp_xschem.raw ac"
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue