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xschem
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add lvs_ignore to context saved vars. Refactored some preprocessor macros SPICE_IGNORE_INST --> SPICE_IGNORE)

This commit is contained in:
stefan schippers 2023-06-06 23:38:29 +02:00
parent b6e9ab33cc
commit 38a28a3acb
10 changed files with 97 additions and 82 deletions
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16
src/actions.c
View File

@ -693,16 +693,16 @@ int set_sym_flags(xSymbol *sym)
sym->flags |= HIDE_INST;
if(!strcmp(get_tok_value(sym->prop_ptr,"spice_ignore",0), "true"))
sym->flags |= SPICE_IGNORE_INST;
sym->flags |= SPICE_IGNORE;
if(!strcmp(get_tok_value(sym->prop_ptr,"verilog_ignore",0), "true"))
sym->flags |= VERILOG_IGNORE_INST;
sym->flags |= VERILOG_IGNORE;
if(!strcmp(get_tok_value(sym->prop_ptr,"vhdl_ignore",0), "true"))
sym->flags |= VHDL_IGNORE_INST;
sym->flags |= VHDL_IGNORE;
if(!strcmp(get_tok_value(sym->prop_ptr,"tedax_ignore",0), "true"))
sym->flags |= TEDAX_IGNORE_INST;
sym->flags |= TEDAX_IGNORE;
if(!strcmp(get_tok_value(sym->prop_ptr,"lvs_ignore",0), "short"))
sym->flags |= LVS_IGNORE_SHORT;
@ -729,13 +729,13 @@ int set_inst_flags(xInstance *inst)
inst->flags |= HIDE_INST;
if(!strcmp(get_tok_value(inst->prop_ptr,"spice_ignore",0), "true"))
inst->flags |= SPICE_IGNORE_INST;
inst->flags |= SPICE_IGNORE;
if(!strcmp(get_tok_value(inst->prop_ptr,"verilog_ignore",0), "true"))
inst->flags |= VERILOG_IGNORE_INST;
inst->flags |= VERILOG_IGNORE;
if(!strcmp(get_tok_value(inst->prop_ptr,"vhdl_ignore",0), "true"))
inst->flags |= VHDL_IGNORE_INST;
inst->flags |= VHDL_IGNORE;
if(!strcmp(get_tok_value(inst->prop_ptr,"tedax_ignore",0), "true"))
inst->flags |= TEDAX_IGNORE_INST;
inst->flags |= TEDAX_IGNORE;
if(!strcmp(get_tok_value(inst->prop_ptr,"hide_texts",0), "true"))
inst->flags |= HIDE_SYMBOL_TEXTS;

16
src/draw.c
View File

@ -449,32 +449,32 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
(
xctx->netlist_type == CAD_SPICE_NETLIST &&
(
(xctx->inst[n].flags & SPICE_IGNORE_INST) ||
(xctx->sym[xctx->inst[n].ptr].flags & SPICE_IGNORE_INST)
(xctx->inst[n].flags & SPICE_IGNORE) ||
(xctx->sym[xctx->inst[n].ptr].flags & SPICE_IGNORE)
)
) ||
(
xctx->netlist_type == CAD_VERILOG_NETLIST &&
(
(xctx->inst[n].flags & VERILOG_IGNORE_INST) ||
(xctx->sym[xctx->inst[n].ptr].flags & VERILOG_IGNORE_INST)
(xctx->inst[n].flags & VERILOG_IGNORE) ||
(xctx->sym[xctx->inst[n].ptr].flags & VERILOG_IGNORE)
)
) ||
(
xctx->netlist_type == CAD_VHDL_NETLIST &&
(
(xctx->inst[n].flags & VHDL_IGNORE_INST) ||
(xctx->sym[xctx->inst[n].ptr].flags & VHDL_IGNORE_INST)
(xctx->inst[n].flags & VHDL_IGNORE) ||
(xctx->sym[xctx->inst[n].ptr].flags & VHDL_IGNORE)
)
) ||
(
xctx->netlist_type == CAD_TEDAX_NETLIST &&
(
(xctx->inst[n].flags & TEDAX_IGNORE_INST) ||
(xctx->sym[xctx->inst[n].ptr].flags & TEDAX_IGNORE_INST)
(xctx->inst[n].flags & TEDAX_IGNORE) ||
(xctx->sym[xctx->inst[n].ptr].flags & TEDAX_IGNORE)
)
) ||
(

24
src/netlist.c
View File

@ -895,20 +895,20 @@ static int instcheck(int n, int p)
if(!inst[n].node) return 0;
if( xctx->netlist_type == CAD_VERILOG_NETLIST &&
((inst[n].flags & VERILOG_IGNORE_INST) ||
(k >= 0 && (sym[k].flags & VERILOG_IGNORE_INST))) ) return 0;
((inst[n].flags & VERILOG_IGNORE) ||
(k >= 0 && (sym[k].flags & VERILOG_IGNORE))) ) return 0;
if( xctx->netlist_type == CAD_SPICE_NETLIST &&
((inst[n].flags & SPICE_IGNORE_INST) ||
(k >= 0 && (sym[k].flags & SPICE_IGNORE_INST))) ) return 0;
((inst[n].flags & SPICE_IGNORE) ||
(k >= 0 && (sym[k].flags & SPICE_IGNORE))) ) return 0;
if( xctx->netlist_type == CAD_VHDL_NETLIST &&
((inst[n].flags & VHDL_IGNORE_INST) ||
(k >= 0 &&(sym[k].flags & VHDL_IGNORE_INST))) ) return 0;
((inst[n].flags & VHDL_IGNORE) ||
(k >= 0 &&(sym[k].flags & VHDL_IGNORE))) ) return 0;
if( xctx->netlist_type == CAD_TEDAX_NETLIST &&
((inst[n].flags & TEDAX_IGNORE_INST) ||
(k >= 0 && (sym[k].flags & TEDAX_IGNORE_INST))) ) return 0;
((inst[n].flags & TEDAX_IGNORE) ||
(k >= 0 && (sym[k].flags & TEDAX_IGNORE))) ) return 0;
if( netlist_lvs_ignore &&
((inst[n].flags & LVS_IGNORE_OPEN) ||
@ -1052,10 +1052,10 @@ static int name_nodes_of_pins_labels_and_propagate()
if(type && inst[i].node && IS_LABEL_OR_PIN(type) ) { /* instance must have a pin! */
if(for_netlist>0) {
/* 20150918 skip labels / pins if ignore property specified on instance */
if( xctx->netlist_type == CAD_VERILOG_NETLIST && (inst[i].flags & VERILOG_IGNORE_INST)) continue;
if( xctx->netlist_type == CAD_SPICE_NETLIST && (inst[i].flags & SPICE_IGNORE_INST)) continue;
if( xctx->netlist_type == CAD_VHDL_NETLIST && (inst[i].flags & VHDL_IGNORE_INST)) continue;
if( xctx->netlist_type == CAD_TEDAX_NETLIST && (inst[i].flags & TEDAX_IGNORE_INST)) continue;
if( xctx->netlist_type == CAD_VERILOG_NETLIST && (inst[i].flags & VERILOG_IGNORE)) continue;
if( xctx->netlist_type == CAD_SPICE_NETLIST && (inst[i].flags & SPICE_IGNORE)) continue;
if( xctx->netlist_type == CAD_VHDL_NETLIST && (inst[i].flags & VHDL_IGNORE)) continue;
if( xctx->netlist_type == CAD_TEDAX_NETLIST && (inst[i].flags & TEDAX_IGNORE)) continue;
if( netlist_lvs_ignore && (inst[i].flags & LVS_IGNORE_OPEN)) continue;
}
port=0;

14
src/spice_netlist.c
View File

@ -166,7 +166,7 @@ static int spice_netlist(FILE *fd, int spice_stop )
err |= traverse_node_hash(); /* print all warnings about unconnected floatings etc */
for(i=0;i<xctx->instances; ++i) /* print first ipin/opin defs ... */
{
if(skip_instance(i, lvs_ignore, SPICE_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, SPICE_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && IS_PIN(type) ) {
if(top_sub && !flag) {
@ -187,7 +187,7 @@ static int spice_netlist(FILE *fd, int spice_stop )
if(top_sub) fprintf(fd, "\n");
for(i=0;i<xctx->instances; ++i) /* ... then print other lines */
{
if(skip_instance(i, lvs_ignore, SPICE_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, SPICE_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && !IS_LABEL_OR_PIN(type) ) {
@ -278,7 +278,7 @@ int global_spice_netlist(int global) /* netlister driver */
first = 0;
for(i=0;i<xctx->instances; ++i) /* print netlist_commands of top level cell with 'place=header' property */
{
if(skip_instance(i, lvs_ignore, SPICE_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, SPICE_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
my_strdup(_ALLOC_ID_, &place,get_tok_value((xctx->inst[i].ptr+ xctx->sym)->prop_ptr,"place",0));
if( type && !strcmp(type,"netlist_commands") ) {
@ -307,7 +307,7 @@ int global_spice_netlist(int global) /* netlister driver */
/* print top subckt ipin/opins */
for(i=0;i<xctx->instances; ++i) {
if(skip_instance(i, lvs_ignore, SPICE_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, SPICE_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
dbg(1, "global_spice_netlist(): |%s|\n", type);
/*
@ -329,7 +329,7 @@ int global_spice_netlist(int global) /* netlister driver */
for(i=0;i<xctx->instances; ++i) /* print netlist_commands of top level cell with no 'place=end' property
and no place=header */
{
if(skip_instance(i, lvs_ignore, SPICE_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, SPICE_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
my_strdup(_ALLOC_ID_, &place,get_tok_value((xctx->inst[i].ptr+ xctx->sym)->prop_ptr,"place",0));
if( type && !strcmp(type,"netlist_commands") ) {
@ -400,7 +400,7 @@ int global_spice_netlist(int global) /* netlister driver */
get_additional_symbols(1);
for(i=0;i<xctx->symbols; ++i)
{
if(xctx->sym[i].flags & SPICE_IGNORE_INST) continue;
if(xctx->sym[i].flags & SPICE_IGNORE) continue;
if(lvs_ignore && (xctx->sym[i].flags & LVS_IGNORE)) continue;
if(!xctx->sym[i].type) continue;
my_strdup(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
@ -463,7 +463,7 @@ int global_spice_netlist(int global) /* netlister driver */
if(!split_f) {
for(i=0;i<xctx->instances; ++i) /* print netlist_commands of top level cell with 'place=end' property */
{
if(skip_instance(i, lvs_ignore, SPICE_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, SPICE_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
my_strdup(_ALLOC_ID_, &place,get_tok_value((xctx->inst[i].ptr+ xctx->sym)->prop_ptr,"place",0));
if( type && !strcmp(type,"netlist_commands") ) {

6
src/tedax_netlist.c
View File

@ -36,7 +36,7 @@ static int tedax_netlist(FILE *fd, int tedax_stop )
if(!tedax_stop) {
for(i=0;i<xctx->instances; ++i) /* print first ipin/opin defs ... */
{
if(skip_instance(i, lvs_ignore, TEDAX_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, TEDAX_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && IS_PIN(type) ) {
print_tedax_element(fd, i) ; /* this is the element line */
@ -44,7 +44,7 @@ static int tedax_netlist(FILE *fd, int tedax_stop )
}
for(i=0;i<xctx->instances; ++i) /* ... then print other lines */
{
if(skip_instance(i, lvs_ignore, TEDAX_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, TEDAX_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && !IS_LABEL_OR_PIN(type) ) {
@ -204,7 +204,7 @@ int global_tedax_netlist(int global) /* netlister driver */
get_additional_symbols(1);
for(i=0;i<xctx->symbols; ++i)
{
if(xctx->sym[i].flags & TEDAX_IGNORE_INST) continue;
if(xctx->sym[i].flags & TEDAX_IGNORE) continue;
if(lvs_ignore && (xctx->sym[i].flags & LVS_IGNORE)) continue;
if(!xctx->sym[i].type) continue;
my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(tcl_hook2(xctx->sym[i].name), ""));

24
src/verilog_netlist.c
View File

@ -45,7 +45,7 @@ static int verilog_netlist(FILE *fd , int verilog_stop)
{
for(i=0;i<xctx->instances; ++i) /* ... print all element except ipin opin labels use package */
{
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
dbg(2, "verilog_netlist(): into the netlisting loop\n");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type &&
@ -129,7 +129,7 @@ int global_verilog_netlist(int global) /* netlister driver */
fmt_attr = xctx->format ? xctx->format : "verilog_format";
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
{
@ -159,7 +159,7 @@ int global_verilog_netlist(int global) /* netlister driver */
tmp=0;
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"opin"))==0)
{
@ -173,7 +173,7 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level inout pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"iopin"))==0)
{
@ -187,7 +187,7 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level input pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"ipin"))==0)
{
@ -215,7 +215,7 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level out pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"opin"))==0)
{
@ -234,7 +234,7 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level inout pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"iopin"))==0)
{
@ -253,7 +253,7 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level input pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"ipin"))==0)
{
@ -275,7 +275,7 @@ int global_verilog_netlist(int global) /* netlister driver */
fprintf(fd,"---- begin user architecture code\n");
for(i=0;i<xctx->instances; ++i) {
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if(type && !strcmp(type,"netlist_commands")) {
fprintf(fd, "%s\n", get_tok_value(xctx->inst[i].prop_ptr,"value", 0));
@ -329,7 +329,7 @@ int global_verilog_netlist(int global) /* netlister driver */
get_additional_symbols(1);
for(i=0;i<xctx->symbols; ++i)
{
if(xctx->sym[i].flags & VERILOG_IGNORE_INST) continue;
if(xctx->sym[i].flags & VERILOG_IGNORE) continue;
if(lvs_ignore && (xctx->sym[i].flags & LVS_IGNORE)) continue;
if(!xctx->sym[i].type) continue;
my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(tcl_hook2(xctx->sym[i].name), ""));
@ -459,7 +459,7 @@ int verilog_block_netlist(FILE *fd, int i)
fmt_attr = xctx->format ? xctx->format : "verilog_format";
for(j=0;j<xctx->instances; ++j)
{
if(skip_instance(j, lvs_ignore, VERILOG_IGNORE_INST)) continue;
if(skip_instance(j, lvs_ignore, VERILOG_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[j].ptr+ xctx->sym)->type);
if( type && ( strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
{
@ -559,7 +559,7 @@ int verilog_block_netlist(FILE *fd, int i)
err |= verilog_netlist(fd, verilog_stop);
fprintf(fd,"---- begin user architecture code\n");
for(l=0;l<xctx->instances; ++l) {
if(skip_instance(l, lvs_ignore, VERILOG_IGNORE_INST)) continue;
if(skip_instance(l, lvs_ignore, VERILOG_IGNORE)) continue;
if(xctx->netlist_count &&
!strcmp(get_tok_value(xctx->inst[l].prop_ptr, "only_toplevel", 0), "true")) continue;

34
src/vhdl_netlist.c
View File

@ -39,7 +39,7 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
fprintf(fd, "//// begin user declarations\n");
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore, VHDL_IGNORE_INST)) continue;
if(skip_instance(l, lvs_ignore, VHDL_IGNORE)) continue;
if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
if(!strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "arch_declarations") )
@ -55,7 +55,7 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
fprintf(fd, "//// begin user attributes\n");
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore, VHDL_IGNORE_INST)) continue;
if(skip_instance(l, lvs_ignore, VHDL_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[l].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"attributes"))==0)
{
@ -70,7 +70,7 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
{
for(i=0;i<xctx->instances; ++i) /* ... print all element except ipin opin labels use package */
{ /* dont print elements with vhdl_ignore=true set in symbol */
if(skip_instance(i, lvs_ignore, VHDL_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VHDL_IGNORE)) continue;
dbg(2, "vhdl_netlist(): into the netlisting loop\n");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type &&
@ -152,7 +152,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level packages\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VHDL_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VHDL_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"package"))==0)
{
@ -167,7 +167,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level use statements\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VHDL_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VHDL_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"use"))==0)
{
@ -232,7 +232,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
tmp=0;
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VHDL_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VHDL_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(xctx->inst[i].prop_ptr,"sig_type",0));
if(!sig_type || sig_type[0]=='\0') my_strdup(_ALLOC_ID_, &sig_type,"std_logic");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
@ -249,7 +249,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level inout pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VHDL_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VHDL_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(xctx->inst[i].prop_ptr,"sig_type",0));
if(!sig_type || sig_type[0]=='\0') my_strdup(_ALLOC_ID_, &sig_type,"std_logic");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
@ -266,7 +266,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level input pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VHDL_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VHDL_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(xctx->inst[i].prop_ptr,"sig_type",0));
if(!sig_type || sig_type[0]=='\0') my_strdup(_ALLOC_ID_, &sig_type,"std_logic");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
@ -284,7 +284,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level port attributes\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VHDL_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VHDL_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"port_attributes"))==0)
{
@ -304,7 +304,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
for(j=0;j<xctx->symbols; ++j)
{
if( strcmp(get_tok_value(xctx->sym[j].prop_ptr,"vhdl_primitive",0),"true")==0 ) continue;
if(xctx->sym[j].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[j].flags & VHDL_IGNORE) continue;
if(lvs_ignore && (xctx->sym[j].flags & LVS_IGNORE)) continue;
if(!xctx->sym[j].type || (strcmp(xctx->sym[j].type,"primitive")!=0 &&
strcmp(xctx->sym[j].type,"subcircuit")!=0)) continue;
@ -363,7 +363,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
fprintf(fd,"//// begin user architecture code\n");
for(i=0;i<xctx->instances; ++i) {
if(skip_instance(i, lvs_ignore, VHDL_IGNORE_INST)) continue;
if(skip_instance(i, lvs_ignore, VHDL_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if(type && !strcmp(type,"netlist_commands")) {
fprintf(fd, "%s\n", get_tok_value(xctx->inst[i].prop_ptr,"value", 0));
@ -417,7 +417,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
get_additional_symbols(1);
for(i=0;i<xctx->symbols; ++i)
{
if(xctx->sym[i].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[i].flags & VHDL_IGNORE) continue;
if(lvs_ignore && (xctx->sym[i].flags & LVS_IGNORE)) continue;
if(!xctx->sym[i].type) continue;
my_strdup(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
@ -539,7 +539,7 @@ int vhdl_block_netlist(FILE *fd, int i)
dbg(1, "vhdl_block_netlist(): packages\n");
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore, VHDL_IGNORE_INST)) continue;
if(skip_instance(l, lvs_ignore, VHDL_IGNORE)) continue;
if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
if( !strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "package") )
fprintf(fd, "%s\n", xctx->inst[l].prop_ptr);
@ -548,7 +548,7 @@ int vhdl_block_netlist(FILE *fd, int i)
dbg(1, "vhdl_block_netlist(): use statements\n");
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore, VHDL_IGNORE_INST)) continue;
if(skip_instance(l, lvs_ignore, VHDL_IGNORE)) continue;
if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
if( !strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "use") )
fprintf(fd, "%s\n", xctx->inst[l].prop_ptr);
@ -590,7 +590,7 @@ int vhdl_block_netlist(FILE *fd, int i)
dbg(1, "vhdl_block_netlist(): port attributes\n");
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore, VHDL_IGNORE_INST)) continue;
if(skip_instance(l, lvs_ignore, VHDL_IGNORE)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[l].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"port_attributes"))==0)
{
@ -625,7 +625,7 @@ int vhdl_block_netlist(FILE *fd, int i)
found=0;
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore, VHDL_IGNORE_INST)) continue;
if(skip_instance(l, lvs_ignore, VHDL_IGNORE)) continue;
if(!xctx->x_strcmp(xctx->sym[j].name, tcl_hook2(xctx->inst[l].name)))
{
found=1; break;
@ -671,7 +671,7 @@ int vhdl_block_netlist(FILE *fd, int i)
fprintf(fd,"//// begin user architecture code\n");
for(l=0;l<xctx->instances; ++l) {
if(skip_instance(l, lvs_ignore, VHDL_IGNORE_INST)) continue;
if(skip_instance(l, lvs_ignore, VHDL_IGNORE)) continue;
if(xctx->netlist_count &&
!strcmp(get_tok_value(xctx->inst[l].prop_ptr, "only_toplevel", 0), "true")) continue;

30
src/xschem.h
View File

@ -171,14 +171,18 @@ extern char win_temp_dir[PATH_MAX];
#define PIN_OR_LABEL 2 /* symbol represents a pin or a label */
#define HILIGHT_CONN 4 /* used to hilight instances if connected wire is hilighted */
#define HIDE_INST 8 /* will only show a bounding box for specific symbol instance */
#define SPICE_IGNORE_INST 16
#define VERILOG_IGNORE_INST 32
#define VHDL_IGNORE_INST 64
#define TEDAX_IGNORE_INST 128
#define SPICE_IGNORE 16
#define VERILOG_IGNORE 32
#define VHDL_IGNORE 64
#define TEDAX_IGNORE 128
#define IGNORE_INST 256
#define HIDE_SYMBOL_TEXTS 512
#define LVS_IGNORE_SHORT 1024 /* flag set if inst/symbol has lvs_ignore=short */
#define LVS_IGNORE_OPEN 2048 /* flag set if inst/symbol has lvs_ignore=open */
#define SPICE_SHORT 4096
#define VERILOG_SHORT 8192
#define VHDL_SHORT 16384
#define TEDAX_SHORT 32768
#define LVS_IGNORE (LVS_IGNORE_SHORT | LVS_IGNORE_OPEN)
#define CADMAXGRIDPOINTS 512
#define CADMAXHIER 40
@ -547,10 +551,10 @@ typedef struct
* bit 1: **free**
* bit 2: HILIGHT_CONN, highlight if connected net/label is highlighted
* bit 3: HIDE_INST, hidden instance, show only bounding box (hide=true attribute)
* bit 4: SPICE_IGNORE_INST, spice_ignore=true
* bit 5: VERILOG_IGNORE_INST, verilog_ignore=true
* bit 6: VHDL_IGNORE_INST, vhdl_ignore=true
* bit 7: TEDAX_IGNORE_INST, tedax_ignore=true
* bit 4: SPICE_IGNORE, spice_ignore=true
* bit 5: VERILOG_IGNORE, verilog_ignore=true
* bit 6: VHDL_IGNORE, vhdl_ignore=true
* bit 7: TEDAX_IGNORE, tedax_ignore=true
* bit 8: IGNORE_INST, instance must be ignored based on *_ignore=true and netlisting mode.
* used in draw.c
* bit 9: HIDE_SYMBOL_TEXTS, hide_texts=true on instance (not used in symbol, but keep free)
@ -579,16 +583,16 @@ typedef struct
short sel;
short embed; /* cache embed=true|false attribute in prop_ptr */
int color; /* hilight color */
short flags; /* bit 0: skip field, set to 1 while drawing layer 0 if symbol is outside bbox
int flags; /* bit 0: skip field, set to 1 while drawing layer 0 if symbol is outside bbox
* to avoid doing the evaluation again.
* bit 1: flag for different textlayer for pin/labels,
* 1: ordinary symbol, 0: label/pin/show
* bit 2: HILIGHT_CONN, highlight if connected net/label is highlighted
* bit 3: HIDE_INST, hidden instance, show only bounding box (hide=true attribute)
* bit 4: SPICE_IGNORE_INST, spice_ignore=true
* bit 5: VERILOG_IGNORE_INST, verilog_ignore=true
* bit 6: VHDL_IGNORE_INST, vhdl_ignore=true
* bit 7: TEDAX_IGNORE_INST, tedax_ignore=true
* bit 4: SPICE_IGNORE, spice_ignore=true
* bit 5: VERILOG_IGNORE, verilog_ignore=true
* bit 6: VHDL_IGNORE, vhdl_ignore=true
* bit 7: TEDAX_IGNORE, tedax_ignore=true
* bit 8: IGNORE_INST, instance must be ignored based on *_ignore=true and netlisting mode.
* used in draw.c
* bit 9: HIDE_SYMBOL_TEXTS, hide_texts=true (hide_texts=true attribute on instance)

2
src/xschem.tcl
View File

@ -5453,7 +5453,7 @@ set tctx::global_list {
graph_logy graph_rainbow graph_raw_level graph_schname graph_sel_color graph_sel_wave
graph_selected graph_sort graph_unlocked hide_empty_graphs hide_symbols hsize
incr_hilight infowindow_text input_line_cmd input_line_data launcher_default_program
light_colors line_width live_cursor2_backannotate local_netlist_dir
light_colors line_width live_cursor2_backannotate local_netlist_dir lvs_ignore
lvs_netlist measure_text netlist_dir netlist_show
netlist_type no_change_attrs nolist_libs noprint_libs old_selected_tok only_probes path pathlist
persistent_command preserve_unchanged_attrs prev_symbol ps_colors rainbow_colors

13
xschem_library/ngspice/solar_panel.sch
View File

@ -1,4 +1,4 @@
v {xschem version=3.1.0 file_version=1.2
v {xschem version=3.4.0 file_version=1.2
Solar panel simulation.
A Photovoltaic model has been created for this (pv_ngspice.sym)
\{Stefan\}.}
@ -252,6 +252,16 @@ N 770 -1030 890 -1030 {
lab=TRIANG}
N 820 -330 820 -210 {
lab=0}
N 1760 -710 1810 -710 {
lab=#net7}
N 1780 -650 1810 -650 {
lab=#net8}
N 1930 -680 2040 -680 {
lab=#net9}
N 1770 -650 1780 -650 {
lab=#net8}
N 1770 -650 1770 -520 {
lab=#net8}
C {title.sym} 160 -40 0 0 {name=l1 author="Stefan Schippers" net_name=true}
C {code_shown.sym} 170 -310 0 0 {name=CONTROL
value="tcleval(
@ -354,3 +364,4 @@ C {lab_pin.sym} 160 -450 0 0 {name=l20 lab=SUN }
C {spice_probe.sym} 850 -1030 0 1 {name=p4 analysis=tran}
C {spice_probe.sym} 810 -890 0 1 {name=p5 analysis=tran}
C {spice_probe.sym} 760 -670 0 0 {name=p6 analysis=tran}
C {comp_ngspice.sym} 1870 -680 0 0 {name=x5 OFFSET=0.5 AMPLITUDE=1 ROUT=7k COUT=1n}