added comp_65nm_read.sym example in inst_sch_select/inst_sch_select.sch, symbol with spice_sym_def attribute
This commit is contained in:
stefan schippers
parent
89d847fb62
commit
eca52e1f4a
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@ -6133,7 +6133,7 @@ proc build_widgets { {topwin {} } } {
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-variable compare_sch \
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-accelerator {Alt-X}
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$topwin.menubar.hilight.menu add command \
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-label {Highlight net-pin name mismatches on selected instances} \
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-label {Highlight net-pin mismatches on sel. instances} \
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-command "xschem net_pin_mismatch" \
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-accelerator {Shift-X}
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$topwin.menubar.hilight.menu add command -label {Highlight duplicate instance names} \
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@ -0,0 +1,6 @@
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* comp_65nm_read.cir
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.subckt comp_65nm_read PLUS OUT MINUS
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v1 x 0 1.1
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e1 out x plus minus 0.5
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.ends
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@ -0,0 +1,24 @@
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v {xschem version=3.4.0 file_version=1.2
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}
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G {}
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K {type=subcircuit
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format="@name @pinlist @symname"
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template="name=x1"
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spice_sym_def="tcleval([read_data_nonewline [abs_sym_path comp_65nm_read.cir]])"}
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V {}
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S {}
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E {}
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L 4 -40 -50 -40 50 {}
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L 4 40 0 60 0 {}
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L 4 -60 30 -40 30 {}
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L 4 -40 -50 40 0 {}
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L 4 -40 50 40 0 {}
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L 4 -60 -30 -40 -30 {}
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B 5 -62.5 -32.5 -57.5 -27.5 {name=PLUS dir=in }
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B 5 57.5 -2.5 62.5 2.5 {name=OUT dir=out }
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B 5 -62.5 27.5 -57.5 32.5 {name=MINUS dir=in }
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T {@symname} -32 44 0 0 0.3 0.3 {}
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T {@name} -10 -48.25 0 0 0.2 0.2 {}
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T {PLUS} -38.75 -30.25 0 0 0.2 0.2 {}
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T {OUT} 28.75 -5.25 0 1 0.2 0.2 {}
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T {MINUS} -38.75 18.5 0 0 0.2 0.2 {}
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@ -1,11 +1,11 @@
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v {xschem version=3.1.0 file_version=1.2
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v {xschem version=3.4.0 file_version=1.2
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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B 2 710 -590 1510 -190 {flags=graph
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B 2 710 -620 1510 -220 {flags=graph
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y1=-0.013
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y2=2.1
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ypos1=0
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@ -13,22 +13,23 @@ ypos2=2
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divy=5
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subdivy=1
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unity=1
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x1=0
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x2=5e-08
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x1=-2.5e-09
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x2=4.75e-08
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divx=5
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subdivx=1
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node="out1
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out2
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out3
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out4
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out5"
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color="7 8 9 10 11"
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out5
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out6"
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color="7 8 9 10 11 12"
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dataset=-1
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unitx=1
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logx=0
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logy=0
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hilight_wave=-1}
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B 2 710 -910 1510 -590 {flags=graph
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B 2 710 -940 1510 -620 {flags=graph
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y1=-0.013
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y2=2.1
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ypos1=0
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@ -36,8 +37,8 @@ ypos2=2
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divy=5
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subdivy=1
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unity=1
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x1=0
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x2=5e-08
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x1=-2.5e-09
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x2=4.75e-08
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divx=5
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subdivx=1
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node="plus
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@ -49,35 +50,38 @@ logx=0
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logy=0
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hilight_wave=-1}
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T {Default instance:
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Uses comp_65nm.sch} 10 -900 0 0 0.4 0.4 { layer=7}
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Uses comp_65nm.sch} 10 -930 0 0 0.4 0.4 { layer=7}
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T {Alternate instance:
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Uses comp_65nm_parax.sch} 10 -690 0 0 0.4 0.4 { layer=8}
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Uses comp_65nm_parax.sch} 10 -720 0 0 0.4 0.4 { layer=8}
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T {Alternate instance:
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Uses comp_65nm_pex
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contained in attribute
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spice_sym_def
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No schematic used} 10 -490 0 0 0.4 0.4 {}
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No schematic used} 10 -520 0 0 0.4 0.4 {}
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T {Alternate instance:
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Uses comp_65nm_empty.sch
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netlist embedded in global
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spice schematic attribute} 340 -890 0 0 0.4 0.4 { layer=10}
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spice schematic attribute} 340 -920 0 0 0.4 0.4 { layer=10}
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T {Alternate instance:
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Uses spice_sym_def to read in
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file comp_65nm_file.cir
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no schematic used} 340 -590 0 0 0.4 0.4 { layer=11}
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no schematic used} 340 -620 0 0 0.4 0.4 { layer=11}
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T {The same symbol is simulated with 5 different implementations
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using instance 'schematic' and 'spice_sym_def' attributes} 190 -1010 0 0 0.6 0.6 { layer=4 slant=oblique}
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T {Instance based implementation selection.} 250 -1070 0 0 0.8 0.8 {}
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C {comp_65nm.sym} 180 -790 0 0 {name=x1}
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C {lab_pin.sym} 120 -820 0 0 {name=p1 lab=PLUS}
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C {lab_pin.sym} 240 -790 0 1 {name=p2 lab=OUT1}
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C {lab_pin.sym} 120 -760 0 0 {name=p3 lab=MINUS}
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C {comp_65nm.sym} 180 -580 0 0 {name=x2
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using instance 'schematic' and 'spice_sym_def' attributes} 190 -1040 0 0 0.6 0.6 { layer=4 slant=oblique}
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T {Instance based implementation selection.} 250 -1100 0 0 0.8 0.8 {}
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T {comp_65nm_read.sym:
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symbol has "spice_sym_def"
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attribute and reads in a file} 340 -360 0 0 0.4 0.4 { layer=12}
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C {comp_65nm.sym} 180 -820 0 0 {name=x1}
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C {lab_pin.sym} 120 -850 0 0 {name=p1 lab=PLUS}
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C {lab_pin.sym} 240 -820 0 1 {name=p2 lab=OUT1}
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C {lab_pin.sym} 120 -790 0 0 {name=p3 lab=MINUS}
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C {comp_65nm.sym} 180 -610 0 0 {name=x2
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schematic=comp_65nm_parax.sch}
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C {lab_pin.sym} 120 -610 0 0 {name=p4 lab=PLUS}
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C {lab_pin.sym} 240 -580 0 1 {name=p5 lab=OUT2}
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C {lab_pin.sym} 120 -550 0 0 {name=p6 lab=MINUS}
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C {comp_65nm.sym} 180 -310 0 0 {name=x3
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C {lab_pin.sym} 120 -640 0 0 {name=p4 lab=PLUS}
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C {lab_pin.sym} 240 -610 0 1 {name=p5 lab=OUT2}
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C {lab_pin.sym} 120 -580 0 0 {name=p6 lab=MINUS}
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C {comp_65nm.sym} 180 -340 0 0 {name=x3
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schematic=comp_65nm_pex
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spice_sym_def=".subckt comp_65nm_pex PLUS OUT MINUS
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** parasitic netlist
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@ -109,9 +113,9 @@ C2 GN1 0 200f m=1
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verilog_sym_def="verilog stuff"
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vhdl_sym_def="vhdl stuff"}
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C {lab_pin.sym} 120 -340 0 0 {name=p7 lab=PLUS}
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C {lab_pin.sym} 240 -310 0 1 {name=p8 lab=OUT3}
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C {lab_pin.sym} 120 -280 0 0 {name=p9 lab=MINUS}
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C {lab_pin.sym} 120 -370 0 0 {name=p7 lab=PLUS}
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C {lab_pin.sym} 240 -340 0 1 {name=p8 lab=OUT3}
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C {lab_pin.sym} 120 -310 0 0 {name=p9 lab=MINUS}
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C {code.sym} 0 -200 0 0 {name=MODELS only_toplevel=false value="* Beta Version released on 2/22/06
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* PTM 65nm NMOS
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@ -238,31 +242,31 @@ C {code.sym} 0 -200 0 0 {name=MODELS only_toplevel=false value="* Beta Version r
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+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15
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+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1
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"}
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C {vsource.sym} 680 -110 0 0 {name=V1 value=2}
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C {lab_pin.sym} 680 -140 0 0 {name=p21 lab=VCC}
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C {lab_pin.sym} 680 -80 0 0 {name=p10 lab=0}
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C {vsource.sym} 800 -110 0 0 {name=V2 value=1}
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C {lab_pin.sym} 800 -140 0 0 {name=p11 lab=MINUS}
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C {lab_pin.sym} 800 -80 0 0 {name=p12 lab=0}
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C {vsource.sym} 950 -110 0 0 {name=V3 value="pwl 0 0 10n 0 20n 2 30n 2 40n 0"}
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C {lab_pin.sym} 950 -140 0 0 {name=p13 lab=PLUS}
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C {lab_pin.sym} 950 -80 0 0 {name=p14 lab=0}
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C {vsource.sym} 700 -120 0 0 {name=V1 value=2}
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C {lab_pin.sym} 700 -150 0 0 {name=p21 lab=VCC}
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C {lab_pin.sym} 700 -90 0 0 {name=p10 lab=0}
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C {vsource.sym} 820 -120 0 0 {name=V2 value=1}
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C {lab_pin.sym} 820 -150 0 0 {name=p11 lab=MINUS}
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C {lab_pin.sym} 820 -90 0 0 {name=p12 lab=0}
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C {vsource.sym} 970 -120 0 0 {name=V3 value="pwl 0 0 10n 0 20n 2 30n 2 40n 0"}
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C {lab_pin.sym} 970 -150 0 0 {name=p13 lab=PLUS}
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C {lab_pin.sym} 970 -90 0 0 {name=p14 lab=0}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {launcher.sym} 790 -170 0 0 {name=h5
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C {launcher.sym} 820 -190 0 0 {name=h5
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descr="load waves"
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tclcommand="xschem raw_read $netlist_dir/test_instance_schematic_selection.raw tran"
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}
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C {code_shown.sym} 140 -190 0 0 {name=COMMANDS only_toplevel=false value=".control
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C {code_shown.sym} 140 -170 0 0 {name=COMMANDS only_toplevel=false value=".control
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save all
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tran 1n 50n
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write test_instance_schematic_selection.raw
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.endc"}
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C {comp_65nm.sym} 490 -700 0 0 {name=x4
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C {comp_65nm.sym} 490 -730 0 0 {name=x4
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schematic=comp_65nm_empty.sch}
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C {lab_pin.sym} 430 -730 0 0 {name=p15 lab=PLUS}
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C {lab_pin.sym} 550 -700 0 1 {name=p16 lab=OUT4}
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C {lab_pin.sym} 430 -670 0 0 {name=p17 lab=MINUS}
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C {comp_65nm.sym} 490 -420 0 0 {name=x5
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C {lab_pin.sym} 430 -760 0 0 {name=p15 lab=PLUS}
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C {lab_pin.sym} 550 -730 0 1 {name=p16 lab=OUT4}
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C {lab_pin.sym} 430 -700 0 0 {name=p17 lab=MINUS}
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C {comp_65nm.sym} 490 -450 0 0 {name=x5
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schematic=comp_65nm_file
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spice_sym_def="tcleval(
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[read_data_nonewline [abs_sym_path comp_65nm_file.cir]]
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@ -272,6 +276,12 @@ vhdl_sym_def="tcleval(
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[read_data_nonewline [abs_sym_path comp_65nm_file.cir]]
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)"
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tclcommand="textwindow [abs_sym_path comp_65nm_file.cir]"}
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C {lab_pin.sym} 430 -450 0 0 {name=p18 lab=PLUS}
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C {lab_pin.sym} 550 -420 0 1 {name=p19 lab=OUT5}
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C {lab_pin.sym} 430 -390 0 0 {name=p20 lab=MINUS}
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C {lab_pin.sym} 430 -480 0 0 {name=p18 lab=PLUS}
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C {lab_pin.sym} 550 -450 0 1 {name=p19 lab=OUT5}
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C {lab_pin.sym} 430 -420 0 0 {name=p20 lab=MINUS}
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C {comp_65nm_read.sym} 490 -230 0 0 {name=x6
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tclcommand="textwindow [abs_sym_path comp_65nm_read.cir]"}
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C {lab_pin.sym} 430 -260 0 0 {name=p22 lab=PLUS}
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C {lab_pin.sym} 550 -230 0 1 {name=p23 lab=OUT6}
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C {lab_pin.sym} 430 -200 0 0 {name=p24 lab=MINUS}
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