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xschem
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fix a bug in my_mstrcat if an empty string is appended; add resolved_net(n) function that returns the top-most hierarchy name of the net mapping to upper level port connections if any; add xschem resolved_net comand that returns the resolved_net of selected wire/label/pin; add @#n:resolved_net pattern in symbol texts that uses resolved_net

This commit is contained in:
stefan schippers 2023-05-27 11:20:49 +02:00
parent 09a373954f
commit cf61c253c5
18 changed files with 211 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
doc/xschem_man/developer_info.html
View File

@ -482,6 +482,8 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
<li><kbd> abort_operation</kbd></li><pre>
Resets UI state, unselect all and abort any pending operation </pre>
<li><kbd> add_symbol_pin</kbd></li><pre>
@ -758,7 +760,7 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
--&gt; { {Vsw} {plus} {580} {-560} } { {p2} {p} {660} {-440} }
{ {Vpanel1} {minus} {600} {-440} } </pre>
<li><kbd> is_symgen symbol</kbd></li><pre>
tell if 'symbol' is a generator (symbol(param1,param2,...) </pre>
tell if 'symbol' is agenerator (symbol(param1,param2,...) </pre>
<li><kbd> line x1 y1 x2 y2 [pos]</kbd></li><pre>
Place a line on current layer (rectcolor)
if integer number 'pos' is given place line at indicated
@ -967,6 +969,9 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
Example: xschem replace_symbol R3 capa.sym </pre>
<li><kbd> reset_flags</kbd></li><pre>
Reset cached instance and symbol cached flags (inst-&gt;flags, sym-&gt;flags) </pre>
<li><kbd> resolved_net</kbd></li><pre>
returns the topmost full hierarchy name of selected net/pin/label
nets connected to I/O ports are mapped to upper level recursively </pre>
<li><kbd> rotate</kbd></li><pre>
Rotate selected objects around their centers </pre>
<li><kbd> save</kbd></li><pre>
@ -1178,6 +1183,9 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
</ul>
<!-- TCL global variables -->

10
src/actions.c
View File

@ -1695,7 +1695,9 @@ int descend_schematic(int instnumber)
const char *pin_name = get_tok_value(xctx->sym[xctx->inst[n].ptr].rect[PINLAYER][i].prop_ptr,"name",0);
char *pin_node = NULL, *net_node = NULL;
int k, mult, net_mult;
char *single_p = NULL, *single_n = NULL;
char *single_p, *single_n = NULL;
char *p_n_s1 = NULL;
char *p_n_s2 = NULL;
if(!pin_name[0]) continue;
if(!xctx->inst[n].node[i]) continue;
@ -1703,14 +1705,16 @@ int descend_schematic(int instnumber)
my_strdup2(_ALLOC_ID_, &pin_node, expandlabel(pin_name, &mult));
my_strdup2(_ALLOC_ID_, &net_node, expandlabel(xctx->inst[n].node[i], &net_mult));
p_n_s1 = pin_node;
for(k = 1; k<=mult; ++k) {
my_strdup2(_ALLOC_ID_, &single_p, find_nth(pin_node, ",", k));
single_p = my_strtok_r(p_n_s1, ",", "", &p_n_s2);
if(single_p[0] == '#') single_p++;
p_n_s1 = NULL;
my_strdup2(_ALLOC_ID_, &single_n,
find_nth(net_node, ",", ((inst_number - 1) * mult + k - 1) % net_mult + 1));
str_hash_lookup(&xctx->portmap[xctx->currsch + 1], single_p, single_n, XINSERT);
dbg(1, "descend_schematic(): %s: %s ->%s\n", xctx->inst[n].instname, single_p, single_n);
}
if(single_p) my_free(_ALLOC_ID_, &single_p);
if(single_n) my_free(_ALLOC_ID_, &single_n);
my_free(_ALLOC_ID_, &net_node);
my_free(_ALLOC_ID_, &pin_node);

26
src/editprop.c
View File

@ -439,19 +439,21 @@ size_t my_mstrcat(int id, char **str, const char *add, ...)
append_str = add;
do {
if( *str != NULL) {
if(append_str[0]=='\0') continue;
a = strlen(append_str) + 1;
my_realloc(id, str, s + a );
memcpy(*str + s, append_str, a);
s += a - 1;
dbg(3,"my_mstrcat(%d,): reallocated string %s\n", id, *str);
if(append_str[0]) {
a = strlen(append_str) + 1;
my_realloc(id, str, s + a );
memcpy(*str + s, append_str, a);
s += a - 1;
dbg(3,"my_mstrcat(%d,): reallocated string %s\n", id, *str);
}
} else {
if(append_str[0] == '\0') continue;
a = strlen(append_str) + 1;
*str = my_malloc(id, a);
memcpy(*str, append_str, a);
dbg(3,"my_mstrcat(%d,): allocated string %s\n", id, *str);
s = a - 1;
if(append_str[0]) {
a = strlen(append_str) + 1;
*str = my_malloc(id, a);
memcpy(*str, append_str, a);
s = a - 1;
dbg(3,"my_mstrcat(%d,): allocated string %s\n", id, *str);
}
}
append_str = va_arg(args, const char *);
} while(append_str);

83
src/hilight.c
View File

@ -507,6 +507,7 @@ void hilight_parent_pins(void)
for(j=0;j<rects; ++j)
{
char *p_n_s1, *p_n_s2;
if(!xctx->inst[i].node[j]) continue;
my_strdup(_ALLOC_ID_, &net_node, expandlabel(xctx->inst[i].node[j], &net_mult));
dbg(1, "hilight_parent_pins(): net_node=%s\n", net_node);
@ -515,9 +516,12 @@ void hilight_parent_pins(void)
my_strdup(_ALLOC_ID_, &pin_node, expandlabel(pin_name, &mult));
dbg(1, "hilight_parent_pins(): pin_node=%s\n", pin_node);
p_n_s1 = pin_node;
for(k = 1; k<=mult; ++k) {
xctx->currsch++;
entry = bus_hilight_hash_lookup(find_nth(pin_node, ",", k), 0, XLOOKUP);
/* entry = bus_hilight_hash_lookup(find_nth(pin_node, ",", k), 0, XLOOKUP); */
entry = bus_hilight_hash_lookup(my_strtok_r(p_n_s1, ",", "", &p_n_s2), 0, XLOOKUP);
p_n_s1 = NULL;
xctx->currsch--;
if(entry)
{
@ -559,6 +563,7 @@ void hilight_child_pins(void)
for(j=0;j<rects; ++j)
{
char *p_n_s1, *p_n_s2;
dbg(1, "hilight_child_pins(): inst_number=%d\n", inst_number);
if(!xctx->inst[i].node[j]) continue;
@ -568,6 +573,7 @@ void hilight_child_pins(void)
if(!pin_name[0]) continue;
my_strdup(_ALLOC_ID_, &pin_node, expandlabel(pin_name, &mult));
dbg(1, "hilight_child_pins(): pin_node=%s\n", pin_node);
p_n_s1 = pin_node;
for(k = 1; k<=mult; ++k) {
dbg(1, "hilight_child_pins(): looking nth net:%d, k=%d, inst_number=%d, mult=%d\n",
(inst_number-1)*mult+k, k, inst_number, mult);
@ -578,13 +584,16 @@ void hilight_child_pins(void)
((inst_number - 1) * mult + k - 1) % net_mult + 1), 0, XLOOKUP);
xctx->currsch++;
if(entry) {
bus_hilight_hash_lookup(find_nth(pin_node, ",", k), entry->value, XINSERT_NOREPLACE);
/* bus_hilight_hash_lookup(find_nth(pin_node, ",", k), entry->value, XINSERT_NOREPLACE); */
bus_hilight_hash_lookup(my_strtok_r(p_n_s1, ",", "", &p_n_s2), entry->value, XINSERT_NOREPLACE);
/* dbg(1, "hilight_child_pins(): inserting: %s\n", find_nth(pin_node, ",", k)); */
}
else {
bus_hilight_hash_lookup(find_nth(pin_node, ",", k), 0, XDELETE);
/* bus_hilight_hash_lookup(find_nth(pin_node, ",", k), 0, XDELETE); */
bus_hilight_hash_lookup(my_strtok_r(p_n_s1, ",", "", &p_n_s2), 0, XDELETE);
/* dbg(1, "hilight_child_pins(): deleting: %s\n", find_nth(pin_node, ",", k)); */
}
p_n_s1 = NULL;
} /* for(k..) */
}
my_free(_ALLOC_ID_, &pin_node);
@ -1866,6 +1875,74 @@ void select_hilight_net(void)
}
/* returns the full path name of "net" recursively resolving port connections
* propagating lower level nets to upper levels.
* "net" can be a bussed net. */
char *resolved_net(const char *net)
{
char *rnet = NULL;
Str_hashentry *entry;
if(net) {
char *n_s1, *n_s2;
int k, mult;
char *exp_net = NULL;
char *resolved_net;
int level = xctx->currsch;
int start_level;
char *path = xctx->sch_path[level] + 1;
char *path2 = NULL;
char *path2_ptr;
int skip = 0;
start_level = sch_waves_loaded();
if(start_level == -1) start_level = 0;
if(net[0] == '#') net++;
if(path) {
/* skip path components that are above the level where raw file was loaded */
while(*path && skip < start_level) {
if(*path == '.') skip++;
++path;
}
}
dbg(1, "path=%s\n", path);
my_strdup(_ALLOC_ID_, &exp_net, expandlabel(net, &mult));
n_s1 = exp_net;
for(k = 0; k < mult; k++) {
char *net_name = my_strtok_r(n_s1, ",", "", &n_s2);
level = xctx->currsch;
n_s1 = NULL;
resolved_net = net_name;
while(level > start_level) {
entry = str_hash_lookup(&xctx->portmap[level], resolved_net, NULL, XLOOKUP);
if(entry) resolved_net = entry->value;
else break;
level--;
}
my_strdup2(_ALLOC_ID_, &path2, path);
skip = start_level;
path2_ptr = path2;
if(level == start_level) path2_ptr[0] = '\0';
else while(*path2_ptr) {
if(*path2_ptr == '.') skip++;
if(skip == level) {
*(path2_ptr +1) = '\0';
break;
}
path2_ptr++;
}
dbg(1, "path2=%s\n", path2);
dbg(1, "level=%d start_level=%d\n", level, start_level);
my_mstrcat(_ALLOC_ID_, &rnet, path2, resolved_net, NULL);
if(k < mult - 1) my_strcat(_ALLOC_ID_, &rnet, ",");
}
my_free(_ALLOC_ID_, &path2);
my_free(_ALLOC_ID_, &exp_net);
}
return rnet;
}
void draw_hilight_net(int on_window)
{
int save_draw;

40
src/scheduler.c
View File

@ -2928,6 +2928,33 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
Tcl_ResetResult(interp);
}
/* resolved_net
* returns the topmost full hierarchy name of selected net/pin/label
* nets connected to I/O ports are mapped to upper level recursively */
else if(!strcmp(argv[1], "resolved_net"))
{
char *net = NULL;
Tcl_ResetResult(interp);
prepare_netlist_structs(0);
if(xctx->lastsel == 1) {
if(xctx->sel_array[0].type == ELEMENT) {
int n=xctx->sel_array[0].n;
if(xctx->inst[n].ptr >= 0) {
const char *type = xctx->sym[xctx->inst[n].ptr].type;
if(IS_LABEL_SH_OR_PIN(type) && xctx->inst[n].node && xctx->inst[n].node[0]) {
net = xctx->inst[n].node[0];
}
}
} else if(xctx->sel_array[0].type == WIRE) {
int n=xctx->sel_array[0].n;
if(xctx->wire[n].node) {
net = xctx->wire[n].node;
}
}
}
Tcl_AppendResult(interp, resolved_net(net), NULL);
}
/* rotate
* Rotate selected objects around their centers */
else if(!strcmp(argv[1], "rotate"))
@ -3693,20 +3720,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
* testmode */
else if(!strcmp(argv[1], "test"))
{
Str_hashentry *entry;
int level;
Tcl_ResetResult(interp);
if(argc > 2) {
const char *node = argv[2];
level = xctx->currsch;
while(level > 0) {
entry = str_hash_lookup(&xctx->portmap[level], node, NULL, XLOOKUP);
if(entry) node = entry->value;
else break;
level--;
}
Tcl_AppendResult(interp, node, NULL);
}
}
/* toggle_colorscheme

9
src/token.c
View File

@ -3287,6 +3287,15 @@ const char *translate(int inst, const char* s)
my_strdup2(_ALLOC_ID_, &pin_attr_value, "");
}
}
/* @#n:resolved_net attribute (n = pin number or name) will translate to hierarchy-resolved net */
if(!pin_attr_value && !strcmp(pin_attr, "resolved_net")) {
prepare_netlist_structs(0);
my_strdup2(_ALLOC_ID_, &pin_attr_value,
xctx->inst[inst].node && xctx->inst[inst].node[n] ?
resolved_net(xctx->inst[inst].node[n]) : "?");
}
if(!pin_attr_value ) my_strdup(_ALLOC_ID_, &pin_attr_value, "--UNDEF--");
value = pin_attr_value;
/* recognize slotted devices: instname = "U3:3", value = "a:b:c:d" --> value = "c" */

1
src/xschem.h
View File

@ -1502,6 +1502,7 @@ extern int hilight_netname(const char *name);
extern void unhilight_net();
extern void propagate_hilights(int set, int clear, int mode);
extern void select_connected_wires(int stop_at_junction);
extern char *resolved_net(const char *net);
extern void draw_hilight_net(int on_window);
extern void display_hilights(int what, char **str);
extern void redraw_hilights(int clear);

4
xschem_library/devices/iopin.sym
View File

@ -1,10 +1,10 @@
v {xschem version=3.1.0 file_version=1.2
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {type=iopin
format="*.iopin @lab"
template="name=p1 lab=xxx"
}
net_name=true}
V {}
S {}
E {}

4
xschem_library/devices/ipin.sym
View File

@ -1,10 +1,10 @@
v {xschem version=3.1.0 file_version=1.2
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {type=ipin
format="*.ipin @lab"
template="name=p1 lab=xxx"
}
net_name=true}
V {}
S {}
E {}

5
xschem_library/devices/lab_pin.sym
View File

@ -1,9 +1,10 @@
v {xschem version=3.1.0 file_version=1.2
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {type=label
format="*.alias @lab"
template="name=p1 sig_type=std_logic lab=xxx"}
template="name=p1 sig_type=std_logic lab=xxx"
net_name=true}
V {}
S {}
E {}

5
xschem_library/devices/lab_wire.sym
View File

@ -1,9 +1,10 @@
v {xschem version=3.1.0 file_version=1.2
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {type=label
format="*.alias @lab"
template="name=p1 sig_type=std_logic lab=xxx"}
template="name=p1 sig_type=std_logic lab=xxx"
net_name=true}
V {}
S {}
E {}

4
xschem_library/devices/opin.sym
View File

@ -1,10 +1,10 @@
v {xschem version=3.1.0 file_version=1.2
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {type=opin
format="*.opin @lab"
template="name=p1 lab=xxx"
}
net_name=true}
V {}
S {}
E {}

43
xschem_library/inst_sch_select/comp_65nm.sch
View File

@ -1,10 +1,13 @@
v {xschem version=3.1.0 file_version=1.2
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {}
V {}
S {}
E {}
T {( @#0:resolved_net )} 100 -335 0 1 0.2 0.2 {name=p161 layer=15}
T {( @#0:resolved_net )} 100 -285 0 1 0.2 0.2 {name=p1 layer=15}
T {( @#0:resolved_net )} 240 -315 0 1 0.2 0.2 {name=p20 layer=15}
N 590 -150 590 -130 { lab=0}
N 370 -180 550 -180 { lab=GN1}
N 330 -230 330 -210 { lab=GN1}
@ -17,7 +20,7 @@ N 670 -340 670 -300 { lab=#net3}
N 550 -410 550 -380 { lab=#net2}
N 510 -380 550 -380 { lab=#net2}
N 510 -380 510 -340 { lab=#net2}
N 510 -460 510 -440 { lab=#net4}
N 510 -460 510 -440 { lab=VCC}
N 800 -460 800 -400 { lab=VCC}
N 670 -370 760 -370 { lab=#net3}
N 330 -210 370 -210 { lab=GN1}
@ -25,35 +28,35 @@ N 370 -210 370 -180 { lab=GN1}
N 670 -460 670 -440 { lab=VCC}
N 550 -410 640 -410 { lab=#net2}
N 800 -150 800 -130 { lab=0}
N 800 -340 800 -210 { lab=#net5}
N 800 -340 800 -210 { lab=#net4}
N 550 -180 550 -170 { lab=GN1}
N 550 -170 660 -170 { lab=GN1}
N 660 -180 660 -170 { lab=GN1}
N 660 -180 760 -180 { lab=GN1}
N 670 -380 670 -340 { lab=#net3}
N 1130 -290 1170 -290 { lab=OUT}
N 800 -290 870 -290 { lab=#net5}
N 800 -290 870 -290 { lab=#net4}
N 980 -150 980 -130 { lab=0}
N 980 -420 980 -400 { lab=VCC}
N 940 -370 940 -180 { lab=#net5}
N 980 -340 980 -210 { lab=#net6}
N 870 -290 940 -290 { lab=#net5}
N 940 -370 940 -180 { lab=#net4}
N 980 -340 980 -210 { lab=#net5}
N 870 -290 940 -290 { lab=#net4}
N 1130 -150 1130 -130 { lab=0}
N 1130 -420 1130 -400 { lab=VCC}
N 1090 -370 1090 -180 { lab=#net6}
N 1090 -370 1090 -180 { lab=#net5}
N 1130 -340 1130 -210 { lab=OUT}
N 980 -290 1090 -290 { lab=#net6}
N 990 -620 990 -510 { lab=#net6}
N 930 -620 930 -510 { lab=#net5}
N 890 -560 930 -560 { lab=#net5}
N 890 -560 890 -290 { lab=#net5}
N 990 -560 1010 -560 { lab=#net6}
N 1010 -560 1030 -560 { lab=#net6}
N 1030 -560 1030 -290 { lab=#net6}
N 960 -660 990 -660 { lab=#net6}
N 990 -660 990 -620 { lab=#net6}
N 930 -510 930 -470 { lab=#net5}
N 930 -470 960 -470 { lab=#net5}
N 980 -290 1090 -290 { lab=#net5}
N 990 -620 990 -510 { lab=#net5}
N 930 -620 930 -510 { lab=#net4}
N 890 -560 930 -560 { lab=#net4}
N 890 -560 890 -290 { lab=#net4}
N 990 -560 1010 -560 { lab=#net5}
N 1010 -560 1030 -560 { lab=#net5}
N 1030 -560 1030 -290 { lab=#net5}
N 960 -660 990 -660 { lab=#net5}
N 990 -660 990 -620 { lab=#net5}
N 930 -510 930 -470 { lab=#net4}
N 930 -470 960 -470 { lab=#net4}
C {nmos4.sym} 570 -180 0 0 {name=M1 model=nmos w=4u l=0.4u m=1}
C {lab_pin.sym} 590 -180 0 1 {name=p2 lab=0}
C {lab_pin.sym} 590 -130 0 0 {name=p6 lab=0}

6
xschem_library/ngspice/comp_ngspice.sch
View File

@ -1,10 +1,14 @@
v {xschem version=3.1.0 file_version=1.2
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {}
V {}
S {}
E {}
T {( @#0:resolved_net )} 440 -265 0 1 0.2 0.2 {name=l2 layer=15}
T {( @#0:resolved_net )} 100 -285 0 1 0.2 0.2 {name=p1 layer=15}
T {( @#0:resolved_net )} 100 -235 0 1 0.2 0.2 {name=p2 layer=15}
T {( @#0:resolved_net )} 690 -265 0 1 0.2 0.2 {name=p3 layer=15}
N 450 -240 450 -180 { lab=IOUT}
N 450 -240 540 -240 { lab=IOUT}
N 600 -240 680 -240 { lab=OUT}

6
xschem_library/ngspice/opamp_65nm.sch
View File

@ -1,9 +1,13 @@
v {xschem version=3.0.0 file_version=1.2 }
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {}
V {}
S {}
E {}
T {( @#0:resolved_net )} 100 -335 0 1 0.2 0.2 {name=p161 layer=15}
T {( @#0:resolved_net )} 100 -285 0 1 0.2 0.2 {name=p1 layer=15}
T {( @#0:resolved_net )} 240 -315 0 1 0.2 0.2 {name=p20 layer=15}
N 660 -190 660 -170 { lab=0}
N 440 -220 620 -220 { lab=GN1}
N 400 -270 400 -250 { lab=GN1}

10
xschem_library/rom8k/rom2_sa.sym
View File

@ -1,8 +1,10 @@
v {xschem version=2.9.5_RC6 file_version=1.1}
G {type=subcircuit
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
net_name=true}
V {}
S {}
E {}
@ -36,3 +38,5 @@ T {LDPRECH} -125 -4 0 0 0.2 0.2 {}
T {LDSAL} -125 16 0 0 0.2 0.2 {}
T {vcc} -125 36 0 0 0.2 0.2 {}
T {vss} -125 56 0 0 0.2 0.2 {}
T {@#vcc:resolved_net} -100 40 0 0 0.1 0.1 { layer=15}
T {@#vss:resolved_net} -100 60 0 0 0.1 0.1 { layer=15}

10
xschem_library/rom8k/rom2_sacell.sym
View File

@ -1,8 +1,10 @@
v {xschem version=2.9.5_RC6 file_version=1.1}
G {type=subcircuit
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
net_name=true}
V {}
S {}
E {}
@ -33,3 +35,5 @@ T {VSS} -125 26 0 0 0.2 0.2 {}
T {LDQI} 125 -34 0 1 0.2 0.2 {}
T {LDQ_B} 125 -14 0 1 0.2 0.2 {}
T {LDYMS} 125 6 0 1 0.2 0.2 {}
T {@#VCC:resolved_net} -100 10 0 0 0.1 0.1 { layer=15}
T {@#VSS:resolved_net} -100 30 0 0 0.1 0.1 { layer=15}

8
xschem_library/rom8k/rom3_rowdec.sym
View File

@ -1,8 +1,10 @@
v {xschem version=2.9.5 file_version=1.1}
G {type=subcircuit
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
net_name=true}
V {}
S {}
E {}