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add examples/test_bus_tap.sch

This commit is contained in:
stefan schippers 2023-05-22 00:49:54 +02:00
parent 5bd2c624a8
commit a4d5ddb63f
4 changed files with 133 additions and 4 deletions
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2
xschem_library/devices/bus_tap.sym
View File

@ -2,7 +2,7 @@ v {xschem version=3.4.0 file_version=1.2
}
G {}
K {type=show_label
format="* tap: @@bus --> @@tap"
format="* tap: @@bus --> @@lab"
template="name=l1 lab=[0]"}
V {}
S {}

9
xschem_library/examples/0_examples_top.sch
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@ -1,4 +1,4 @@
v {xschem version=3.1.0 file_version=1.2
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {}
@ -88,7 +88,8 @@ N 860 -390 920 -390 {lab=#net2}
N 880 -430 910 -420 {lab=#net1}
N 380 -310 640 -310 {lab=BUS[4:0]}
N 510 -400 510 -320 {lab=BUS[1]}
N 410 -360 410 -320 {lab=BUS[2]}
N 410 -350 410 -320 {lab=BUS[2]}
N 460 -400 460 -320 {lab=BUS[2:1]}
C {poweramp.sym} 480 -690 0 0 {name=x1
tclcommand="xschem descend"}
C {tesla.sym} 160 -570 0 0 {name=x2}
@ -119,7 +120,7 @@ C {rlc.sym} 160 -770 0 0 {name=x0}
C {lab_pin.sym} 640 -310 0 1 {name=l2 sig_type=std_logic lab=BUS[4:0]}
C {bus_connect.sym} 500 -310 0 0 {name=l3 lab=BUS[1]}
C {bus_connect_nolab.sym} 400 -310 0 0 {name=r1}
C {lab_pin.sym} 410 -360 3 1 {name=l4 sig_type=std_logic lab=BUS[2]}
C {lab_pin.sym} 410 -350 3 1 {name=l4 sig_type=std_logic lab=BUS[2]}
C {LCC_instances.sym} 160 -450 0 0 {name=x7}
C {test_backannotated_subckt.sym} 160 -410 0 0 {name=x10}
C {plot_manipulation.sym} 160 -370 0 0 {name=x11}
@ -1470,3 +1471,5 @@ C {poweramp_lcc.sym} 480 -650 0 0 {name=x16
tclcommand="xschem descend"}
C {test_symbolgen.sym} 480 -530 0 0 {name=x18}
C {inst_sch_select.sym} 480 -490 0 0 {name=x24}
C {test_bus_tap.sym} 480 -450 0 0 {name=x22}
C {bus_tap.sym} 450 -310 1 1 {name=l5 lab=[2:1]}

115
xschem_library/examples/test_bus_tap.sch Normal file
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@ -0,0 +1,115 @@
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {}
V {}
S {}
E {}
N 140 -300 880 -300 {bus=true
lab=DATA[15:0]}
N 360 -410 360 -310 {
lab=DATA[3]}
N 250 -410 250 -310 {
lab=DATA[4]}
N 420 -290 420 -210 {
lab=DATA[7:4]}
N 300 -290 300 -210 {
lab=DATA[11:8]}
N 190 -290 190 -210 {
lab=DATA[3:0]}
N 570 -290 570 -210 {
lab=DATA[15:12]}
N 470 -410 470 -310 {
lab=DATA[10]}
N 590 -410 590 -310 {
lab=DATA[0]}
N 590 -480 590 -470 {
lab=VCC}
N 470 -480 470 -470 {
lab=VCC}
N 360 -480 360 -470 {
lab=VCC}
N 250 -480 250 -470 {
lab=VCC}
N 190 -150 190 -140 {
lab=VSS}
N 300 -150 300 -140 {
lab=VSS}
N 420 -150 420 -140 {
lab=VSS}
N 570 -150 570 -140 {
lab=VSS}
C {bus_tap.sym} 370 -300 3 0 {name=l1 lab=[3]}
C {bus_tap.sym} 260 -300 3 0 {name=l2 lab=[4]}
C {bus_tap.sym} 410 -300 1 0 {name=l3 lab=[7:4]}
C {bus_tap.sym} 290 -300 1 0 {name=l4 lab=[11:8]}
C {bus_tap.sym} 180 -300 1 0 {name=l5 lab=[3:0]}
C {bus_tap.sym} 480 -300 3 0 {name=l7 lab=[10]}
C {bus_tap.sym} 600 -300 3 0 {name=l8 lab=[0]}
C {res.sym} 590 -440 0 0 {name=R1
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
C {res.sym} 470 -440 0 0 {name=R2
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
C {res.sym} 360 -440 0 0 {name=R3
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
C {res.sym} 250 -440 0 0 {name=R4
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
C {res.sym} 190 -180 0 0 {name=R5[3:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
C {res.sym} 300 -180 0 0 {name=R6[3:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
C {res.sym} 420 -180 0 0 {name=R7[3:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
C {res.sym} 570 -180 0 0 {name=R8[3:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
C {lab_pin.sym} 140 -300 0 0 {name=p1 sig_type=std_logic lab=DATA[15:0]
}
C {bus_tap.sym} 560 -300 1 0 {name=l6 lab=[15:12]}
C {lab_pin.sym} 250 -480 0 0 {name=p2 sig_type=std_logic lab=VCC
}
C {lab_pin.sym} 360 -480 0 0 {name=p3 sig_type=std_logic lab=VCC
}
C {lab_pin.sym} 470 -480 0 0 {name=p4 sig_type=std_logic lab=VCC
}
C {lab_pin.sym} 590 -480 0 0 {name=p5 sig_type=std_logic lab=VCC
}
C {lab_pin.sym} 190 -140 0 0 {name=p6 sig_type=std_logic lab=VSS
}
C {lab_pin.sym} 300 -140 0 0 {name=p7 sig_type=std_logic lab=VSS
}
C {lab_pin.sym} 420 -140 0 0 {name=p8 sig_type=std_logic lab=VSS
}
C {lab_pin.sym} 570 -140 0 0 {name=p9 sig_type=std_logic lab=VSS
}

11
xschem_library/examples/test_bus_tap.sym Normal file
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@ -0,0 +1,11 @@
v {xschem version=3.4.0 file_version=1.2}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
T {@symname} -72 -6 0 0 0.3 0.3 {}
T {@name} 135 -22 0 0 0.2 0.2 {}
L 4 -130 -10 130 -10 {}
L 4 -130 10 130 10 {}
L 4 -130 -10 -130 10 {}
L 4 130 -10 130 10 {}