disable displaying backannotation data if `b` cursor is hidden or `Simulation->Live annotation with b cursor` is disabled. Use resolved_net() in translate() when displaying @spice_get_voltage so it will work on sub block ports
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1cf0c820f9
commit
4f387f3bbe
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@ -420,7 +420,9 @@ static int waves_callback(int event, int mx, int my, KeySym key, int button, int
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need_all_redraw = 1;
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}
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} else {
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need_all_redraw = 1;
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xctx->graph_annotate_p = -1;
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/* need_all_redraw = 1; */
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redraw_all_at_end = 1;
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}
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}
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/* swap cursors */
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33
src/token.c
33
src/token.c
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@ -3398,13 +3398,16 @@ const char *translate(int inst, const char* s)
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else if(strcmp(token,"@spice_get_voltage")==0 )
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{
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int start_level; /* hierarchy level where waves were loaded */
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if(xctx->graph_annotate_p>=0 && !tclgetboolvar("live_cursor2_backannotate")) {
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xctx->graph_annotate_p = -1;
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}
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if((start_level = sch_waves_loaded()) >= 0 && xctx->graph_annotate_p>=0) {
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int multip;
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int no_of_pins= (xctx->inst[inst].ptr + xctx->sym)->rects[PINLAYER];
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if(no_of_pins == 1) {
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char *fqnet = NULL;
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const char *path = xctx->sch_path[xctx->currsch] + 1;
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const char *net = NULL;
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char *net = NULL;
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size_t len;
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int idx;
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double val;
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@ -3417,14 +3420,19 @@ const char *translate(int inst, const char* s)
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++path;
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}
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prepare_netlist_structs(0);
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net = expandlabel(xctx->inst[inst].lab, &multip);
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if(net == NULL || net[0] == '\0') net = net_name(inst,0, &multip, 0, 0);
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my_strdup2(_ALLOC_ID_, &net, expandlabel(xctx->inst[inst].lab, &multip));
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if(net == NULL || net[0] == '\0') {
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my_strdup2(_ALLOC_ID_, &net, net_name(inst, 0, &multip, 0, 0));
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}
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if(multip == 1) {
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len = strlen(path) + strlen(net) + 1;
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dbg(1, "translate() @spice_get_voltage: inst=%s\n", xctx->inst[inst].instname);
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dbg(1, " net=%s\n", net);
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fqnet = my_malloc(_ALLOC_ID_, len);
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my_snprintf(fqnet, len, "%s%s", path, net);
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/*
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* fqnet = my_malloc(_ALLOC_ID_, len);
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* my_snprintf(fqnet, len, "%s%s", path, net);
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*/
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my_strdup2(_ALLOC_ID_, &fqnet, resolved_net(net));
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strtolower(fqnet);
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dbg(1, "translate() @spice_get_voltage: fqnet=%s start_level=%d\n", fqnet, start_level);
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idx = get_raw_index(fqnet);
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@ -3447,7 +3455,8 @@ const char *translate(int inst, const char* s)
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dbg(1, "inst %d, net=%s, fqnet=%s idx=%d valstr=%s\n", inst, net, fqnet, idx, valstr);
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my_free(_ALLOC_ID_, &fqnet);
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}
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}
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my_free(_ALLOC_ID_, &net);
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}
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}
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}
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}
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@ -3455,6 +3464,9 @@ const char *translate(int inst, const char* s)
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{
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int start_level; /* hierarchy level where waves were loaded */
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dbg(1, "--> %s\n", token);
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if(xctx->graph_annotate_p>=0 && !tclgetboolvar("live_cursor2_backannotate")) {
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xctx->graph_annotate_p = -1;
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}
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if((start_level = sch_waves_loaded()) >= 0 && xctx->graph_annotate_p>=0) {
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char *fqnet = NULL;
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const char *path = xctx->sch_path[xctx->currsch] + 1;
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@ -3509,6 +3521,9 @@ const char *translate(int inst, const char* s)
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else if(strncmp(token,"@spice_get_current(", 19)==0 )
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{
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int start_level; /* hierarchy level where waves were loaded */
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if(xctx->graph_annotate_p>=0 && !tclgetboolvar("live_cursor2_backannotate")) {
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xctx->graph_annotate_p = -1;
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}
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if((start_level = sch_waves_loaded()) >= 0 && xctx->graph_annotate_p>=0) {
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char *fqdev = NULL;
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const char *path = xctx->sch_path[xctx->currsch] + 1;
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@ -3576,6 +3591,9 @@ const char *translate(int inst, const char* s)
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else if(strcmp(token,"@spice_get_diff_voltage")==0 )
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{
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int start_level; /* hierarchy level where waves were loaded */
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if(xctx->graph_annotate_p>=0 && !tclgetboolvar("live_cursor2_backannotate")) {
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xctx->graph_annotate_p = -1;
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}
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if((start_level = sch_waves_loaded()) >= 0 && xctx->graph_annotate_p>=0) {
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int multip;
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int no_of_pins= (xctx->inst[inst].ptr + xctx->sym)->rects[PINLAYER];
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@ -3642,6 +3660,9 @@ const char *translate(int inst, const char* s)
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else if(strcmp(token,"@spice_get_current")==0 )
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{
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int start_level; /* hierarchy level where waves were loaded */
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if(xctx->graph_annotate_p>=0 && !tclgetboolvar("live_cursor2_backannotate")) {
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xctx->graph_annotate_p = -1;
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}
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if((start_level = sch_waves_loaded()) >= 0 && xctx->graph_annotate_p>=0) {
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char *fqdev = NULL;
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const char *path = xctx->sch_path[xctx->currsch] + 1;
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@ -12,3 +12,4 @@ L 5 -0 -0 3.125 0 {}
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B 5 -1.25 -1.25 1.25 1.25 {name=p dir=inout}
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P 5 7 13.75 5 17.5 0 13.75 -5 6.875 -5 3.125 0 6.875 5 13.75 5 {fill=true}
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T {@lab} 19.8438 -9.375 0 0 0.33 0.33 {}
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T {@spice_get_voltage} -1.875 3.90625 0 1 0.2 0.2 {layer=15}
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@ -12,3 +12,4 @@ L 5 -5 0 0 0 {}
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B 5 -1.25 -1.25 1.25 1.25 {name=p dir=out}
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P 5 7 -5 0 -8.75 -5 -17.5 -5 -13.75 0 -17.5 5 -8.75 5 -5 0 {fill=true}
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T {@lab} -18.75 -8.75 0 1 0.33 0.33 {}
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T {@spice_get_voltage} 1.875 3.90625 0 0 0.2 0.2 {layer=15}
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@ -12,3 +12,4 @@ L 5 0 0 8.75 0 {}
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B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
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P 5 7 17.5 0 13.75 -5 5 -5 8.75 0 5 5 13.75 5 17.5 0 {fill=true}
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T {@lab} 20 -8.75 0 0 0.33 0.33 {}
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T {@spice_get_voltage} -1.875 3.90625 0 1 0.2 0.2 {layer=15}
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