f1bf4fdf57
jtag,main,xilinx: fix warnings, lint
2024-03-09 10:21:21 +01:00
6366518ff7
device,ftdiJtagMPSSE,jtag: check/lint happy
2024-03-07 06:58:31 +01:00
6dc2e752f4
ch347jtag: drop unused sync_cb
2024-03-07 06:57:27 +01:00
e299061992
xilinx.cpp: After programming, go to bypass
...
Needed for xc7s50 on VMM3 boards to detect FLASH
2024-03-04 15:33:25 +01:00
bcbd8aa0e3
new board: olimex_gatemateevb Olimex GateMate A1 EVB
2024-03-03 08:25:55 +01:00
645471a16c
spiFlashdb.hpp: Detect N25Q256A.
2024-03-01 13:38:23 +01:00
f57abf9024
Add Trenz TEC0330 board.
2024-03-01 13:38:12 +01:00
88c4d86e63
Add xc7vx330t
2024-03-01 10:50:28 +01:00
ae39b2c556
board.hpp: Add TE0712-8 Board (XC7A200TFBG484)
2024-02-28 22:46:01 +01:00
a2d8bc861f
Merge pull request #437 from UweBonnes/xc6v
...
Add spilOverJtag for Virtex6
2024-02-28 22:03:53 +01:00
4af0bf6ed5
update CH347 ( #424 )
2024-02-28 20:44:49 +01:00
a926ab9b88
Add (Cern) VMM3 board
2024-02-28 11:50:10 +01:00
0e99360d1c
Add (Cern) VEC_V6 Board
2024-02-28 11:50:10 +01:00
354d3f86ab
Virtex6: Add spiOverJtag for Virtex6, detect xc6vlx130 and provide bitfile for xc6vlx130tff784
2024-02-28 11:50:10 +01:00
956d9355a6
Add S25FL128L flash
2024-02-28 11:50:10 +01:00
85d9ca5d20
board: added digilent cmoda7_15t
2024-02-26 21:18:33 +01:00
0182d592be
dfu,ftdipp_mpsse: sprintf -> snprintf
2024-02-20 20:59:13 +01:00
3165552994
DFU: fix code to accept tinyDFU implementation (where not altsettings have an DFU descriptor)
2024-02-15 06:45:13 +01:00
ffc519c0e2
lattice: improve info about "BSE Error Code" from Device Status Register
2024-02-13 09:32:30 +01:00
e923ef4059
lattice nexus boards: change from CABLE_DEFAULT (i.e. 6MHz) to CABLE_MHZ(1) (i.e. 1MHz)
...
as at 6MHz the download of bitstreams is not stable.
With "not stable" we mean that:
- when dealing with Certus/Crosslink, most of the times it works
- when dealing with CertusPro devices, most of the times it doesn't work
We think this is due to the size of the bitstream and the way that the
transmission/storing is handled on the receiving side (i.e. the FPGA).
2024-02-13 09:24:47 +01:00
0f9422f09a
latticeBitParser: add support for loading Lattice (Nexus) encrypted bitstreams,
...
by adding key and preamble of encrypted bitstreams to if statements.
2024-02-13 09:22:34 +01:00
daa1e38799
xvc client: handle failed ll_write()
...
Avoids "Send instruction failed" in a tight loop...
2024-02-11 14:25:00 -08:00
4c737b2b96
xvc client ensure send() entire buffer
2024-02-11 14:25:00 -08:00
39be00fd56
Merge pull request #427 from jgroman/master
...
Fix Tang Primer 25K SRAM loading when flash is erased
2024-02-02 13:09:45 +01:00
eba9c37027
Fix SRAM loading on invalid flash
2024-02-02 12:54:17 +01:00
fc58ffed38
Update spiFlashdb.hpp for Macronix MX25L3233F used on Cmod A7-35T
...
Digilent changed from Micron N25Q032A to Macronix MX25L3233F in 2020/2021, so this flash is needed in openfpgaloader to load to Cmod A7-35T
2024-02-01 19:48:21 +01:00
f9c1aa4eed
Merge pull request #423 from jgroman/master
...
Add faulty MPSEE cmd 8E workaround
2024-01-29 07:17:50 +01:00
33eaf58869
Add faulty MPSEE cmd 8E workaround
2024-01-27 13:02:46 +01:00
1aaa1b37ac
board: add Antmicro LPDDR4 Tester board
...
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2024-01-25 12:29:12 +01:00
59f5759888
board: add Antmicro DDR5 Tester board
...
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2024-01-25 12:25:07 +01:00
17939d587e
board: add Antmicro DDR4 Tester board
...
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2024-01-25 12:23:27 +01:00
308e47c5c0
Merge pull request #420 from sean-anderson-seco/xilinx-ids
...
xilinx: Add remaining ZynqMP IDs
2024-01-19 07:25:54 +01:00
da0f6f6f2a
xilinx: Add remaining ZynqMP IDs
...
The IDs were taken from UG1085 v2.2 table 1-2.
2024-01-18 14:50:23 -05:00
9943c3072a
lattice: Add all MachXO[23] part IDs
...
The version field is the only difference between many parts in the
MachXO[23] family, including between different families. Add the version
field to all parts, fixing detection of some MachXO3 parts as MachXO2s.
The id codes were extracted from the BSDL files on Lattice's website.
2024-01-18 13:48:50 -05:00
4148be3d31
part: 0x012bc043 is for LCMXO2-4000HC
...
I found this when I was trying to program a LCMXO2-4000HC, but
openFPGALoader said it is a LCMX03LF-4300C:
$ openFPGALoader --detect
No cable or board specified: using direct ft2232 interface
Jtag frequency : requested 6.00MHz -> real 6.00MHz
index 0:
idcode 0x12bc043
manufacturer lattice
family MachXO3LF
model LCMX03LF-4300C
irlength 8
From what I found on the internet, the idcode for LCMX03LF-4300C seems
to be 0x612BC043:
https://bsdl.info/details.htm?sid=b483da5dec63d6cd88ca59b002289d77
2024-01-11 10:00:02 +08:00
a3826614b3
gowin: writeFLASH: increase delay before CRC check (required for 9K device)
2024-01-09 19:56:53 +01:00
0b59efcb42
src/gowin: GW5A/SPI flash: adding delay after erase flash and after SPI mode instruction. Seems fixed write error.
2024-01-09 18:48:21 +01:00
62ad3a3003
gowin: fix flash erase for GW1NSR-4C: during shiftDR sequence TDI MUST be 0x0000
2024-01-04 07:24:02 +01:00
c51dbcb0ed
Merge pull request #410 from pu-cc/gatemate-chain-fix
...
gatemate: fix configuration byte alignment in jtag chains
2023-12-27 14:42:29 +01:00
001f20c884
gatemate: use more suitable change to RUN_TEST_IDLE state
2023-12-27 13:38:13 +01:00
8c6c0ee85a
Add WebAssembly support.
2023-12-22 21:07:33 +00:00
bca3bd6623
Use correct format specifier for printing uint64_t.
2023-12-22 21:07:23 +00:00
cd40de37cb
main: allows mcufw only mode for gowin
2023-12-14 13:13:48 +01:00
22f33618b0
gowin: mcufw may be written without fs (but this erase all memory)
2023-12-14 13:13:29 +01:00
2093ce7520
gowin: fix gw1n external flash access
2023-12-14 11:48:14 +01:00
1dbc9e664b
gowin: programFlash/writeFlash: disable previous rewrite (fix write with tangnano4k)
2023-12-14 11:38:34 +01:00
1dfdec6ce1
gatemate: fix configuration in jtag chains
2023-12-12 10:21:30 +01:00
ed547ed893
boards: adding AMD Virtex UltraScale+ FPGA VCU1525 Acceleration Development Kit
2023-12-11 12:23:37 +01:00
d8186c5e8a
gowin: GW5AST work around
2023-12-11 07:20:37 +01:00
1c7a4afd01
ftdipp_mpsse: display/typo
2023-12-11 07:18:02 +01:00
bd917d51ef
gowin: try second eraseSRAM before writeSRAM. Not always working but better...
2023-12-10 08:14:06 +01:00
b70a3991cc
Add pynq-z1 board
2023-12-08 14:51:38 -05:00
2a2435ecbe
board: Xilinx KCU105 (Kintex Ultrascale xcku040)
2023-12-08 16:00:59 +01:00
807d794703
latticeBitParser: add ECP3 VERIFY ID support (avoid to fail with bitstream)
2023-12-08 07:07:35 +01:00
fb587e73d8
gowin: Fix clk cycle after sending a command, don't read status register programSRAM sequence
2023-12-04 07:25:43 +01:00
0dcd851187
gowin: avoid multiple status register access
2023-12-04 07:05:40 +01:00
01d6244a0f
gowin: Fix status register parse for GW5AST
2023-12-04 07:01:56 +01:00
8007ffe263
xilinx: lint more happy
2023-11-25 15:14:32 +01:00
234f7f5a35
XADC and DNA for Xilinx FPGA ( #407 )
...
* xilinx: add XADC and DNA args, see https://github.com/cfib/openFPGALoaderXADC/tree/XADC_3
parts: add xcku060
* doc: add xcku060
2023-11-25 08:47:24 +01:00
b119a955a6
gowin: GW5A SPI flash support
2023-11-19 13:29:15 +01:00
a5f2aa56c8
gowin: displayReadReg update. Now GW5A field are correctly displayed
2023-11-19 10:25:06 +01:00
31c89e21a3
gowin: detectFamily new function
2023-11-19 10:18:45 +01:00
1cbdee362d
jtag,main: fix warnings
2023-11-19 10:17:54 +01:00
7059c15960
Add user device list for non-fpga JTAG devices
2023-11-10 14:00:24 -07:00
63c1950f2f
Add xc7k70t and small fixes for xc7k160t
2023-11-09 07:45:46 +07:00
1a86fa21ae
Merge pull request #399 from bg-gsl/fix_lattice_bscan_nexus
...
Fix lattice bscan nexus in clearSRAM()
2023-11-08 12:47:34 +01:00
fa5ff873e4
lattice.cpp: restore bypass instruction in clearSRAM()
2023-11-08 09:49:14 +01:00
f71858f96a
Rewrite GOWIN algorithms
2023-10-29 08:07:48 +01:00
790d2bccab
fsParser: adding GW5A-25 IDCODE
2023-10-29 07:02:12 +01:00
59b56bcc95
all jtag cable: no more hardcoding tdi bit with writeTMS
2023-10-29 06:41:39 +01:00
43ae0d8fdd
ftdiJtagMPSSE,jtagInterface: {set|get}{Read|Write}Edge signature
2023-10-29 06:12:09 +01:00
46ce2e61a7
ALINX AX7101 board.
2023-10-28 17:22:42 +02:00
d58a1c3fc7
lattice: correct mask for sram erase for NEXUS_FAMILY, as it is 0x00
2023-10-26 11:30:24 +02:00
917e42127b
lattice: fix bscan register initialization inside clearSRAM()
...
For NEXUS family fpgas, the Bscan register is 362 bits long
or 45.25 bytes => 46 bytes.
This error was already correct when programming the sram.
clearSRAM() is instead used when programming the spi flash memory.
2023-10-25 17:43:49 +02:00
a87d689d83
ALINX AX7102 board.
2023-10-24 14:03:18 +02:00
fd8497026a
ftdiJtagMPSSE,jtag,jtagInterface: allows to force read/write edge configuration (useful to mimic SPI through JTAG)
2023-10-24 07:26:19 +02:00
b76a67963e
board: SiPEED tang Mega 138K
2023-10-24 06:11:53 +02:00
9a2fe6e157
board: SiPEED tang Primer 25K
2023-10-24 06:07:42 +02:00
988bedefb6
lattice: fix typo / warning
2023-10-23 07:12:45 +02:00
590611a8d5
lattice: fix the warning "left shift count >= width of type" shown in win32/64 builds
2023-10-20 08:44:20 +02:00
bab386911a
spi flash: add mapping for Micron MT25/N25Q128_1_8V (Lattice Certus Versa and CertusPro eval boards) and distinguish between N25Q128 1.8V and 3V memories
2023-10-20 07:57:56 +02:00
940da5fb2b
spi flash: add mapping for Macronix MX25L51245G (CertusPro Versa board and gr740-mini)
2023-10-20 07:55:53 +02:00
5f6074a7fc
lattice: fix bscan width and other minor things for NEXUS family
2023-10-20 07:55:53 +02:00
dce0c050a7
board: add gr740-mini
2023-10-20 07:55:53 +02:00
2754e99215
cable: add FTDI FT4232HP mapping
2023-10-20 07:55:53 +02:00
0bbf817c92
part: fix typo
2023-10-19 17:46:50 +02:00
32ef0bd29c
Adding xcku115 to parts list ( #394 )
...
* Adding xcku115 to parts list
* Adding xcku115 to list of supported FPGAs
---------
Co-authored-by: Stephen Goadhouse <stephen.david.goadhouse@cern.ch>
2023-10-19 17:45:42 +02:00
dafe350fbe
lattice nexus family: REFRESH (plus config logic reset) in case of fpga in error state and add capabilities to handle the whole 64-bits status register
2023-10-12 09:06:54 +02:00
5733ca29c3
fix lattice programming and add nexus boards
...
Fix to lattice programming:
we considered a svf file generated by Lattice Radiant-Programmer
and compared it with the current way lattice devices were programmed.
There were few differences dealing with configuration reset and REFRESH.
These fixes allow us to program an fpga when it is in a state
of error (e.g. there's no bitstream in the SPI Flash).
Lattice parts added:
- CertusPro FPGA
Nexus boards added:
- Certus Versa Evaluation board
- CertusPro Evaluation board
- CertusPro Versa Evaluation board
2023-10-11 09:52:45 +02:00
ec35f15a51
altera,efinix,gowin,xilinx: Fix 'Flash SRAM' -> 'Load SRAM'
2023-10-09 14:53:57 +02:00
18056180a8
gatemate: do not call ftdi-related routines when using alternative cables
2023-10-04 15:41:10 +02:00
ad5ada90db
board: trion_t20_bga256_jtag support
2023-10-03 06:51:38 +02:00
e9b31425d6
cable: efinix jtag ft2232 variant
2023-10-03 06:48:47 +02:00
c0ad3225cc
Add support for Xilinx xczu17eg. It's tested on xczu17eg board with Digilent HS3 at 30Mbps.
2023-09-22 19:33:01 -07:00
c82a8e6207
Make CH347 driver faster
...
Speed up toggleClk
Defer write-only USB transactions to better utilize bus
2023-09-22 07:08:48 +02:00
67159e8297
Move JTAG chain bit init to device_select()
2023-09-22 07:05:20 +02:00
4c39abf51c
Add missing pieces to JTAG
2023-09-22 07:01:48 +02:00
85f9791600
drop div_by_5 to allow 2.5MHz clock
2023-09-22 06:55:21 +02:00
01ac90a172
[xilinx] add jtag->flush before sleep
2023-09-21 07:38:25 +02:00
b10be9ae8a
properly fill dummy arrays
2023-09-21 07:36:41 +02:00
d3410e0e30
Update JTAG chain detect
2023-09-21 07:33:54 +02:00
afbf0c4ff8
board: adding @lambdaconcept ecpix5_r03 (ft4232)
2023-09-21 06:24:30 +02:00
6c16417ee9
Merge UPDATE_DR and UPDATE_IR handling in JTAG state machines
2023-09-20 07:59:34 +02:00
6a0de15bff
Parse LoadingRate field
2023-09-20 07:58:06 +02:00
0c89ac9a44
Add GD32VF103 to misc devices
2023-09-20 07:48:21 +02:00
94b62460c5
jtag: shiftDR: (fix daisy chain) when more than one FPGA, a sequence of '0' before and/or after must be sent instead of '1' ( fix #189 and #133
2023-09-17 08:59:26 +02:00
9810735e32
jtag: rework detectChain: try unmasked idcode first
2023-09-14 21:53:27 +02:00
57fc9bcb6f
part: machXO3: re-add partially revision
2023-09-14 21:52:53 +02:00
5e9cc7c440
pass along reset paramaters to provide control to the caller
...
Upsteam-Status: Submitted [https://github.com/traucucayre/openFPGALoader ]
- Submitted to upstream, waiting approval
2023-09-10 20:46:08 -07:00
c417ce6746
lattice: spi_put: avoid loop when tx == NULL
2023-09-06 15:50:28 +02:00
61b59ce827
jtag: fix state machine (issue introduce by commit 9e91c3)
2023-09-06 15:47:32 +02:00
9e91c31e31
Fixes for PVS errors
2023-09-01 22:30:24 +03:00
0f3afbcaea
Make IDCODE unsigned
2023-08-29 20:01:21 +03:00
8976404b78
Use JTAG state
2023-08-29 20:00:28 +03:00
1908ccd83b
make output buffer const
2023-08-29 19:51:41 +03:00
0de2ea6b39
gowin: add preliminary support for GW5AST-138
...
Arora V series is a new series of Gowin FPGA, in which the flashing
process has changed.
Add preliminary support by adding FS file line count and deal with the
SRAM writing process. Flash writing is not yet done.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-08-12 12:36:06 +08:00
6a4e107e42
part: add known ID codes for GW5 series
...
Codes are from Gowin UG704.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-08-09 22:11:41 +08:00
9d22d62a54
part/board: adding Avnet Mini-ITX
...
Adding the Avnet Mini-ITX dev board that uses the XC7Z100 Zynq-7000
device.
2023-08-07 17:06:02 +01:00
e3c8d6be1d
board: added QMTECH cyclone10 LP starter kit (10CL016YU484C8G)
2023-08-05 11:49:53 +02:00
7424ea2af9
part: update altera/intel idcode (same idcode for III/IV/10 LP)
2023-08-05 06:47:51 +02:00
baff0cad1e
src/part: Fix Xilinx XC2 ident.
2023-08-03 16:12:51 +02:00
502f38fb00
src/part.hpp: Add Kintex Ultrascale+ KU3P ID-Code.
2023-08-03 16:07:55 +02:00
4042646434
src/part.hpp: Add separator for each vendor.
2023-08-03 16:07:43 +02:00
c3e0707f6b
src/part.hpp: Reorder families (older first, smaller first) and minor alignment cleanups.
2023-08-03 16:07:33 +02:00
a1dea79230
src/part.hpp: Add separator for each chip family.
2023-08-03 16:07:24 +02:00
4c5f6f361b
svf_jtag: fix -Wmismatched-new-delete delete -> delete[]
2023-08-03 07:53:59 +02:00
6ef87c5466
ftdipp_mpsse: fix format-zero-length snprintf -> memset
2023-08-03 07:43:56 +02:00
0e1e07262c
ftdispi: add missing status_pin
2023-08-03 07:42:06 +02:00
2f8056cba5
usbBlaster: cleanup
2023-07-30 08:54:13 +02:00
75d98d12e9
jtag: merge init_internal to CTOR, pass verbose to jtag drivers
2023-07-30 08:45:57 +02:00
4bf4b94bbb
cables: verbose type coherency
2023-07-30 08:39:15 +02:00
469e1c3669
efinix: remove verbose comparison
2023-07-30 07:28:29 +02:00
76f84c1190
ftdipp_mpsse: _verbose int8_t -> bool
2023-07-30 07:23:19 +02:00
c41ef7539c
ftdispi: convert verbose bool -> int8_t
2023-07-30 07:19:17 +02:00
baeb9d52ec
Merge pull request #358 from inkdot7/decimal_busdev
...
Parse USB bus:dev as decimal integers, to be consistent with `--scan-usb`.
2023-07-29 18:10:48 +02:00
bed17f3be8
Parse USB bus:dev as decimal integers, to be consistent with --scan-usb.
...
Do not accept auto-detected base 0 (e.g. prefix '0x' for hex), since '0'
prefix gives an octal interpretation, and the user is likely to copy
values from `--scan-usb` or `lsusb` that could then be misinterpreted,
e.g. 005:010.
2023-07-29 09:49:52 +02:00
4f7a4c33aa
Tell USB bus and address when ftdi open fails, when bus and addr both non-zero.
2023-07-29 08:52:16 +02:00
3955a70843
jtag: fix warning (uninitialized tms)
2023-07-27 07:39:20 +02:00
ab9eff7412
jlink: fix warning (uninitialized length)
2023-07-27 07:35:14 +02:00
1dba0572ff
lattice: fix warning (uninitialized rx_buf)
2023-07-27 07:18:59 +02:00
a1e9d3f7db
main: (SPI mode) sanity check: print error and quit when manufacturer is unknown
2023-07-27 07:15:49 +02:00
a89fc54f29
cable: ch347: fix for CI (libusb_strerror with a cast in -> libusb_error, fix libusb callback signature)
2023-07-26 08:37:39 +02:00
0fc8ba10a8
Add WCH CH347T(mode #3 ) JTAG cable
...
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
2023-07-26 08:17:57 +02:00
8ffa024a95
spiFlash: temporary disable read extended ( #345 )
2023-07-24 14:45:13 +02:00
91f2900f0c
add support for colorlight-i9+ board + spiOverJtag/spiOverJtag_xc7a50tfgg484.bit.gz
2023-06-30 11:36:32 +02:00
3e25a33346
boards: added support for 14bits 125MHz redpitaya board (7010)
2023-06-29 16:59:42 +02:00
1f5d6cb373
xilinx: rework error message for zynqXX in SPI_MODE
2023-06-01 20:33:27 +02:00
87b17ed9bf
efinix: support using JTAG interfaces
2023-06-01 11:05:26 +10:00
ec82dd6467
jlink: support J-Link BASE and J-Trace PRO
2023-05-29 11:57:47 +10:00
23d65823aa
jlink: report skipped devices with verbose
2023-05-29 11:57:47 +10:00
Gwenhael Goavec-Merou
Gwenhael Goavec-Merou
Uwe Bonnes
ZhiYuanNJ
Gwenhael Goavec
Giovanni Bruni
Michael Davidsaver
jgroman
sigmaeo
Michal Sieron
Sean Anderson
Chuang Zhu
Patrick Urban
Catherine
Tim Paine
bma
Mark Featherston
Hans Baier
Alexey Starikovskiy
Haakan T Johansson
sgoadhouse
Zhongyi Chen
Rodrigo Rengifo
Icenowy Zheng
Shareef Jalloq
Florent Kermarrec
Stéphane Chevigny
Andrew Dennison