Merge branch 'master' into netgen-1.5

Corrected a problem that stems from code that was deprecated and
marked as unneeded, so I simply removed the code rather than debug the issue, which was that buses got the delimeters erased for checking but never put back again. Also: Modified the verilog reading code so that if an empty set "()" is given for a pin, then the initial proxy, which is a single net with the name prefix "_noconnect_", can be promoted to a bus if further processing reveals it to be a bus and not a single-bit signal.
2026-08-22 05:57:36 +02:00 · 2021-12-30 03:00:43 -05:00 · 2021-12-29 14:31:38 -05:00 · 2021-12-27 03:00:18 -05:00 · 2021-12-26 10:31:48 -05:00 · 2021-12-20 03:00:02 -05:00
32 changed files with 3142 additions and 1360 deletions
@@ -0,0 +1,40 @@
+# This is a basic workflow to help you get started with Actions
+
+name: CI
+
+# Controls when the workflow will run
+on:
+  # Triggers the workflow on push or pull request events but only for the master branch
+  push:
+    branches: [ master ]
+  pull_request:
+    branches: [ master ]
+
+  # Allows you to run this workflow manually from the Actions tab
+  workflow_dispatch:
+
+# A workflow run is made up of one or more jobs that can run sequentially or in parallel
+jobs:
+  # This workflow contains a single job called "build"
+  build:
+    # The type of runner that the job will run on
+    runs-on: ubuntu-latest
+
+    # Steps represent a sequence of tasks that will be executed as part of the job
+    steps:
+      # Runs a set of commands using the runners shell
+      #- name: Logging into Dockerhub
+      #  run: docker login -u ${{ secrets.DOCKERHUB_USERNAME }} -p ${{ secrets.DOCKERHUB_PASSWORD }}
+        
+      - name: Pulling the docker image
+        run: docker pull vezzal/vezzal:v1
+        
+      - name: Start the container with the docker image
+        run: docker run -id --name test_netgen vezzal/vezzal:v1 bash | exit
+        
+      - name: Run the testing on the container and send the mail
+        run: docker exec test_netgen /vezzal/test_netgen.sh "[email protected],[email protected]" ${{ secrets.MAILING_KEY }}
+        
+  
+      
+          
@@ -12,3 +12,5 @@ scripts/config.status
 *~
 *.log
 UPDATE_ME
+tcltk/netgen.sh
+tcltk/netgen.tcl
@@ -9,7 +9,7 @@ MODULES = base
 MAKEFLAGS =
 INSTALL_CAD_DIRS = lib doc

-include defs.mak
+-include defs.mak

 all:	$(ALL_TARGET)

@@ -1,4 +1,8 @@
-NETGEN:  VERSION 1.5
+![Continuous Integration](https://github.com/RTimothyEdwards/netgen/actions/workflows/main.yml/badge.svg)
+
+# NETGEN
+
+### VERSION 1.5

 NETGEN is a general-purpose netlist management system.  It can read
 and write several netlist formats, including NTK (Caltech, CMU),
@@ -87,6 +91,49 @@ and IRSIM version 9.7:

 Note: For FreeBSD, use 'gmake' instead.

+Note: On MacOS (Big Sur) follow the following procedure. If you have installed `xschem` and `magic` already on MacOS then steps (1) and (2) can likely be skipped.
+
+**1) Build Tcl for X11**
+
+We are following the instructions from `xschem` (https://github.com/StefanSchippers/xschem/blob/master/README_MacOS.md). 
+
+* Download `Tcl` from https://prdownloads.sourceforge.net/tcl/tcl8.6.10-src.tar.gz
+
+We are using not `opt` but `opt2` so that this `Tcl` does not interfere with `tcl-tk` from HomeBrew.
+
+```
+./configure --prefix=/usr/local/opt2/tcl-tk  
+make
+make install
+```
+
+**2) Build Tk for X11**
+
+* Download `Tk` from https://prdownloads.sourceforge.net/tcl/tk8.6.10-src.tar.gz
+
+```
+./configure --prefix=/usr/local/opt2/tcl-tk \
+--with-tcl=/usr/local/opt2/tcl-tk/lib --with-x \
+--x-includes=/opt/X11/include --x-libraries=/opt/X11/lib  
+make
+make install
+```
+
+**3) Build netgen**
+
+We need to provide this custom-built `tcl-tk` and suppress compilation errors.
+
+```
+./configure --with-tcl=/usr/local/opt2/tcl-tk/lib \
+--with-tk=/usr/local/opt2/tcl-tk/lib \
+--x-includes=/opt/X11/include \
+--x-libraries=/opt/X11/lib \
+CFLAGS=-Wno-error=implicit-function-declaration
+make
+make install
+```
+
+
 IN CASE OF FAILURE
 -------------------
 Please contact me (tim@opencircuitdesign.com) to report compile-time and
@@ -1 +1 @@
-1.5.136
+1.5.215
@@ -23,12 +23,13 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include <stdio.h>
 #include <stdlib.h>	/* for strtod() */
 #include <stdarg.h>
+#include <ctype.h>

 #include "netgen.h"
-#include "hash.h"
 #include "objlist.h"
 #include "netfile.h"
 #include "print.h"
+#include "hash.h"

 void extCell(char *name, int filenum)
 {
@@ -186,7 +187,7 @@ char *ReadExt(char *fname, int doflat, int *fnum)
  /* Make sure all .ext file reading is case sensitive */
  matchfunc = match;
  matchintfunc = matchfile;
-  hashfunc = hash;
+  hashfunc = hashcase;

  if (LookupCellFile(fname, filenum) != NULL) {
    Printf("Error:  Duplicate cell name \"%s\"!\n", fname);
@@ -652,7 +653,7 @@ char *ReadSim(char *fname, int *fnum)
  /* Make sure all .sim file reading is case sensitive */
  matchfunc = match;
  matchintfunc = matchfile;
-  hashfunc = hash;
+  hashfunc = hashcase;

  CellDef(fname, filenum);

@@ -193,17 +193,19 @@ void flattenCell(char *name, int file)
 	if (Debug) Printf("Renaming %s to %s\n", tmp->name, tmpstr);
 	FreeString(tmp->name);
 	tmp->name = strsave(tmpstr);
-#if OLDPREFIX
-	sprintf(tmpstr, "%s%s%s", ParentParams->instance.name, SEPARATOR,
-		tmp->instance.name);
-#else
-	strcpy(tmpstr+prefixlength,tmp->instance.name);
-#endif
-	FreeString(tmp->instance.name);
-	tmp->instance.name = strsave(tmpstr);
 	HashPtrInstall(tmp->name, tmp, &(ThisCell->objdict));
-	if (tmp->type == FIRSTPIN) 
-	  HashPtrInstall(tmp->instance.name, tmp, &(ThisCell->instdict));
+	if ((tmp->type != NODE) && (tmp->instance.name != NULL)) {
+#if OLDPREFIX
+	   sprintf(tmpstr, "%s%s%s", ParentParams->instance.name, SEPARATOR,
+		    tmp->instance.name);
+#else
+	   strcpy(tmpstr+prefixlength,tmp->instance.name);
+#endif
+	   FreeString(tmp->instance.name);
+	   tmp->instance.name = strsave(tmpstr);
+	   if (tmp->type == FIRSTPIN) 
+	      HashPtrInstall(tmp->instance.name, tmp, &(ThisCell->instdict));
+        }
      }

      /* splice instance out of parent */
@@ -252,14 +254,15 @@ void flattenCell(char *name, int file)
 int flattenInstancesOf(char *name, int fnum, char *instance)
 {
  struct objlist *ParentParams;
-  struct objlist *ParentProps;
-  struct objlist *NextObj;
-  struct objlist *ChildObjList;
+  struct objlist *ParentProps, *CurrentProp;
+  struct objlist *NextObj, *LastObj, *prepp;
+  struct objlist *ChildObjList, *ChildListEnd;
+  struct objlist *ChildStart, *ChildEnd, *ParentEnd, *ParentNext;
  struct nlist *ThisCell;
  struct  nlist *ChildCell;
  struct objlist *tmp, *ob2, *ob3;
  int	notdone, rnodenum;
-  char	tmpstr[200];
+  char	tmpstr[1024];
  int	nextnode, oldmax, numflat = 0;
 #if !OLDPREFIX
  int     prefixlength;
@@ -296,21 +299,35 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
  while (notdone) {
    notdone = 0;
    ParentParams = ThisCell->cell;
+    LastObj = NULL;
+
    for (ParentParams = ThisCell->cell; ParentParams != NULL;
-	 ParentParams = NextObj) {
+		ParentParams = NextObj) {
      if (Debug) Printf("Parent = %s, type = %d\n",
 			ParentParams->name, ParentParams->type);
      NextObj = ParentParams->next;
-      if (ParentParams->type != FIRSTPIN) continue;
-      if (!(*matchfunc)(ParentParams->model.class, instance)) continue;
+      if (ParentParams->type != FIRSTPIN) {
+	  LastObj = ParentParams;
+	  continue;
+      }
+      if (!(*matchfunc)(ParentParams->model.class, instance)) {
+	  LastObj = ParentParams;
+	  continue;
+      }

      ChildCell = LookupCellFile(ParentParams->model.class, ThisCell->file);
      if (Debug)
 	 Printf(" Flattening instance: %s, primitive = %s\n",
 			ParentParams->instance.name, (ChildCell->class == 
 			CLASS_SUBCKT) ? "no" : "yes");
-      if (ChildCell->class != CLASS_SUBCKT) continue;
-      if (ChildCell == ThisCell) continue;	// Avoid infinite loop
+      if ((ChildCell->class != CLASS_SUBCKT) && (ChildCell->class != CLASS_MODULE)) {
+	   LastObj = ParentParams;
+	   continue;
+      }
+      if (ChildCell == ThisCell) {
+	   LastObj = ParentParams;
+	   continue;	// Avoid infinite loop
+      }

      /* Does the parent cell have properties?  If so, save a pointer to them */
      for (ParentProps = ParentParams->next; ParentProps &&
@@ -318,202 +335,264 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
 		ParentProps = ParentProps->next) {
 	 if (ParentProps->type == PROPERTY) break;
      }
-      if (ParentProps && (ParentProps->type != PROPERTY)) ParentProps = NULL;
-
-      /* not primitive, so need to flatten this instance */
-      notdone = 1;
-      /* if this is a new instance, flatten it */
-      /* if (ChildCell->dumped == 0) flattenCell(ParentParams->model.class, file); */
-
-      ChildObjList = CopyObjList(ChildCell->cell, 1);
-      numflat++;
-
-      /* update node numbers in child to unique numbers */
-      oldmax = 0;
-      for (tmp = ChildObjList; tmp != NULL; tmp = tmp->next) 
-	if (tmp->node > oldmax) oldmax = tmp->node;
-      if (nextnode <= oldmax) nextnode = oldmax + 1;
-
-      for (tmp = ChildObjList; tmp != NULL; tmp = tmp->next) 
-	if (tmp->node <= oldmax && tmp->node > 0) {
-	  if (Debug) Printf("Update node %d --> %d\n", tmp->node, nextnode);
-	  UpdateNodeNumbers(ChildObjList, tmp->node, nextnode);
-	  nextnode++;
-	}
-
-      /* copy nodenumbers of ports from parent */
-      ob2 = ParentParams;
-      for (tmp = ChildObjList; tmp != NULL; tmp = tmp->next) 
-	if (IsPort(tmp)) {
-	  if (tmp->node > 0) {
-	    if (ob2->node == -1) {
-
-	       // Before commiting to attaching to a unconnected node, see
-	       // if there is another node in ParentParams with the same
-	       // name and a valid node number.  If so, connect them.  In
-	       // the broader case, it may be necessary to consider all
-	       // nodes, not just those with node == -1, and call join()
-	       // here to update all node numbers in the parent cell.
-	       // In that case, a more efficient method is needed for
-	       // tracking same-name ports.
-
-	       for (ob3 = ParentParams; ob3 && ob3->type >= FIRSTPIN; ob3 = ob3->next) {
-		   if (ob3 == ob2) continue;
-		   if ((*matchfunc)(ob3->name, ob2->name) && ob3->node != -1) {
-		       ob2->node = ob3->node;
-		       break;
-		   }
-	       }
-	    }
-	    if (Debug) {
-	       // Printf("  Sealing port: %d to node %d\n", tmp->node, ob2->node);
-	       Printf("Update node %d --> %d\n", tmp->node, ob2->node);
-	    }
-	    UpdateNodeNumbers(ChildObjList, tmp->node, ob2->node);
-	  }
-
-	/* in pathological cases, the lengths of the port lists may
-           change.  This is an error, but that is no reason to allow
-           the code to core dump.  We avoid this by placing a 
-           superfluous check on ob2->type
-        */
-
-	  if (ob2 != NULL)
-	    ob2 = ob2->next;
-
-	  if (ob2 == NULL) break;
-	}
-
-      /* Using name == NULL to indicate that a .ext file is being */
-      /* flattened on the fly.  This is quick & dirty.		  */
-
-      if (name != NULL) {
-        /* delete all port elements from child */
-        while ((ChildObjList != NULL) && IsPort(ChildObjList)) {
-	  /* delete all ports at beginning of list */
-	  if (Debug) Printf("deleting leading port from child\n");
-	  tmp = ChildObjList->next;
-	  // FreeObjectAndHash(ChildObjList, ChildCell);
-	  FreeObject(ChildObjList);
-	  ChildObjList = tmp;
-        }
-        tmp = ChildObjList;
-        while (tmp && (tmp->next != NULL)) {
-	  if (IsPort(tmp->next)) {
-	    ob2 = (tmp->next)->next;
-	    if (Debug) Printf("deleting a port from child\n");
-	    // FreeObjectAndHash(tmp->next, ChildCell);
-	    FreeObject(tmp->next);
-	    tmp->next = ob2;
-	  } 
-	  else tmp = tmp->next;
-        }
+      if (ParentProps && (ParentProps->type != PROPERTY)) {
+	  ParentProps = NULL;
+	  CurrentProp = NULL;
      }
+      else
+	  CurrentProp = ParentProps;

-      /* for each element in child, prepend 'prefix' */
+      /* Find the end record of the parent cell and save it */
+      for (ParentEnd = (ParentProps) ? ParentProps : ParentParams;
+		ParentEnd && ParentEnd->next &&
+		/* Stop on a node or the next instance */
+		((ParentEnd->next->type > FIRSTPIN) ||
+		    (ParentEnd->next->type == PROPERTY));
+		ParentEnd = ParentEnd->next);
+
+      /* Not primitive, so need to flatten this instance */
+      notdone = 1;
+
+      /* Loop over property records.  Need to flatten once per	*/
+      /* property record (or more, if property has M > 1)	*/
+
+      ob2 = NULL;
+      ChildObjList = NULL;
+      ChildListEnd = NULL;
+      while (1) {
+
+         ChildStart = CopyObjList(ChildCell->cell, 1);
+         numflat++;
+
+         /* Find the end record of the child cell and save it */
+         for (ChildEnd = ChildStart; ChildEnd && ChildEnd->next;
+			ChildEnd = ChildEnd->next);
+
+         if (ChildListEnd == NULL) ChildListEnd = ChildEnd;
+
+         /* update node numbers in child to unique numbers */
+         oldmax = 0;
+         for (tmp = ChildStart; tmp != NULL; tmp = tmp->next) 
+	    if (tmp->node > oldmax) oldmax = tmp->node;
+         if (nextnode <= oldmax) nextnode = oldmax + 1;
+
+         for (tmp = ChildStart; tmp != NULL; tmp = tmp->next) 
+	    if (tmp->node <= oldmax && tmp->node > 0) {
+	       if (Debug) Printf("Update node %d --> %d\n", tmp->node, nextnode);
+	       UpdateNodeNumbers(ChildStart, tmp->node, nextnode);
+	       nextnode++;
+	    }
+
+         /* copy nodenumbers of ports from parent */
+         ob2 = ParentParams;
+         for (tmp = ChildStart; tmp != NULL; tmp = tmp->next)  {
+	    if (IsPort(tmp)) {
+	       if (tmp->node > 0) {
+	          if (ob2->node == -1) {
+
+	             // Before commiting to attaching to a unconnected node, see
+	             // if there is another node in ParentParams with the same
+	             // name and a valid node number.  If so, connect them.  In
+	             // the broader case, it may be necessary to consider all
+	             // nodes, not just those with node == -1, and call join()
+	             // here to update all node numbers in the parent cell.
+	             // In that case, a more efficient method is needed for
+	             // tracking same-name ports.
+
+	             for (ob3 = ParentParams; ob3 && ob3->type >= FIRSTPIN;
+					ob3 = ob3->next) {
+		        if (ob3 == ob2) continue;
+		        if ((*matchfunc)(ob3->name, ob2->name) && ob3->node != -1) {
+		           ob2->node = ob3->node;
+		           break;
+		        }
+	             }
+	          }
+	          if (Debug) {
+	             // Printf("  Sealing port: %d to node %d\n", tmp->node, ob2->node);
+	             Printf("Update node %d --> %d\n", tmp->node, ob2->node);
+	          }
+	          UpdateNodeNumbers(ChildStart, tmp->node, ob2->node);
+	       }
+
+	       /* in pathological cases, the lengths of the port lists may
+                * change.  This is an error, but that is no reason to allow
+                * the code to core dump.  We avoid this by placing a 
+                * superfluous check on ob2->type
+                */
+	       if (ob2 != NULL) ob2 = ob2->next;
+
+	       if (ob2 == NULL) break;
+	    }
+	 }
+
+         /* Using name == NULL to indicate that a .ext file is being 	*/
+         /* flattened on the fly.  This is quick & dirty.		*/
+
+         if (name != NULL) {
+            /* delete all port elements from child */
+            while ((ChildStart != NULL) && IsPort(ChildStart)) {
+	       /* delete all ports at beginning of list */
+	       if (Debug) Printf("deleting leading port from child\n");
+	       tmp = ChildStart->next;
+	       FreeObject(ChildStart);
+	       ChildStart = tmp;
+            }
+            tmp = ChildStart;
+            while (tmp && (tmp->next != NULL)) {
+	       if (IsPort(tmp->next)) {
+	          ob2 = (tmp->next)->next;
+	          if (Debug) Printf("deleting a port from child\n");
+	          FreeObject(tmp->next);
+	          tmp->next = ob2;
+	       } 
+	       else tmp = tmp->next;
+            }
+	    if (ChildStart == NULL) {
+	       if (ChildListEnd == ChildEnd) ChildListEnd = NULL;
+	       ChildEnd = NULL;
+	    }
+         }
+
+         /* for each element in child, prepend 'prefix' */
 #if !OLDPREFIX
-      /* replaces all the sprintf's below */
-      strcpy(tmpstr,ParentParams->instance.name);
-      strcat(tmpstr,SEPARATOR);
-      prefixlength = strlen(tmpstr);
+         /* replaces all the sprintf's below */
+         strcpy(tmpstr,ParentParams->instance.name);
+         strcat(tmpstr,SEPARATOR);
+         prefixlength = strlen(tmpstr);
 #endif
-      for (tmp = ChildObjList; tmp != NULL; tmp = tmp->next) {
-	if (tmp->type == PROPERTY)
-	    continue;
+         for (tmp = ChildStart; tmp != NULL; tmp = tmp->next) {
+	    if (tmp->type == PROPERTY)
+	       continue;

-	else if (IsGlobal(tmp)) {
-	   /* Keep the name but search for node of same name in parent	*/
-	   /* and replace the node number, if found.			*/
+	    else if (IsGlobal(tmp)) {
+	       /* Keep the name but search for node of same name in parent	*/
+	       /* and replace the node number, if found.			*/

-	   for (ob2 = ThisCell->cell; ob2 != NULL; ob2 = ob2->next) {
-	      /* Type in parent may be a port, not a global */
-	      if (ob2->type == tmp->type || ob2->type == PORT) {
-	         if ((*matchfunc)(tmp->name, ob2->name)) {
-		    if (ob2->node >= 0) {
-		       // Replace all child objects with this node number
-		       rnodenum = tmp->node;
-		       for (ob3 = ChildObjList; ob3 != NULL; ob3 = ob3->next) {
-			  if (ob3->node == rnodenum)
-			     ob3->node = ob2->node;
-		       }
-		       break;
-		    }
-		 }
-	      }
-	   }
-	   // Don't hash this if the parent had a port of this name
-	   if (!ob2 || ob2->type != PORT)
-	      HashPtrInstall(tmp->name, tmp, &(ThisCell->objdict));
-	   continue;
-	}
+	       for (ob2 = ThisCell->cell; ob2 != NULL; ob2 = ob2->next) {
+	          /* Type in parent may be a port, not a global */
+	          if (ob2->type == tmp->type || ob2->type == PORT) {
+	             if ((*matchfunc)(tmp->name, ob2->name)) {
+		        if (ob2->node >= 0) {
+		           // Replace all child objects with this node number
+		           rnodenum = tmp->node;
+		           for (ob3 = ChildStart; ob3 != NULL; ob3 = ob3->next) {
+			      if (ob3->node == rnodenum)
+			         ob3->node = ob2->node;
+		           }
+		           break;
+		        }
+		     }
+	          }
+	       }
+	       // Don't hash this if the parent had a port of this name
+	       if (!ob2 || ob2->type != PORT)
+	          HashPtrInstall(tmp->name, tmp, &(ThisCell->objdict));
+	       continue;
+	    }

 #if OLDPREFIX	
-	sprintf(tmpstr, "%s%s%s", ParentParams->instance.name, SEPARATOR,
-		tmp->name);
+	    sprintf(tmpstr, "%s%s%s", ParentParams->instance.name, SEPARATOR,
+				tmp->name);
 #else
-	strcpy(tmpstr+prefixlength,tmp->name);
+	    strcpy(tmpstr+prefixlength,tmp->name);
 #endif
-	if (Debug) Printf("Renaming %s to %s\n", tmp->name, tmpstr);
-	FreeString(tmp->name);
-	tmp->name = strsave(tmpstr);
+	    if (Debug) Printf("Renaming %s to %s\n", tmp->name, tmpstr);
+	    FreeString(tmp->name);
+	    tmp->name = strsave(tmpstr);
+	    HashPtrInstall(tmp->name, tmp, &(ThisCell->objdict));
+	    if ((tmp->type != NODE) && (tmp->instance.name != NULL)) {
 #if OLDPREFIX
-	sprintf(tmpstr, "%s%s%s", ParentParams->instance.name, SEPARATOR,
-		tmp->instance.name);
+	       sprintf(tmpstr, "%s%s%s", ParentParams->instance.name, SEPARATOR,
+		    		tmp->instance.name);
 #else
-	strcpy(tmpstr+prefixlength,tmp->instance.name);
+	       strcpy(tmpstr+prefixlength,tmp->instance.name);
 #endif
-	FreeString(tmp->instance.name);
-	tmp->instance.name = strsave(tmpstr);
-	HashPtrInstall(tmp->name, tmp, &(ThisCell->objdict));
-	if (tmp->type == FIRSTPIN) 
-	  HashPtrInstall(tmp->instance.name, tmp, &(ThisCell->instdict));
-      }
-
-      /* Do property inheritance */
-
-      if (ParentProps) {
-         for (ob2 = ChildObjList; ob2 != NULL; ob2=ob2->next) {
-
-	    /* If the parent cell has properties to declare, then	*/
-	    /* pass them on to children.  Use globals only if the	*/
-	    /* spiceparams dictionary is active (during file reading	*/
-	    /* only).							*/
-
-	    if (ob2->type == PROPERTY)
-		ReduceExpressions(ob2, ParentProps, ChildCell,
-			(spiceparams.hashtab == NULL) ? 0 : 1);
+	       FreeString(tmp->instance.name);
+	       tmp->instance.name = strsave(tmpstr);
+	       if (tmp->type == FIRSTPIN) 
+	          HashPtrInstall(tmp->instance.name, tmp, &(ThisCell->instdict));
+            }
         }
+
+         /* Do property inheritance */
+
+         /* NOTE:  Need to do:  Check properties for M > 1 and decrement
+          * and repeat without moving CurrentProp
+          */
+
+         if (CurrentProp) {
+            for (ob2 = ChildStart; ob2 != NULL; ob2=ob2->next) {
+
+	       /* If the parent cell has properties to declare, then	*/
+	       /* pass them on to children.  Use globals only if the	*/
+	       /* spiceparams dictionary is active (during file		*/
+	       /* reading only).					*/
+
+	       if (ob2->type == PROPERTY)
+		  ReduceExpressions(ob2, CurrentProp, ChildCell,
+				(spiceparams.hashtab == NULL) ? 0 : 1);
+            }
+
+            /* Repeat for each property record, as each property represents a
+             * unique instance that must be flattened individually.
+             */
+
+	    CurrentProp = CurrentProp->next;
+	    if ((CurrentProp == NULL) || (CurrentProp->type != PROPERTY)) break;
+         }
+         else break;
+
+         /* Put the child cell at the start of ChildObjList */
+         ChildEnd->next = ChildObjList;
+         ChildObjList = ChildStart;
      }

-      /* splice instance out of parent */
-      if ((ParentParams == ThisCell->cell) && (ChildObjList == NULL)) {
-	ThisCell->cell = ob2;	/* Child cell was empty */
-	tmp = ob2;
+      /* Put the child cell at the start of ChildObjList */
+      if (ChildEnd) {
+         ChildEnd->next = ChildObjList;
+         ChildObjList = ChildStart;
      }
-      else {
+
+      /* Pull the instance out of the parent */
+
+      if ((ParentParams != ThisCell->cell) || (ChildObjList != NULL)) {
         if (ParentParams == ThisCell->cell) {
-	   /* ParentParams are the very first thing in the list */
-	   ThisCell->cell = ChildObjList;
-	   for (ob2 = ChildObjList; ob2 && ob2->next != NULL; ob2 = ob2->next) ;
+	    /* ParentParams are the very first thing in the list */
+	    ThisCell->cell = ChildObjList;
         }
-         else {
-	   /* find ParentParams in ThisCell list */
-	   for (ob2 = ThisCell->cell; ob2 && ob2->next != ParentParams; ob2=ob2->next); 
-	   if (ob2)
-	      for (ob2->next = ChildObjList; ob2->next != NULL; ob2 = ob2->next) ;
+         else if (ChildObjList) {
+	    /* find ParentParams in ThisCell list.  In most cases, LastObj  */
+	    /* should be pointing to it.				    */
+	    if (LastObj && (LastObj->next == ParentParams)) {
+	       LastObj->next = ChildObjList;
+	    }
+	    else {
+	       for (ob2 = LastObj; ob2 && ob2->next != ParentParams;
+			ob2 = ob2->next); 
+	       if (ob2 == NULL) {
+		  /* It should not happen that LastObj is ahead of ParentParams	*/
+		  /* but just in case, this long loop will find it.		*/
+	          for (ob2 = ThisCell->cell; ob2 && ob2->next != ParentParams;
+				ob2 = ob2->next); 
+	       }
+	       ob2->next = ChildObjList;
+	    }
         }
-         /* now, ob2 is last element in child list, so skip and reclaim parent */
+	 else {
+	    /* The child was completely optimized out, so close list around it */
+	    LastObj->next = ParentEnd->next;
+	 }

-         tmp = ParentParams;
-         do {
-	   tmp = tmp->next;
-         } while ((tmp != NULL) && ((tmp->type > FIRSTPIN) || (tmp->type == PROPERTY)));
-         if (ob2) ob2->next = tmp;
+         /* Link end of child list into the parent */
+	 if (ChildListEnd && ParentEnd)
+	    ChildListEnd->next = ParentEnd->next;
      }
-      while (ParentParams != tmp) {
-	ob2 = ParentParams->next;
-	FreeObjectAndHash(ParentParams, ThisCell);
-	ParentParams = ob2;
+      ParentNext = (ParentEnd) ? ParentEnd->next : NULL;
+      while (ParentParams != ParentNext) {
+	 ob2 = ParentParams->next;
+	 FreeObjectAndHash(ParentParams, ThisCell);
+	 ParentParams = ob2;
      }
      NextObj = ParentParams;
    }				/* repeat until no more instances found */
@@ -1136,9 +1215,10 @@ int UniquePins(char *name, int filenum)
 struct nlist *cleanuppins(struct hashlist *p, void *clientdata)
 {
   struct nlist *ptr;
-   struct objlist *ob, *obt, *lob, *nob, *firstpin;
+   struct objlist *ob, *obt, *lob, *nob, *firstpin, *pob;
   struct nlist *tc = (struct nlist *)clientdata;
   int pinnum;
+   char *saveinst = NULL;

   ptr = (struct nlist *)(p->ptr);
   if (tc->file != ptr->file) return NULL;
@@ -1166,7 +1246,7 @@ struct nlist *cleanuppins(struct hashlist *p, void *clientdata)
          while (ob && obt && (ob->type > FIRSTPIN || ob == firstpin) &&
 			ob->model.class != NULL) {
 	     nob = ob->next;
-	     if ((obt->type == PORT) && (obt->node == -1)) {
+	     if ((obt->type == PORT) && (obt->node == -2)) {

 	        /* Remove this pin */

@@ -1186,13 +1266,44 @@ struct nlist *cleanuppins(struct hashlist *p, void *clientdata)
 	        }

 		FREE(ob->name);
-		if (ob->instance.name != NULL) FREE(ob->instance.name);
+		if (ob->instance.name != NULL) {
+		    /* Keep a copy of the instance name (see below) */
+		    if (saveinst != NULL) FREE(saveinst);
+		    saveinst = ob->instance.name;
+		}
 		if (ob->model.class != NULL) FREE(ob->model.class);
 		FREE(ob);
 	     }
 	     else {
-		lob = ob;
-		ob->type = pinnum++;	// Renumber pins in order
+		if ((ob->type == PROPERTY) && (pinnum == 1))
+		{
+		    /* If this happens, then all the pins got removed,
+		     * and there is probably something very much wrong
+		     * with the setup.  However, to keep netgen from
+		     * blowing up, add back a "proxy(no pins)" record
+		     * in front; otherwise we'd have an orphaned
+		     * property record.
+		     */
+		    pob = GetObject();
+		    pob->name = (char *)MALLOC(15);
+		    sprintf(pob->name, "proxy(no pins)");
+		    pob->model.class = strsave(ob->model.class);
+		    if (saveinst != NULL)
+			pob->instance.name = strsave(saveinst);
+		    else
+			/* This should never happen */
+			pob->instance.name = strsave("error");
+		    pob->type = pinnum++;
+		    pob->node = -1;
+		    pob->next = ob;
+		    lob->next = pob;
+		    lob = ob;
+		}
+		else
+		{
+		    lob = ob;
+		    ob->type = pinnum++;	// Renumber pins in order
+		}
 	     }
 	     ob = nob;
 	     obt = obt->next;
@@ -1203,6 +1314,8 @@ struct nlist *cleanuppins(struct hashlist *p, void *clientdata)
 	     HashPtrInstall(firstpin->instance.name, firstpin, &(ptr->instdict));
      }
   }
+
+   if (saveinst != NULL) FREE(saveinst);
   return NULL;		/* Keep the search going */
 }

@@ -1238,7 +1351,7 @@ int CleanupPins(char *name, int filenum)

   for (ob = ThisCell->cell; ob != NULL; ob = ob->next) {
      if (ob->type != PORT) break;
-      if (ob->node == -1) {
+      if (ob->node == -2) {
 	 needscleanup = 1;
 	 break;
      }
@@ -1265,7 +1378,7 @@ int CleanupPins(char *name, int filenum)
      }
      else if (ob->type != PORT) break;
      nob = ob->next;
-      if (ob->node == -1) {
+      if (ob->node == -2) {
 	 if (lob == NULL) {
 	    ThisCell->cell = ob->next;
 	 }
@@ -1308,6 +1421,22 @@ typedef struct ecomplist {
    ECompListPtr next;
 } ECompList;

+/*----------------------------------------------------------------------*/
+/* Determine if a cell contains at least one device or subcircuit	*/
+/*----------------------------------------------------------------------*/
+
+int
+HasContents(struct nlist *tc)
+{
+    struct objlist *ob;
+
+    for (ob = tc->cell; ob; ob = ob->next)
+	if (ob->type == FIRSTPIN)
+	    return TRUE;
+
+    return FALSE;
+}
+
 /*------------------------------------------------------*/
 /* Survey the contents of a cell and sort into a hash	*/
 /*------------------------------------------------------*/
@@ -1405,6 +1534,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
    struct hashdict compdict;
    ECompare *ecomp, *ncomp;
    ECompList *list0X, *listX0;
+    int hascontents1, hascontents2;
    int match, modified = 0;

    if (file1 == -1)
@@ -1420,6 +1550,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
    if (tc1 == NULL || tc2 == NULL) return 0;

    InitializeHashTable(&compdict, OBJHASHSIZE);
+    listX0 = list0X = NULL;

    // Gather information about instances of cell "name1"
    SurveyCell(tc1, &compdict, file1, file2, 0);
@@ -1432,7 +1563,6 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
    // in the hierarchy of each instance contain devices
    // or subcircuits that have more in the compared circuit.

-    listX0 = list0X = NULL;
    ecomp = (ECompare *)HashFirst(&compdict);
    while (ecomp != NULL) {

@@ -1469,19 +1599,20 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 			}
 		    }
 		    else {
-		       match = 0;
+		       // cell exists in one circuit but not the other, so flatten it.
+		       // match = 0;
 		       break;
 		    }
 		}
 	    }
 	    if (match) {
-		if (ecomp->cell1) {
+		if (ecomp->cell1 && (ecomp->num1 > 0)) {
 		    Fprintf(stdout, "Flattening instances of %s in cell %s"
 				" makes a better match\n", ecomp->cell1->name,
 				name1);
 		    flattenInstancesOf(name1, file1, ecomp->cell1->name); 
 		}
-		if (ecomp->cell2) {
+		if (ecomp->cell2 && (ecomp->num2 > 0)) {
 		    Fprintf(stdout, "Flattening instances of %s in cell %s"
 				" makes a better match\n", ecomp->cell2->name,
 				name2);
@@ -1536,10 +1667,10 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 	}

 	/* Case 2:  Cell2 class is a subcircuit, and flattening	*/
-	/* (it without regard to cell1) improves the matching.	*/
+	/* it (without regard to cell1) improves the matching.	*/

 	else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell2 != NULL) &&
-			(ecomp->cell2->class == CLASS_SUBCKT)) {
+			(ecomp->num2 != 0) && (ecomp->cell2->class == CLASS_SUBCKT)) {
 	    ecomp->add2 = -ecomp->num2;
 	    match = 1;
 	    for (ob2 = ecomp->cell2->cell; ob2; ob2 = ob2->next) {
@@ -1594,10 +1725,10 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 	}
 	
 	/* Case 3:  Cell1 class is a subcircuit, and flattening	*/
-	/* (it without regard to cell1) improves the matching.	*/
+	/* it (without regard to cell1) improves the matching.	*/

 	else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell1 != NULL) &&
-			(ecomp->cell1->class == CLASS_SUBCKT)) {
+			(ecomp->num1 != 0) && (ecomp->cell1->class == CLASS_SUBCKT)) {
 	    ecomp->add1 = -ecomp->num1;
 	    match = 1;
 	    for (ob2 = ecomp->cell1->cell; ob2; ob2 = ob2->next) {
@@ -1660,7 +1791,8 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
    while (ecomp != NULL) {
 	if ((ecomp->num1 != ecomp->num2) && (ecomp->cell1 != NULL) &&
 			((ecomp->cell1->class == CLASS_RES) ||
-			(ecomp->cell1->class == CLASS_VSOURCE))) {
+			(ecomp->cell1->class == CLASS_VSOURCE) ||
+			(ecomp->cell1->class == CLASS_ISOURCE))) {
 	    int node1 = -1, node2 = -1;
 	    lob = NULL;
 	    for (ob1 = tc1->cell; ob1; ) {
@@ -1709,11 +1841,16 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 						tsub1->name,
 						tc1->name);

-					/* merge node of endpoints */
-					for (ob2 = tc1->cell; ob2; ob2 = ob2->next) {
-					    if (ob2->node == node2)
-						ob2->node = node1;
-					}
+					/* A current source is an open, while a	    */
+					/* resistor or voltage source is a short.   */
+
+					if (ecomp->cell1->class != CLASS_ISOURCE) {
+					    /* merge node of endpoints */
+					    for (ob2 = tc1->cell; ob2; ob2 = ob2->next) {
+						if (ob2->node == node2)
+						    ob2->node = node1;
+					    }
+					}	

 					/* snip, snip.  Excise this device */
 					if (lob == NULL) {
@@ -1765,7 +1902,8 @@ PrematchLists(char *name1, int file1, char *name2, int file2)

 	if ((ecomp->num1 != ecomp->num2) && (ecomp->cell2 != NULL) &&
 			((ecomp->cell2->class == CLASS_RES) ||
-			(ecomp->cell2->class == CLASS_VSOURCE))) {
+			(ecomp->cell2->class == CLASS_VSOURCE) ||
+			(ecomp->cell2->class == CLASS_ISOURCE))) {
 	    int node1 = -1, node2 = -1;
 	    lob = NULL;
 	    for (ob2 = tc2->cell; ob2; ) {
@@ -1815,9 +1953,11 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 						tc2->name);

 					/* merge node of endpoints */
-					for (ob1 = tc2->cell; ob1; ob1 = ob1->next) {
-					    if (ob1->node == node2)
-						ob1->node = node1;
+					if (ecomp->cell2->class != CLASS_ISOURCE) {
+					    for (ob1 = tc2->cell; ob1; ob1 = ob1->next) {
+						if (ob1->node == node2)
+						    ob1->node = node1;
+					    }
 					}

 					/* snip, snip.  Excise this device */
@@ -1942,6 +2082,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 	}
    }

+done:
    // Free the hash table and its contents.

    ecomp = (ECompare *)HashFirst(&compdict);
@@ -0,0 +1,8 @@
+#ifndef _FLATTEN_H
+#define _FLATTEN_H
+
+extern int UniquePins(char *name, int filenum);
+extern void flattenCell(char *name, int file);
+extern int HasContents(struct nlist *);
+
+#endif /* _FLATTEN_H */
@@ -30,8 +30,8 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #endif

 #include "netgen.h"
-#include "hash.h"
 #include "objlist.h"
+#include "hash.h"

 unsigned long (*hashfunc)(char *, int) = NULL;
 int (*matchfunc)(char *, char *) = NULL;
@@ -148,7 +148,7 @@ unsigned long hashnocase(char *s, int hashsize)
 	return (hashsize == 0) ? hashval : (hashval % hashsize);
 }

-unsigned long hash(char *s, int hashsize)
+unsigned long hashcase(char *s, int hashsize)
 {
 	unsigned long hashval;
 	
@@ -48,7 +48,7 @@ extern void *HashFirst(struct hashdict *dict);
 extern void *HashNext(struct hashdict *dict);

 extern unsigned long hashnocase(char *s, int hashsize);
-extern unsigned long hash(char *s, int hashsize);
+extern unsigned long hashcase(char *s, int hashsize);

 extern int (*matchfunc)(char *, char *);
 /* matchintfunc() compares based on the name and the first	*/
@@ -26,6 +26,7 @@ extern void PrintCoreStats(void);
 extern void ResetState(void);
 extern void CreateTwoLists(char *name1, int file1, char *name2, int file2,
 		int dolist);
+extern void DescribeContents(char *name1, int file1, char *name2, int file2);
 extern int Iterate(void);
 extern int VerifyMatching(void);
 extern void PrintAutomorphisms(void);
@@ -46,6 +47,7 @@ extern int  CreateCompareQueue(char *, int, char *, int);
 extern int  GetCompareQueueTop(char **, int *, char **, int *);
 extern int  PeekCompareQueueTop(char **, int *, char **, int *);
 extern void RemoveCompareQueue();
+extern int FlattenUnmatched(struct nlist *, char *, int, int);

 extern void PrintIllegalClasses();
 extern void PrintIllegalNodeClasses();
@@ -54,6 +56,15 @@ extern void PrintIllegalElementClasses();
 extern void DumpNetwork(struct objlist *ob, int cidx);
 extern void DumpNetworkAll(char *name, int file);

+extern void RegroupDataStructures();
+extern void FormatIllegalElementClasses();
+extern void FormatIllegalNodeClasses();
+extern int ResolveAutomorphsByProperty();
+extern int ResolveAutomorphsByPin();
+extern void SummarizeElementClasses(struct ElementClass *EC);
+extern int remove_group_tags(struct objlist *ob);
+
+
 #ifdef TCL_NETGEN
 extern int EquivalentNode();
 extern int EquivalentElement();
@@ -289,6 +289,7 @@ int GetNextLineNoNewline(char *delimiter)
    char *newbuf;
    int testc;
    int nested = 0;
+    int llen;

    if (feof(infile)) return -1;

@@ -301,20 +302,33 @@ int GetNextLineNoNewline(char *delimiter)

 	if (linesize == 0) {
 	    /* Allocate memory for line */
-	    linesize = 500;
-	    line = (char *)MALLOC(linesize);
-	    linetok = (char *)MALLOC(linesize);
+	    linesize = 2000;
+	    line = (char *)MALLOC(linesize + 1);
+	    linetok = (char *)MALLOC(linesize + 1);
 	}
 	fgets(line, linesize, infile);
-	while (strlen(line) == linesize - 1) {
-	    newbuf = (char *)MALLOC(linesize + 500);
+	/* Immediately resolve backslash-EOL */
+	llen = strlen(line);
+	while ((llen > 1) && (llen < linesize - 1) && *(line + llen - 2) == '\\') {
+	    *(line + llen - 2) = '\n';
+	    fgets(line + llen - 1, linesize - llen + 1, infile);
+	    llen = strlen(line);
+	}
+	while (llen == linesize - 1) {
+	    newbuf = (char *)MALLOC(linesize + 501);
 	    strcpy(newbuf, line);
 	    FREE(line);
 	    line = newbuf;
 	    fgets(line + linesize - 1, 501, infile);
+	    llen = strlen(line);
+	    while ((llen > 1) && (llen < linesize - 1) && *(line + llen - 2) == '\\') {
+		*(line + llen - 2) = '\n';
+		fgets(line + llen - 1, linesize - llen + 1, infile);
+		llen = strlen(line);
+	    }
 	    linesize += 500;
 	    FREE(linetok);
-	    linetok = (char *)MALLOC(linesize);
+	    linetok = (char *)MALLOC(linesize + 1);
 	}

 	/* Check for substitutions (verilog only).  Make sure linetok is    */
@@ -329,7 +343,7 @@ int GetNextLineNoNewline(char *delimiter)
 	    for (s = line; *s != '\0'; s++) {
 		if (*s == '`') {
 		    w = s + 1;
-		    while (isalnum(*w)) w++;
+		    while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
 		    e = *w;
 		    *w = '\0';
 		    kl = (struct property *)HashLookup(s + 1, definitions);
@@ -365,7 +379,7 @@ int GetNextLineNoNewline(char *delimiter)
 	    for (s = line; *s != '\0'; s++) {
 		if (*s == '`') {
 		    w = s + 1;
-		    while (isalnum(*w)) w++;
+		    while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
 		    e = *w;
 		    *w = '\0';
 		    kl = (struct property *)HashLookup(s + 1, definitions);
@@ -496,6 +510,24 @@ void GetNextLine(char *delimiter)
    } while (nexttok == NULL);
 }

+/*----------------------------------------------------------------------*/
+/* Return a pointer to the line at the position of nexttok		*/
+/* This is used only when returning the entire line, untokenized, and	*/
+/* is only called by the verilog read routine when reading the value of	*/
+/* a `define statement.							*/
+/*----------------------------------------------------------------------*/
+
+char *GetLineAtTok()
+{
+    char *lpos;
+
+    if (nexttok == NULL) return NULL;
+    if (line == NULL) return NULL;
+
+    lpos = strstr(line, nexttok);
+    return lpos;
+}
+
 /*----------------------------------------------------------------------*/
 /* if nexttok is already NULL, force scanner to read new line		*/
 /*----------------------------------------------------------------------*/
@@ -673,6 +705,7 @@ char *strdtok(char *pstring, char *delim1, char *delim2)
    /* accordingly (needs to be done).						*/

    if (*s == '\\') {
+        s++;
        while (*s != '\0') {
 	    if ((*s == ' ') || (*s == '\\')) {
 		s++;
@@ -765,7 +798,7 @@ int OpenParseFile(char *name, int fnum)
  FILE *locfile;
  struct filestack *newfile;

-  locfile = fopen(name,"r");
+  locfile = fopen(name, "r");
  linenum = 0;
  /* reset the token scanner */
  nexttok = NULL;  
@@ -850,7 +883,12 @@ char *ReadNetlist(char *fname, int *fnum)
      {SPICE_EXTENSION, ReadSpice},
      {SPICE_EXT2, ReadSpice},
      {SPICE_EXT3, ReadSpice},
+      {SPICE_EXT4, ReadSpice},
+      {SPICE_EXT5, ReadSpice},
+      {SPICE_EXT6, ReadSpice},
+      {SPICE_EXT7, ReadSpice},
      {VERILOG_EXTENSION, ReadVerilog},
+      {SYS_VERILOG_EXTENSION, ReadVerilog},
      {NETGEN_EXTENSION, ReadNetgenFile},
      {NULL, NULL}
    };
@@ -858,7 +896,9 @@ char *ReadNetlist(char *fname, int *fnum)

  /* make first pass looking for extension */
  for (index = 0; formats[index].extension != NULL; index++) {
-    if (strstr(fname, formats[index].extension) != NULL) {
+    int extlen = strlen(formats[index].extension);
+    int flen = strlen(fname);
+    if (!strcmp(fname + flen - extlen, formats[index].extension)) {
      return (*(formats[index].proc))(fname, fnum);
    }
  }
@@ -9,11 +9,16 @@
 #define SIM_EXTENSION ".sim"
 #define SPICE_EXTENSION ".spice"
 #define SPICE_EXT2 ".spc"
-#define SPICE_EXT3 ".fspc"
+#define SPICE_EXT3 ".sp"
+#define SPICE_EXT4 ".spi"
+#define SPICE_EXT5 ".fspc"
+#define SPICE_EXT6 ".cir"
+#define SPICE_EXT7 ".ckt"
 #define NETGEN_EXTENSION ".ntg"
 #define CCODE_EXTENSION ".c.code"
 #define ESACAP_EXTENSION ".esa"
 #define VERILOG_EXTENSION ".v"
+#define SYS_VERILOG_EXTENSION ".sv"

 #define LINELENGTH 80

@@ -31,6 +36,7 @@ extern struct hashdict *definitions;
 extern char *nexttok;
 #define SKIPTO(a) do {SkipTok(NULL);} while (!match(nexttok,a))
 extern char *strdtok(char *pstring, char *delim1, char *delim2);
+extern char *GetLineAtTok();
 extern void SkipTok(char *delimiter);
 extern void SkipTokNoNewline(char *delimiter);
 extern void SkipTokComments(char *delimiter);
@@ -43,7 +43,8 @@ extern int  PropertyMerge(char *name, int fnum, char *key, int merge_type,
 		int merge_mask);
 extern void ResolveProperties(char *name1, int file1, char *name2, int file2);
 extern void CopyProperties(struct objlist *obj_to, struct objlist *obj_from);
-extern int PromoteProperty(struct property *, struct valuelist *);
+extern int PromoteProperty(struct property *, struct valuelist *,
+		struct objlist *, struct nlist *);
 extern int SetPropertyDefault(struct property *, struct valuelist *);
 extern struct objlist *LinkProperties(char *model, struct keyvalue *topptr);
 extern int ReduceExpressions(struct objlist *instprop, struct objlist *parprops,
@@ -65,6 +66,15 @@ extern void AssignCircuits(char *name1, int file1, char *name2, int file2);
 /* flatten.c */
 extern int PrematchLists(char *, int, char *, int);

+/* verilog.c */
+struct cellstack {
+	char *cellname;
+	struct cellstack *next;
+};
+
+void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,
+	int blackbox);
+
 /* Define (enumerate) various device classes, largely based on SPICE	*/
 /* model types, mixed with some ext/sim types.				*/

@@ -140,6 +150,7 @@ extern int NoOutput;      /* set this to 1 to disable stdout output */
 extern int Composition;	  /* direction of composition */
 extern int UnixWildcards; /* TRUE if *,?,{},[] only; false if full REGEXP */
 extern int GlobalParallelNone;	/* If TRUE, don't parallel combine any cells */
+extern int GlobalParallelOpen;	/* If TRUE, parallel combine cells w/no-connects */
 /* magic internal flag to restrict searches to recently placed cells */
 extern int QuickSearch;
 /* does re"CellDef"ing a cell add to it or overwrite it??? */
@@ -22,6 +22,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */

 #include <stdio.h>
 #include <ctype.h>
+#include <limits.h>
 #ifdef IBMPC
 #include <alloc.h>
 #endif
@@ -31,13 +32,13 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #endif

 #include "netgen.h"
-#include "hash.h"
 #include "objlist.h"
 #include "regexp.h"
 #include "dbug.h"
 #include "print.h"
 #include "netfile.h"
 #include "netcmp.h"
+#include "hash.h"

 #ifdef TCL_NETGEN
 extern Tcl_Interp *netgeninterp;
@@ -288,8 +289,8 @@ static struct hashdict cell_dict;

 void InitCellHashTable(void)
 {
-    hashfunc = hash;
-    matchfunc = match;
+    hashfunc = hashcase;
+    matchfunc = NULL;
    matchintfunc = matchfile;
    InitializeHashTable(&cell_dict, CELLHASHSIZE);
 }
@@ -975,6 +976,7 @@ struct objlist *CopyObjList(struct objlist *oldlist, unsigned char doforall)
          newob->model.class = NULL;
       else
          newob->model.class = strsave(tmp->model.class);
+       newob->flags = tmp->flags;
       newob->instance.name = (tmp->instance.name) ?
 		strsave(tmp->instance.name) : NULL;
    }
@@ -1112,13 +1114,17 @@ void FreeObjectAndHash(struct objlist *ob, struct nlist *ptr)

 /***************  GENERAL UTILITIES ****************************/

-int NumberOfPorts(char *cellname)
+int NumberOfPorts(char *cellname, int file)
 {
  struct nlist *tp;
  struct objlist *ob;
  int ports;

-  tp = LookupCell(cellname);
+  if (file == -1)
+    tp = LookupCell(cellname);
+  else
+    tp = LookupCellFile(cellname, file);
+
  if (tp == NULL) return(0);
  ports = 0;
  for (ob = tp->cell; ob != NULL; ob = ob->next)
@@ -28,6 +28,8 @@

 #define PROXY (0)		/* Used in model.port record of ports */

+#define NO_CONNECT	1	/* Use in object list to flag an isolated net */
+
 /* Lists of device properties.  Order is defined at the time of	*/
 /* the cell definition; values are sorted at the time instances	*/
 /* are read.							*/
@@ -162,6 +164,7 @@ struct objlist {
 				/* (string) value of property for properties */
     struct valuelist *props;	/* Property record */
  } instance;
+  unsigned char flags;	/* Used by NODE type to flag isolated net */
  int node;		/* the electrical node number of the port/node/pin */
  struct objlist *next;
 };
@@ -192,9 +195,8 @@ struct Permutation {
    struct Permutation *next;
 };

-#define OBJHASHSIZE 997 /* the size of the object and instance hash lists */
+#define OBJHASHSIZE 42073 /* the size of the object and instance hash lists */
                        /* prime numbers are good choices as hash sizes */
-                        /* 101 is a good number for IBMPC */

 /* cell definition for hash table */
 /* NOTE: "file" must come first for the hash matching by name and file */
@@ -242,7 +244,7 @@ extern void FreeObjectAndHash(struct objlist *ob, struct nlist *ptr);
 extern void FreePorts(char *cellname);
 extern struct IgnoreList *ClassIgnore;

-extern int NumberOfPorts(char *cellname);
+extern int NumberOfPorts(char *cellname, int file);
 extern struct objlist *InstanceNumber(struct nlist *tp, int inst);

 extern struct objlist *List(char *list_template);
@@ -310,6 +312,19 @@ extern void GarbageCollect(void);
 extern void InitGarbageCollection(void);
 extern void AddToGarbageList(struct objlist *head);

+extern void DeleteProperties(struct keyvalue **topptr);
+extern void AddProperty(struct keyvalue **topptr, char *key, char *value);
+extern void AddScaledProperty(struct keyvalue **topptr, char *key, char *value, double scale);
+extern void DeleteProperties(struct keyvalue **topptr);
+extern struct objlist *LinkProperties(char *model, struct keyvalue *topptr);
+
+extern void ClassDelete(char *class, int file);
+extern void RemoveShorted(char *class, int file);
+extern void CellRehash(char *name, char *newname, int file);
+
+/* defined in netgen.c */
+extern int ConvertStringToInteger(char *string, int *ival);
+
 #ifdef HAVE_MALLINFO
 void PrintMemoryStats(void);
 #endif
@@ -929,7 +929,7 @@ void ToggleDebug(void)
 void DescribeCell(char *name, int detail)
 {
  Printf("Cell: %s contains %d instances, %d nodes and %d ports\n", name, 
-	 NumberOfInstances(name),  RenumberNodes(name), NumberOfPorts(name));
+	 NumberOfInstances(name),  RenumberNodes(name), NumberOfPorts(name, -1));
  PrintEmbeddingTree(stdout,name,detail);
 }

@@ -801,9 +801,18 @@ void DescribeInstance(char *name, int file)
  {
    if (ob->node > nodemax) nodemax = ob->node;
    else if ((ob->node == -1) && (ob->model.port != PROXY)) {
-      if (disconnectednodes == 0) Fprintf(stderr, "\n");
-      disconnectednodes++;
-      Fprintf(stderr, "Cell %s disconnected node: %s\n", tp->name, ob->name);
+
+      /* All black-box modules and placeholders by definition have all	*/
+      /* disconnected pins, so don't report those.			*/
+
+      if ((!(tp->flags & CELL_PLACEHOLDER)) && (tp->class != CLASS_MODULE)) {
+	// if (disconnectednodes == 0) Fprintf(stderr, "\n");
+        disconnectednodes++;
+	/* Don't report on ports marked "port_match_error", which is just confusing. */
+	if (strcmp(ob->name, "port_match_error")) {
+           Fprintf(stderr, "Cell %s(%d) disconnected node: %s\n", tp->name, tp->file, ob->name);
+	}
+      }
    }
  }
  instlist = (unsigned char *) CALLOC((nodemax + 1), sizeof(unsigned char));
@@ -900,7 +909,7 @@ void PrintLeavesInCell(char *cellname, int filenum)
  np->dumped = 1;

  if (np->class != CLASS_SUBCKT) {
-    Printf("%s; %d ports; Primitive.\n", cellname, NumberOfPorts(cellname));
+    Printf("%s; %d ports; Primitive.\n", cellname, NumberOfPorts(cellname, filenum));
    return;
  }

@@ -913,7 +922,7 @@ void PrintLeavesInCell(char *cellname, int filenum)
      am_a_leaf = 0;
    }

-  if (am_a_leaf) Printf("%s; %d ports\n", cellname, NumberOfPorts(cellname));
+  if (am_a_leaf) Printf("%s; %d ports\n", cellname, NumberOfPorts(cellname, filenum));
  return;
 }

@@ -1026,7 +1035,7 @@ void Query(void)
      break;
    case 'v':
      promptstring("Write Verilog: circuit name: ", repstr);
-      VerilogModule(repstr, filenum, "");
+      VerilogTop(repstr, filenum, "");
      break;
    case 'E':
      promptstring("Write ESACAP: circuit name: ", repstr);
@@ -1063,7 +1072,7 @@ void Query(void)
      ActelLib();
      break;
    case 'S':
-      promptstring("Read SPICE (.ckt) file? ", repstr);
+      promptstring("Read SPICE (.spice) file? ", repstr);
      ReadSpice(repstr, &filenum);
      break;
    case 'V':
@@ -26,6 +26,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #endif

 #include <stdlib.h>  /* for calloc(), free(), getenv() */
+#include <ctype.h>  /* for toupper(), isascii() */
 #ifndef IBMPC
 #include <sys/types.h>	/* for getpwnam() tilde expansion */
 #include <pwd.h>
@@ -40,6 +41,8 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include "objlist.h"
 #include "netfile.h"
 #include "print.h"
+#include "query.h"
+#include "objlist.h"

 // Global storage for parameters from .PARAM
 struct hashdict spiceparams;
@@ -473,15 +476,6 @@ void CleanupSubcell() {
      SetClass(CLASS_MODULE);
 }

-/*------------------------------------------------------*/
-/* Structure for stacking nested subcircuit definitions */
-/*------------------------------------------------------*/
-
-struct cellstack {
-   char *cellname;
-   struct cellstack *next;
-};
-
 /*------------------------------------------------------*/
 /* Push a subcircuit name onto the stack		*/
 /*------------------------------------------------------*/
@@ -874,6 +868,17 @@ skip_ends:
      }
    }

+    /* Ignore anything in a .CONTROL ... .ENDC block */
+    else if (matchnocase(nexttok, ".CONTROL")) {
+	while (1) {
+	    SpiceSkipNewLine();
+	    SkipTok(NULL);
+	    if (EndParseFile()) break;
+	    if (matchnocase(nexttok, ".ENDC"))
+	       break;
+	}
+    }
+
    // Blackbox (library) mode---parse only subcircuits and models;
    // ignore all components.

@@ -935,7 +940,7 @@ skip_ends:
 	 goto baddevice;
      }

-      snprintf(instname, 255, "%s%s", model, inst);
+      snprintf(instname, 255, "%s:%s", model, inst);
      Cell(instname, model, collector, base, emitter);
      pobj = LinkProperties(model, kvlist);
      ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
@@ -1008,7 +1013,7 @@ skip_ends:
 	 goto baddevice;
      }

-      snprintf(instname, 255, "%s%s", model, inst);
+      snprintf(instname, 255, "%s:%s", model, inst);
      Cell(instname, model, drain, gate, source, bulk);
      pobj = LinkProperties(model, kvlist);
      ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
@@ -1099,7 +1104,7 @@ skip_ends:
 	   usemodel = 1;
 	}

-	snprintf(instname, 255, "%s%s", model, inst);
+	snprintf(instname, 255, "%s:%s", model, inst);
 	if (usemodel)
           Cell(instname, model, ctop, cbot);
 	else
@@ -1184,7 +1189,7 @@ skip_ends:
           else if (CountPorts(model, filenum) != 2) {
 	      /* Modeled device:  Make sure it has the right number of ports */
 	      Fprintf(stderr, "Device \"%s\" has wrong number of ports for a "
-			"resistor.\n");
+			"resistor.\n", model);
 	      goto baddevice;
           }
 	   usemodel = 1;
@@ -1192,7 +1197,7 @@ skip_ends:
 	else
 	   strcpy(model, "r");		/* Use default resistor model */

-	snprintf(instname, 255, "%s%s", model, inst);
+	snprintf(instname, 255, "%s:%s", model, inst);
 	if (usemodel)
 	   Cell(instname, model, rtop, rbot);
 	else
@@ -1250,7 +1255,7 @@ skip_ends:
 	 Fprintf(stderr, "Device \"%s\" has wrong number of ports for a diode.\n");
 	 goto baddevice;
      }
-      snprintf(instname, 255, "%s%s", model, inst);
+      snprintf(instname, 255, "%s:%s", model, inst);
      Cell(instname, model, anode, cathode);
      pobj = LinkProperties(model, kvlist);
      ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
@@ -1329,7 +1334,7 @@ skip_ends:
 	else
 	   strcpy(model, "t");		/* Use default xline model */

-	snprintf(instname, 255, "%s%s", model, inst);
+	snprintf(instname, 255, "%s:%s", model, inst);

 	if (usemodel)
 	   Cell(instname, model, node1, node2, node3, node4);
@@ -1412,7 +1417,7 @@ skip_ends:
      else
 	 strcpy(model, "l");		/* Use default inductor model */

-      snprintf(instname, 255, "%s%s", model, inst);
+      snprintf(instname, 255, "%s:%s", model, inst);
      if (usemodel)
 	 Cell(instname, model, end_a, end_b);
      else
@@ -1724,7 +1729,7 @@ skip_ends:
      /* names.								  */

      if (strncmp(instancename, scan->name, strlen(scan->name))) {
-         snprintf(subcktname, 99, "%s%s", scan->name, instancename);
+         snprintf(subcktname, 99, "%s:%s", scan->name, instancename);
         strcpy(instancename, subcktname);
      }
      else {
@@ -1883,20 +1888,36 @@ char *ReadSpiceTop(char *fname, int *fnum, int blackbox)
  CurrentCell = NULL;

  if ((filenum = OpenParseFile(fname, *fnum)) < 0) {
-    char name[100];

-    SetExtension(name, fname, SPICE_EXTENSION);
-    if ((filenum = OpenParseFile(name, *fnum)) < 0) {
-      Fprintf(stderr,"Error in SPICE file read: No file %s\n",name);
+    if (strrchr(fname, '.') == NULL) {
+      char name[1024];
+      SetExtension(name, fname, SPICE_EXTENSION);
+      if ((filenum = OpenParseFile(name, *fnum)) < 0) {
+        Fprintf(stderr, "Error in SPICE file read: No file %s\n", name);
+        *fnum = filenum;
+        return NULL;
+      }
+    }    
+    else {
+      Fprintf(stderr, "Error in SPICE file read: No file %s\n", fname);
      *fnum = filenum;
      return NULL;
-    }    
+    }
  }

-  /* Make sure all SPICE file reading is case insensitive */
-  matchfunc = matchnocase;
-  matchintfunc = matchfilenocase;
-  hashfunc = hashnocase;
+  /* Make sure all SPICE file reading is case insensitive   */
+  /* BUT if a verilog file was read before it, then it will */
+  /* be forced to be case sensitive, caveat end-user.	    */
+
+  if (matchfunc == match) {
+      Printf("Warning:  A case-sensitive file has been read and so the "
+                "SPICE netlist must be treated case-sensitive to match.\n");
+  }
+  else {
+      matchfunc = matchnocase;
+      matchintfunc = matchfilenocase;
+      hashfunc = hashnocase;
+  }

  InitializeHashTable(&spiceparams, OBJHASHSIZE);

@@ -1980,14 +2001,18 @@ void IncludeSpice(char *fname, int parent, struct cellstack **CellStackPtr,
 	/* helps, if the file didn't have an extension.  But	*/
 	/* really, we're getting desperate at this point.	*/

-	if (strchr(fname, '.') == NULL) {
+	if (strrchr(fname, '.') == NULL) {
           SetExtension(name, fname, SPICE_EXTENSION);
           filenum = OpenParseFile(name, parent);
-	}
-        if (filenum < 0) {
-           Fprintf(stderr,"Error in SPICE file include: No file %s\n",name);
-           return;
+	   if (filenum < 0) {
+             Fprintf(stderr, "Error in SPICE file include: No file %s\n", name);
+             return;
+	   }
        }    
+        else {
+          Fprintf(stderr, "Error in SPICE file include: No file %s\n", fname);
+          return;
+	}
     }
  }
  ReadSpiceFile(fname, parent, CellStackPtr, blackbox);
@@ -0,0 +1,8 @@
+#ifndef _TECH_H
+#define _TECH_H
+
+extern int ActelLibPresent(void);
+extern void ActelLib(void);
+extern void VerilogTop(char *name, int fnum, char *filename);
+
+#endif /* _TECH_H */
@@ -52,10 +52,10 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #endif

 #include "netgen.h"
-#include "hash.h"
 #include "objlist.h"
 #include "netfile.h"
 #include "print.h"
+#include "hash.h"

 // See netfile.c for explanation of delimiters.  'X'
 // separates single-character delimiters from two-character delimiters.
@@ -63,6 +63,10 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #define VLOG_PIN_NAME_DELIMITERS "X///**/(**)X()"
 #define VLOG_PIN_CHECK_DELIMITERS "X///**/(**)X,;(){}"

+// Used by portelement structure "flags" record.
+#define PORT_NOT_FOUND	0
+#define PORT_FOUND	1
+
 // Global storage for verilog parameters
 struct hashdict verilogparams;
 // Global storage for verilog definitions
@@ -98,6 +102,31 @@ struct bus *NewBus()
    return (wb);
 }

+//-------------------------------------------------------------------------
+// Find a character c in a string, assuming that string may contain
+// verilog names, where anything, including char c, may appear in the
+// string if it is a backslash-escaped name.  Only the position of
+// character c outside of a verilog name is reported.
+//-------------------------------------------------------------------------
+
+char *strvchr(char *string, char c)
+{
+    char *s;
+
+    for (s = string; *s != '\0'; s++) {
+	if (*s == '\\') {
+	    while (*s != '\0' && *s != ' ') s++;
+	    if (*s == '\0') {
+		Fprintf(stderr, "Error:  Verilog backslash-escaped name"
+			" does not end with a space.\n");
+		break;
+	    }
+	}
+	if (*s == c) return s;
+    }
+    return NULL;
+}
+
 //-------------------------------------------------------------------------
 // Get bus indexes from the notation name[a:b].  If there is only "name"
 // then look up the name in the bus hash list and return the index bounds.
@@ -283,7 +312,7 @@ int GetBusTok(struct bus *wb)

 int GetBus(char *astr, struct bus *wb)
 {
-    char *colonptr, *brackstart, *brackend, *sigend, sdelim;
+    char *colonptr, *brackstart, *brackend, *sigend, sdelim, *aastr;
    int result, start, end;

    if (wb == NULL) return 0;
@@ -302,8 +331,8 @@ int GetBus(char *astr, struct bus *wb)
 	astr++;
 	wb->end = 0;
 	while((*astr != '\0') && (*astr != '}')) {
-	    sigend = strchr(astr, ',');
-	    if (sigend == NULL) sigend = strchr(astr, '}');
+	    sigend = strvchr(astr, ',');
+	    if (sigend == NULL) sigend = strvchr(astr, '}');
 	    if (sigend == NULL) {
 		Printf("Badly formed wire bundle \"%s\"\n", astr - 1);
 		return 1;
@@ -325,15 +354,22 @@ int GetBus(char *astr, struct bus *wb)
 	return 0;
    }

-    brackstart = strchr(astr, '[');
+    // Delimiters may appear in backslash-escaped names. . . ignore these.
+    aastr = astr;
+    if (*aastr == '\\') {
+	aastr++;
+	while (*aastr != ' ' && *aastr != '\\' && *aastr != '\0') aastr++;
+    }
+
+    brackstart = strvchr(aastr, '[');
    if (brackstart != NULL) {
-	brackend = strchr(astr, ']');
+	brackend = strvchr(aastr, ']');
 	if (brackend == NULL) {
 	    Printf("Badly formed array notation \"%s\"\n", astr);
 	    return 1;
 	}
 	*brackend = '\0';
-	colonptr = strchr(astr, ':');
+	colonptr = strvchr(aastr, ':');
 	if (colonptr) *colonptr = '\0';
 	result = sscanf(brackstart + 1, "%d", &start);
 	if (colonptr) *colonptr = ':';
@@ -521,9 +557,43 @@ void CleanupModule() {
   int maxnode = 0;
   int has_submodules = FALSE;
   struct objlist *sobj, *nobj, *lobj, *pobj;
+   struct objlist *myLastPort, *object_it, *myNextObject;

   if (CurrentCell == NULL) return;

+   myLastPort = NULL;
+
+   /* Reorder objects so that all ports come first, before nodes, because
+    * parts of the code depend on it.
+    */
+
+   for (object_it = CurrentCell->cell; object_it && object_it->type <= 0;
+		object_it = myNextObject ) {
+
+       myNextObject = object_it->next;
+       if (!myNextObject)	// end of list
+           continue;
+
+       if (myLastPort == NULL) {
+           if (object_it->type == PORT) {
+               myLastPort = object_it;	    // port at begining of list
+               myNextObject = object_it;    // otherwise skips one
+           }
+           else if (myNextObject->type == PORT) {
+               object_it->next = myNextObject->next;
+               myNextObject->next = CurrentCell->cell;
+               CurrentCell->cell = myNextObject;
+               myLastPort = myNextObject;
+           }
+       }
+       else if (myNextObject->type == PORT) {
+	   object_it->next = myNextObject->next;
+	   myNextObject->next = myLastPort->next;
+	   myLastPort->next = myNextObject;
+	   myLastPort = myNextObject;
+       }
+   }
+
   for (sobj = CurrentCell->cell; sobj; sobj = sobj->next)
      if (sobj->node > maxnode)
 	 maxnode = sobj->node + 1;
@@ -566,11 +636,6 @@ void CleanupModule() {
 /* Structure for stacking nested module definitions	*/
 /*------------------------------------------------------*/

-struct cellstack {
-   char *cellname;
-   struct cellstack *next;
-};
-
 /* Forward declarations */
 extern void IncludeVerilog(char *, int, struct cellstack **, int);

@@ -912,7 +977,7 @@ skip_endmodule:
    }
    else if (match(nexttok, "input") || match(nexttok, "output")
 		|| match(nexttok, "inout")) {
-	struct bus wb;
+	struct bus wb, *nb;
 
 	// Parsing of ports as statements not in the module pin list.
 	wb.start = wb.end = -1;
@@ -945,6 +1010,11 @@ skip_endmodule:
 			    Port(portname);
 			}
 		    }
+		    /* Also register this port as a bus */
+		    nb = NewBus();
+		    nb->start = wb.start;
+		    nb->end = wb.end;
+		    HashPtrInstall(nexttok, nb, &buses);
 		    wb.start = wb.end = -1;
 		}
 		else {
@@ -1058,6 +1128,13 @@ skip_endmodule:
 	 kl->pdefault.ival = 1;
         kl->slop.ival = 0;
      }
+      else if (nexttok[0] == '(') {
+	 /* For now, the netgen verilog parser doesn't handle `define f(X) ... */
+	 SkipNewLine(VLOG_DELIMITERS);
+	 FREE(kl->key);
+	 FREE(kl);
+	 kl = NULL;
+      }
      else if (ConvertStringToInteger(nexttok, &ival) == 1) {
 	 /* Parameter parses as an integer */
      	 kl->type = PROP_INTEGER;
@@ -1071,12 +1148,19 @@ skip_endmodule:
         kl->slop.dval = 0.01;		// One percent default
      }
      else {
-	 /* Treat the parameter as a string */
+         char *toks;
+
+	 /* Treat the parameter as a string; BUT pull everything to */
+	 /* EOL, not just the current token.			    */
+	 toks = GetLineAtTok();
+
      	 kl->type = PROP_STRING;
-	 kl->pdefault.string = strsave(nexttok);
+	 kl->pdefault.string = strsave(toks);
         kl->slop.dval = 0.0;
+
+	 SkipNewLine(VLOG_DELIMITERS);
      }
-      HashPtrInstall(kl->key, kl, &verilogdefs);
+      if (kl) HashPtrInstall(kl->key, kl, &verilogdefs);
    }
    else if (match(nexttok, "`undef")) {
      struct property *kl = NULL;
@@ -1165,7 +1249,7 @@ skip_endmodule:
 	else {	    /* "assign" */
 	    SkipTokComments(VLOG_PIN_CHECK_DELIMITERS);
 	    if (GetBus(nexttok, &wb) == 0) {
-		char *aptr = strchr(nexttok, '[');
+		char *aptr = strvchr(nexttok, '[');
 		if (aptr != NULL) {
 		    *aptr = '\0';
 		    /* Find object of first net in bus */
@@ -1174,9 +1258,16 @@ skip_endmodule:
 		    lhs = LookupObject(nodename, CurrentCell);
 		    *aptr = '[';
 		}
+		else {
+		    strcpy(noderoot, nexttok);
+		    /* Set LHS to the start of the vector */
+		    sprintf(nodename, "%s[%d]", nexttok, wb.start);
+		    lhs = LookupObject(nodename, CurrentCell);
+		}
 	    }
 	    else {
 		lhs = LookupObject(nexttok, CurrentCell);
+		strcpy(noderoot, nexttok);
 	    }
 	    SkipTokComments(VLOG_DELIMITERS);
 	    if (lhs && ((!nexttok) || (!match(nexttok, "=")))) {
@@ -1219,7 +1310,7 @@ skip_endmodule:
 		}
 		else {
 		    if (GetBus(nexttok, &wb2) == 0) {
-			char *aptr = strchr(nexttok, '[');
+			char *aptr = strvchr(nexttok, '[');
 			j = wb2.start;
 			if (aptr != NULL) {
 			    *aptr = '\0';
@@ -1237,13 +1328,21 @@ skip_endmodule:
 			if (rhs != NULL) {
 			    Printf("Improper assignment;  left-hand side cannot "
 					"be parsed.\n");
-			    Printf("Right-hand side is \"%s\".\n", rhs->name);
+			    if (j != -1)
+			    	Printf("Right-hand side is \"%s\".\n", assignroot);
+			    else
+			    	Printf("Right-hand side is \"%s\".\n", rhs->name);
+			    Printf("Improper expression is \"%s\".\n", nexttok);
 			    break;
 			}
 			if (lhs != NULL) {
 			    Printf("Improper assignment;  right-hand side cannot "
 					"be parsed.\n");
-			    Printf("Left-hand side is \"%s\".\n", lhs->name);
+			    if (i != -1)
+			    	Printf("Left-hand side is \"%s\".\n", noderoot);
+			    else
+			    	Printf("Left-hand side is \"%s\".\n", lhs->name);
+			    Printf("Improper expression is \"%s\".\n", nexttok);
 			    /* Not parsable, probably behavioral verilog? */
 			    Printf("Module '%s' is not structural verilog, "
 				    "making black-box.\n", model);
@@ -1308,6 +1407,8 @@ skip_endmodule:
      struct portelement {
 	char *name;	// Name of port in subcell
 	char *net;	// Name of net connecting to port in the parent
+	int   width;	// Width of port, if port is a bus
+	char  flags;	// Used for marking if port was added into netlist
 	struct portelement *next;
      };

@@ -1315,6 +1416,22 @@ skip_endmodule:
      struct objlist *obptr;

      strncpy(modulename, nexttok, 99);
+
+      /* If module name is a verilog primitive, then treat the module as a  */
+      /* black box (this is not a complete list.  Preferable to use hash    */
+      /* function instead of lots of strcmp() calls).			    */
+
+      if (!strcmp(modulename, "buf") || !strcmp(modulename, "notif1") ||
+	    !strcmp(modulename, "not") || !strcmp(modulename, "and") ||
+	    !strcmp(modulename, "or") || !strcmp(modulename, "bufif0") ||
+	    !strcmp(modulename, "bufif1") || !strcmp(modulename, "notif0")) {
+
+         Printf("Module contains verilog primitive '%s'.\n", nexttok);
+         Printf("Module '%s' is not structural verilog, making black-box.\n", model);
+	 SetClass(CLASS_MODULE);
+	 goto skip_endmodule;
+      }
+
      if (!(*CellStackPtr)) {
 	CellDef(fname, filenum);
 	PushStack(fname, CellStackPtr);
@@ -1417,6 +1534,8 @@ nextinst:
 	    else {
 	       new_port = (struct portelement *)CALLOC(1, sizeof(struct portelement));
 	       new_port->name = strsave(nexttok + 1);
+	       new_port->width = -1;
+	       new_port->flags = PORT_NOT_FOUND;
 	       SkipTokComments(VLOG_DELIMITERS);
 	       if (!match(nexttok, "(")) {
 	           Printf("Badly formed subcircuit pin line at \"%s\"\n", nexttok);
@@ -1438,25 +1557,33 @@ nextinst:
 	       }
 	       else {
 		  if (!strcmp(nexttok, "{")) {
-		     char *in_line_net = (char *)MALLOC(1);
-		     char *new_in_line_net = NULL;
-		     *in_line_net = '\0';
-		     /* In-line array---read to "}" */
+		     char *wire_bundle = (char *)MALLOC(1);
+		     char *new_wire_bundle = NULL;
+		     *wire_bundle = '\0';
+		     /* Wire bundle---read to "}" */
 		     while (nexttok) {
-			 new_in_line_net = (char *)MALLOC(strlen(in_line_net) +
+			 new_wire_bundle = (char *)MALLOC(strlen(wire_bundle) +
 				    strlen(nexttok) + 1);
 			 /* Roundabout way to do realloc() becase there is no REALLOC() */
-			 strcpy(new_in_line_net, in_line_net);
-			 strcat(new_in_line_net, nexttok);
-			 FREE(in_line_net);
-			 in_line_net = new_in_line_net;
+			 strcpy(new_wire_bundle, wire_bundle);
+			 strcat(new_wire_bundle, nexttok);
+			 FREE(wire_bundle);
+			 wire_bundle = new_wire_bundle;
 			 if (!strcmp(nexttok, "}")) break;
 			 SkipTokComments(VLOG_PIN_CHECK_DELIMITERS);
 		     }
 		     if (!nexttok) {
-			 Printf("Unterminated net in pin %s\n", in_line_net);
+			 Printf("Unterminated net in pin %s\n", wire_bundle);
 		     }
-		     new_port->net = in_line_net;
+		     new_port->net = wire_bundle;
+		  }
+		  else if (nexttok[0] == '~' || nexttok[0] == '!' || nexttok[0] == '-') {
+		     /* All of these imply that the signal is logically manipulated */
+		     /* in turn implying behavioral code.			    */
+		     Printf("Module '%s' is not structural verilog, "
+				    "making black-box.\n", model);
+		     SetClass(CLASS_MODULE);
+		     goto skip_endmodule;
 		  }
 		  else
 		     new_port->net = strsave(nexttok);
@@ -1558,19 +1685,40 @@ nextinst:
 	    // Check if net name is a wire bus or portion of a bus
 	    if (GetBus(scan->net, &wb) == 0) {
 		int range;
+
+		// This takes care of three situations:
+		// (1) The signal bus length matches the number of instances:
+		//     apply one signal per instance.
+		// (2) The signal bus length is a multiple of the number of instances:
+		//     apply a signal sub-bus to each instance.
+		// (3) The number of instances is a multiple of the signal bus length:
+		//     apply the same signal to each instance.
+
 		if ((arrayend - arraystart) == (wb.end - wb.start)) {
 		    // Net is a bus, but net is split over arrayed instances
 		    Port(scan->name);
 		}
 		else if (wb.start > wb.end) {
-		    range = wb.start - wb.end;
+		    if ((arraystart - arrayend) > (wb.start - wb.end))
+			range = (((arraystart - arrayend) + 1) /
+				    ((wb.start - wb.end) + 1)) - 1;
+		    else
+			range = (((wb.start - wb.end) + 1) /
+				    ((arraystart - arrayend) + 1)) - 1;
+
 		    for (i = range; i >= 0; i--) {
 			sprintf(defport, "%s[%d]", scan->name, i);
 			Port(defport);
 		    }
 		}
 		else {
-		    range = wb.end - wb.start;
+		    if ((arrayend - arraystart) >  (wb.end - wb.start))
+			range = (((arrayend - arraystart) + 1) /
+				    ((wb.end - wb.start) + 1)) - 1;
+		    else
+			range = (((wb.end - wb.start) + 1) /
+				    ((arrayend - arraystart) + 1)) - 1;
+
 		    for (i = 0; i <= range; i++) {
 			sprintf(defport, "%s[%d]", scan->name, i);
 			Port(defport);
@@ -1622,69 +1770,40 @@ nextinst:
 	    int j, result;
 	    struct objlist *bobj;
 	    char *bptr;
-	    int minnet, maxnet, testidx;
+	    int minnet, maxnet, testidx, width;
+
+	    width = portstart - portend;
+	    if (width < 0) width = -width;
+	    width++;
+	    scan->width = width;

 	    result = GetBus(scan->net, &wb);
-	    if (result == -1) {
-		/* CHECK:  THIS CODE SHOULD BE DELETED, IT IS NOT THE ISSUE */
-		/* Not bus notation, but check if signal was defined as a bus */
-		wb.start = wb.end = -1;
-		minnet = maxnet = -1;
-
-		/* Pins should be in index order start->end.  Other nodes */
-		/* should be in order start->end by node number.	  */
-
-		for (bobj = CurrentCell->cell; bobj; bobj = bobj->next) {
-		    if (bobj->type == PORT) {
-			if ((bptr = strchr(bobj->name, '[')) != NULL) {
-			    *bptr = '\0';
-			    if (!strcmp(bobj->name, scan->net)) {
-				*bptr = '[';
-				if (wb.start == -1)
-				    sscanf(bptr + 1, "%d", &wb.start);
-				else
-				    sscanf(bptr + 1, "%d", &wb.end);
-			    }
-			}
-		    }
-		    else if (bobj->type == NODE) {
-			if ((bptr = strchr(bobj->name, '[')) != NULL) {
-			    *bptr = '\0';
-			    if (!strcmp(bobj->name, scan->net)) {
-				if (sscanf(bptr + 1, "%d", &testidx) == 1) {
-				    if (minnet == -1) {
-					minnet = maxnet = bobj->node;
-					wb.start = wb.end = testidx;
-				    }
-				    else if (bobj->node < minnet) {
-					minnet = bobj->node;
-					wb.start = testidx;
-				    }
-				    else if (bobj->node > maxnet) {
-					maxnet = bobj->node;
-					wb.end = testidx;
-				    }
-				}
-			    }
-			    *bptr = '[';
-			}
-		    }
-		}
-		if (wb.start != -1) result = 0;
-	    }
-
 	    if (result == 0) {
-	       if (((wb.start - wb.end) != (portstart - portend)) &&
-		   	((wb.start - wb.end) != (portend - portstart))) {
-		  if (((wb.start - wb.end) != (arraystart - arrayend)) &&
-			((wb.start - wb.end) != (arrayend - arraystart))) {
-		     Fprintf(stderr, "Error:  Net %s bus width does not match "
-				"port %s bus width.\n", scan->net, scan->name);
-		  }
-		  // Otherwise, net is bit-sliced across array of instances.
+	       int match = 0;
+	       int wblen, arraylen;
+
+	       arraylen = arraystart - arrayend;
+	       wblen = wb.start - wb.end;
+
+	       if (arraylen < 0) arraylen = -arraylen;
+	       if (wblen < 0) wblen = -wblen;
+
+	       arraylen++;
+	       wblen++;
+
+	       if ((scan->width * arraylen) == wblen) match = 1;
+	       else if (wblen == scan->width) match = 1;
+	       else if (wblen == arraylen) match = 1;
+	       else {
+		  Fprintf(stderr, "Warning:  Net %s bus width (%d) does not match "
+				"port %s bus width (%d) or array width (%d).\n",
+				scan->net, wblen, scan->name, scan->width, arraylen);
 	       }
-	       else if (wb.start > wb.end) {
-		  char *bptr, *cptr, cchar, *netname;
+
+	       // Net is bit-sliced across array of instances.
+
+	       if (wb.start > wb.end) {
+		  char *bptr = NULL, *cptr = NULL, cchar, *netname;
 		  unsigned char is_bundle = 0;
 		  struct bus wbb;

@@ -1695,8 +1814,8 @@ nextinst:
 		  if (*netname == '{') {
 		     is_bundle = 1;
 		     netname++;
-		     cptr = strchr(netname, ',');
-		     if (cptr == NULL) cptr = strchr(netname, '}');
+		     cptr = strvchr(netname, ',');
+		     if (cptr == NULL) cptr = strvchr(netname, '}');
 		     if (cptr == NULL) cptr = netname + strlen(netname) - 1;
 		     cchar = *cptr;
 		     *cptr = '\0';
@@ -1705,14 +1824,12 @@ nextinst:
 		  // Remove indexed part of scan->net
 		  if (GetBus(netname, &wbb) == 0) {
 		     i = wbb.start;
-		     if ((bptr = strchr(netname, '[')) != NULL)
+		     if ((bptr = strvchr(netname, '[')) != NULL)
 			 *bptr = '\0';
 		  }
 		  else
 		     i = -1;

-		  if (is_bundle) *cptr = cchar;	 /* Restore bundle delimiter */
-		  
 		  while (1) {
 	             new_port = (struct portelement *)CALLOC(1,
 				sizeof(struct portelement));
@@ -1723,6 +1840,7 @@ nextinst:
 		     else
 			 sprintf(vname, "%s[%d]", netname, i); 
 	             new_port->net = strsave(vname);
+		     new_port->width = scan->width;

 		     if (last == NULL)
 			head = new_port;
@@ -1736,38 +1854,58 @@ nextinst:

 		     if (portstart > portend) j--;
 		     else j++;
-		     if (wbb.start > wbb.end) i--;
-		     else i++;
+		     if (i != -1) {
+			if (wbb.start > wbb.end) i--;
+			else i++;
+		     }

 		     if (is_bundle &&
 			    ((i == -1) ||
 			    ((wbb.start > wbb.end) && (i < wbb.end)) ||
-			    ((wbb.start < wbb.end) && (i > wbb.end)))) {
+			    ((wbb.start <= wbb.end) && (i > wbb.end)))) {
 		         if (bptr) *bptr = '[';

 			 netname = cptr + 1;
-		         cptr = strchr(netname, ',');
-			 if (cptr == NULL) cptr = strchr(netname, '}');
+			 if (cptr) *cptr = cchar; /* Restore previous bundle delimiter */
+		         cptr = strvchr(netname, ',');
+			 if (cptr == NULL) cptr = strvchr(netname, '}');
 			 if (cptr == NULL) cptr = netname + strlen(netname) - 1;
 			 cchar = *cptr;
 			 *cptr = '\0';

 			 if (GetBus(netname, &wbb) == 0) {
 			    i = wbb.start;
-			    if ((bptr = strchr(netname, '[')) != NULL)
+			    if ((bptr = strvchr(netname, '[')) != NULL)
 				*bptr = '\0';
 			 }
 			 else i = -1;
-
-			 *cptr = cchar;	    /* Restore delimiter */
 		     }
 		  }
 		  FREE(scan);
 		  scan = last;
+		  if (cptr) *cptr = cchar; /* Restore bundle delimiter */
 	       }
 	    }
 	    else if (portstart != portend) {
-	       Fprintf(stderr, "Error:  Single net %s is connected to bus port %s\n",
+	       /* If the name starts with "_noconnect_", then it was an
+		* auto-generated name that incorrectly assumed a single-bit
+		* wide signal because it did not have a module prototype.
+		* Rewrite the noconnect name as an array.  This just means
+		* that the verilog had an empty list "()" and the initial
+		* assumption was wrong.  If not all instances agree on the
+		* size, then this will eventually generate an error.
+		*/
+	       if (!strncmp(scan->net, "_noconnect_", 11) &&
+			(strchr(scan->net, '\[') == NULL) && (width > 1)) {
+		  char *savenet = scan->net;
+		  char *newnet = MALLOC(strlen(scan->net) + 12);
+		  sprintf(newnet, "%s[%d:0]", scan->net, scan->width - 1);
+		  FREE(savenet);
+		  scan->net = newnet;
+		  continue;	/* Re-process this entry */
+	       }
+	       else
+	          Fprintf(stderr, "Error:  Single net %s is connected to bus port %s\n",
 			scan->net, scan->name);
 	    }
 	 }
@@ -1793,7 +1931,7 @@ nextinst:
         obptr = LookupInstance(locinst, CurrentCell);
         if (obptr != NULL) {
            do {
-	       struct bus wb;
+	       struct bus wb, wb2;
 	       char *obpinname;
 	       int obpinidx;

@@ -1810,19 +1948,27 @@ nextinst:
 	       obpinidx = -1;
 	       while (scan != NULL) {
 		  if (match(obpinname, scan->name)) {
+		     scan->flags |= PORT_FOUND;
 		     break;
 		  }
 		  scan = scan->next;
 	       }
 	       if (scan == NULL) {
-		  Fprintf(stderr, "Error:  No match in call for pin %s\n", obpinname);
-		  break;
-	       }
+		  char localnet[100];

-	       if (GetBus(scan->net, &wb) == 0) {
+		  /* Assume an implicit unconnected pin */
+		  sprintf(localnet, "_noconnect_%d_", localcount++);
+		  Node(localnet);
+		  join(localnet, obptr->name);
+		  Fprintf(stderr,
+			 "Note:  Implicit pin %s in instance %s of %s in cell %s\n",
+			 obpinname, locinst, modulename, CurrentCell->name);
+	       }
+	       else if (GetBus(scan->net, &wb) == 0) {
+		   char *bptr2;
 		   char *scanroot;
 		   scanroot = strsave(scan->net);
-		   brackptr = strchr(scanroot, '[');
+		   brackptr = strvchr(scanroot, '[');
 		   if (brackptr) *brackptr = '\0';

 		   if (arraystart == -1) {
@@ -1854,16 +2000,37 @@ nextinst:
 		   else {
 		       // Instance must be an array
 		       char netname[128];
-		       int slice;
-		       if (wb.start >= wb.end && arraystart >= arrayend)
-			   slice = wb.start - (arraystart - i);
-		       else if (wb.start < wb.end && arraystart > arrayend)
-			   slice = wb.start + (arraystart - i);
-		       else if (wb.start > wb.end && arraystart < arrayend)
-			   slice = wb.start - (arraystart + i);
-		       else // (wb.start < wb.end && arraystart < arrayend)
-			   slice = wb.start + (arraystart + i);
-			   
+		       int slice, portlen, siglen;
+
+		       /* Get the array size of the port for bit slicing */
+		       portlen = (scan->width < 0) ? 1 : scan->width;
+
+		       /* Get the full array size of the connecting bus */
+		       GetBus(scanroot, &wb2);
+		       siglen = wb2.start - wb2.end;
+		       if (siglen < 0) siglen = -siglen;
+		       siglen++;
+
+		       // If signal array is smaller than the portlength *
+		       // length of instance array, then the signal wraps.
+
+		       if (wb2.start >= wb2.end && arraystart >= arrayend) {
+			   slice = wb.start - (arraystart - i) * portlen;
+			   while (slice < wb2.end) slice += siglen;
+		       }
+		       else if (wb2.start < wb2.end && arraystart > arrayend) {
+			   slice = wb.start + (arraystart - i) * portlen;
+			   while (slice > wb2.end) slice -= siglen;
+		       }
+		       else if (wb2.start > wb2.end && arraystart < arrayend) {
+			   slice = wb.start - (arraystart + i) * portlen;
+			   while (slice < wb2.end) slice += siglen;
+		       }
+		       else { // (wb2.start < wb2.end && arraystart < arrayend)
+			   slice = wb.start + (arraystart + i) * portlen;
+			   while (slice > wb2.end) slice -= siglen;
+		       }
+
 		       sprintf(netname, "%s[%d]", scanroot, slice);
 	               if (LookupObject(netname, CurrentCell) == NULL) Node(netname);
 	               join(netname, obptr->name);
@@ -1874,6 +2041,89 @@ nextinst:
 	           if (LookupObject(scan->net, CurrentCell) == NULL) Node(scan->net);
 	           join(scan->net, obptr->name);
 	       }
+
+	       /* Before exiting the loop, check if all ports in the	*/
+	       /* scan list were handled.				*/
+
+	       if ((obptr->next == NULL) || (obptr->next->type <= FIRSTPIN)) {
+	          for (scan = head; scan; scan = scan->next) {
+	             if (!(scan->flags & PORT_FOUND)) {
+		        if (tp->flags & CELL_PLACEHOLDER) {
+			   char tempname[128];
+			   int maxnode;
+
+		           /* This pin was probably implicit in the first call */
+		           /* and so it needs to be added to the definition.	 */
+
+			   ReopenCellDef(modulename, filenum);
+		           Port(scan->name);
+			   ReopenCellDef((*CellStackPtr)->cellname, filenum);
+
+			   /* obptr->next now gets the new port.  Update the	*/
+			   /* port number, and copy class and instance name.	*/
+			   nobj = GetObject();
+			   sprintf(tempname, "%s%s%s", obptr->instance.name,
+						SEPARATOR, scan->name);
+			   nobj->name = strsave(tempname);
+			   nobj->model.class = strsave(obptr->model.class);
+			   nobj->instance.name = strsave(obptr->instance.name);
+			   nobj->type = obptr->type + 1;
+			   nobj->next = obptr->next;
+			   nobj->node = -1;
+			   obptr->next = nobj;
+      			   HashPtrInstall(nobj->name, nobj, &(CurrentCell->objdict));
+
+	           	   if (LookupObject(scan->net, CurrentCell) == NULL)
+			      Node(scan->net);
+	           	   join(scan->net, nobj->name);
+	             	   scan->flags |= PORT_FOUND;
+
+			   /* Now any previous instance of the same cell must	*/
+			   /* insert the same additional pin as a no-connect.	*/
+			   /* NOTE:  This should be running a callback on all	*/
+			   /* cells in the file, not just CurrentCell.		*/
+
+			   for (sobj = CurrentCell->cell; sobj && (sobj != obptr);
+					sobj = sobj->next) {
+			      if (sobj->type == FIRSTPIN) {
+				 if (match(sobj->model.class, obptr->model.class)) {
+				    while (sobj->next && (sobj->next->type > FIRSTPIN))
+				       sobj = sobj->next;
+				    /* Stop when reaching the current instance */
+				    if (sobj->type == obptr->type + 1) break;
+				    nobj = GetObject();
+				    sprintf(tempname, "%s%s%s", sobj->instance.name,
+						SEPARATOR, scan->name);
+				    nobj->name = strsave(tempname);
+				    nobj->model.class = strsave(sobj->model.class);
+				    nobj->instance.name = strsave(sobj->instance.name);
+				    nobj->type = obptr->type + 1;
+				    nobj->node = -1;
+				    nobj->next = sobj->next;
+				    sobj->next = nobj;
+      				    HashPtrInstall(nobj->name, nobj,
+							&(CurrentCell->objdict));
+
+		  	   	    sprintf(tempname, "_noconnect_%d_", localcount++);
+		  	   	    Node(tempname);
+		  	   	    join(tempname, nobj->name);
+		  	   	    Fprintf(stderr, "Note:  Implicit pin %s in instance "
+						"%s of %s in cell %s\n",
+			 			scan->name, sobj->instance.name,
+						modulename, CurrentCell->name);
+				 }
+			      }
+			   }
+		        }
+		        else {
+		           Fprintf(stderr, "Error:  Instance %s has pin %s which is "
+					"not in the %s cell definition.\n",
+					locinst, scan->name, modulename);
+		        }
+	             }
+	          }
+	       }
+
 	       obptr = obptr->next;
            } while (obptr != NULL && obptr->type > FIRSTPIN);
 	 }
@@ -1931,14 +2181,21 @@ char *ReadVerilogTop(char *fname, int *fnum, int blackbox)
  CurrentCell = NULL;

  if ((filenum = OpenParseFile(fname, *fnum)) < 0) {
-    char name[100];

-    SetExtension(name, fname, VERILOG_EXTENSION);
-    if ((filenum = OpenParseFile(name, *fnum)) < 0) {
-      Fprintf(stderr,"Error in Verilog file read: No file %s\n",name);
-      *fnum = filenum;
-      return NULL;
+    if (strchr(fname, '.') == NULL) {
+      char name[1024];
+      SetExtension(name, fname, VERILOG_EXTENSION);
+      if ((filenum = OpenParseFile(name, *fnum)) < 0) {
+        Fprintf(stderr, "Error in Verilog file read: No file %s\n", name);
+        *fnum = filenum;
+        return NULL;
+      }
    }    
+    else {
+       Fprintf(stderr, "Error in Verilog file read: No file %s\n", fname);
+       *fnum = filenum;
+       return NULL;
+    }
  }

  /* All Verilog file reading is case sensitive.  However:  if	*/
@@ -1949,6 +2206,11 @@ char *ReadVerilogTop(char *fname, int *fnum, int blackbox)
     Printf("Warning:  A case-insensitive file has been read and so the	"
 		"verilog file must be treated case-insensitive to match.\n");
  }
+  else {
+     matchfunc = match;
+     matchintfunc = matchfile;
+     hashfunc = hashcase;
+  }

  InitializeHashTable(&verilogparams, OBJHASHSIZE);
  InitializeHashTable(&verilogdefs, OBJHASHSIZE);
@@ -2036,11 +2298,15 @@ void IncludeVerilog(char *fname, int parent, struct cellstack **CellStackPtr,
 	if (strchr(fname, '.') == NULL) {
           SetExtension(name, fname, VERILOG_EXTENSION);
           filenum = OpenParseFile(name, parent);
+	   if (filenum < 0) {
+	      fprintf(stderr,"Error in Verilog file include: No file %s\n", name);
+	      return;
+	   }
        }
-	if (filenum < 0) {
+	else {
 	   fprintf(stderr,"Error in Verilog file include: No file %s\n", fname);
 	   return;
-        }    
+        }
     }
  }
  ReadVerilogFile(fname, parent, CellStackPtr, blackbox);
@@ -23,6 +23,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include <stdio.h>
 #include <stdarg.h>
 #include <ctype.h>
+#include <time.h>

 #ifdef IBMPC
 #include <stdlib.h>  /* for strtol on PC */
@@ -33,6 +34,8 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include "netfile.h"
 #include "hash.h"
 #include "print.h"
+#include "xilinx.h"
+#include "flatten.h"

 #define XILINXHASHSIZE 99
 static long xilinxhashbase = 0xA00;
@@ -132,10 +135,8 @@ char *xilinx_class(model)
 	}
 	return(model);
 }
-void
-Xilinx(cellname, filename)
-	char *cellname;
-	char *filename;
+
+void Xilinx(char *cellname, char *filename)
 {
 	char Path[500];
 	char FileName[500];
@@ -163,8 +164,7 @@ Xilinx(cellname, filename)
 	CloseFile(FileName);
 }

-xilinxCell(cell)
-	char *cell;
+int xilinxCell(char *cell)
 {
 	struct nlist *nl;
 	struct objlist *ob;
@@ -252,9 +252,7 @@ struct objlist *xilinx_gate(ob,nl)
 	return(nob);
 }

-xilinx_sym(nl,gob)
-	struct nlist *nl;
-	struct objlist *gob;
+void xilinx_sym(struct nlist *nl, struct objlist *gob)
 {
 	struct objlist *ob;
 	char *cp,*rindex();
@@ -0,0 +1,10 @@
+#ifndef _XILINX_H
+#define _XILINX_H
+
+extern void xilinx_sym(struct nlist *nl, struct objlist *gob);
+extern void Xilinx(char *cellname, char *filename);
+extern int xilinxCell(char *cell);
+extern int XilinxLibPresent(void);
+extern void XilinxLib(void);
+
+#endif /* _XILINX_H */
@@ -4,4 +4,6 @@
 # all of its config scripts in a different directory than the configure
 # script itself.

-( CFLAGS="-g" ; export CFLAGS ; cd scripts ; ./configure "$@" )
+export CFLAGS="$CFLAGS -g"
+cd scripts
+exec ./configure "$@"
@@ -8,6 +8,8 @@ SCRIPTINSTALL = $(DESTDIR)${INSTALL_PYDIR}

 include ${NETGENDIR}/defs.mak

+CLEANS += lvs_manager.py
+
 main: lvs_manager.py

 tcl-main: lvs_manager.py
@@ -27,6 +29,7 @@ lvs_manager.py: lvs_manager.py.in
 $(DESTDIR)${INSTALL_PYDIR}/lvs_manager.py: lvs_manager.py
 	${RM} $@
 	${CP} lvs_manager.py $@
+	chmod a+x $@

 $(DESTDIR)${INSTALL_PYDIR}/treeviewsplit.py: treeviewsplit.py
 	${RM} $@
@@ -343,7 +343,7 @@ class LVSManager(ttk.Frame):
            techbase = os.path.split(techname)[1]
            self.tech = os.path.splitext(techbase)[0]
            self.lvs_setup = techname
-            self.toppane.title2_frame.layout_select.config(text = self.tech)
+            self.toppane.title2_frame.tech_select.config(text = self.tech)

    def choose_layout(self):
        try:
@@ -358,30 +358,37 @@ class LVSManager(ttk.Frame):
 			title = "Choose a layout cell to compare.")
        if cellname != '':
            print("Selected compare cell " + cellname)
+            self.layout = cellname
            cellbase = os.path.split(cellname)[1]
-            self.layout = os.path.splitext(cellbase)[0]
-            self.toppane.title2_frame.layout_select.config(text = self.layout)
+            layoutname = os.path.splitext(cellbase)[0]
+            self.toppane.title2_frame.layout_select.config(text = layoutname)
+            fileext = os.path.splitext(cellbase)[1]
+            if fileext == '.mag':
+                self.toppane.title2_frame.layout_label.config(text = 'Layout:')
+            else:
+                self.toppane.title2_frame.layout_label.config(text = 'Layout netlist:')

    def choose_netlist(self):
        try:
            project_path = self.rootpath
-            initdirname = self.rootpath + '/netlist/' + self.project + '.spi'
+            initdirname = self.rootpath + '/netlist/' + self.project + '.spice'
        except:
            print('Must choose a project first.')
            return
        cellname = filedialog.askopenfilename(multiple=False,
 			initialdir = initdirname,
-			filetypes = (("Spice netlist", "*.spi"),("Verilog netlist", "*.v")),
+			filetypes = (("Spice netlist", "*.spice"),("Verilog netlist", "*.v"),("All Files","*.*")),
 			title = "Choose a netlist to compare.")
        if cellname != '':
            print("Selected compare cell " + cellname)
+            self.schematic = cellname
            cellbase = os.path.split(cellname)[1]
-            self.schematic = os.path.splitext(cellbase)[0]
-            self.toppane.title2_frame.schem_select.config(text = self.schematic)
+            schematic_name = os.path.splitext(cellbase)[0]
+            self.toppane.title2_frame.schem_select.config(text = schematic_name)
            fileext = os.path.splitext(cellbase)[1]
            if fileext == '.v':
                self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
-            elif fileext == '.sp' or fileext == '.spi' or fileext == '.spice' or fileext == '.spc' or fileext == '.ckt':
+            elif fileext == '.sp' or fileext == '.spice' or fileext == '.spi' or fileext == '.spc' or fileext == '.ckt':
                self.toppane.title2_frame.schem_label.config(text = 'SPICE netlist:')
            elif fileext == '.cdl':
                self.toppane.title2_frame.schem_label.config(text = 'CDL netlist:')
@@ -433,7 +440,10 @@ class LVSManager(ttk.Frame):
                self.logfile = None

            # Put new log file called 'lvs.log' in the mag/ subdirectory
-            self.logfile = open(rootpath + '/layout/lvs.log', 'w')
+            if os.path.exists(rootpath + '/layout'):
+                self.logfile = open(rootpath + '/layout/lvs.log', 'w')
+            else:
+                self.logfile = open(rootpath + '/lvs.log', 'w')
            # Print some initial information to the logfile.
            self.logprint('Starting new log file ' + datetime.datetime.now().strftime('%c'),
 				doflush=True)
@@ -444,15 +454,23 @@ class LVSManager(ttk.Frame):
            # Cell name is the same as project name initially
            self.layout = self.project
            self.schematic = self.project
-            self.toppane.title2_frame.layout_select.config(text = self.layout)
-            self.toppane.title2_frame.schem_select.config(text = self.schematic)
+            layname = os.path.splitext(os.path.split(self.layout)[1])[0]
+            self.toppane.title2_frame.layout_select.config(text = layname)
+            schemname = os.path.splitext(os.path.split(self.schematic)[1])[0]
+            self.toppane.title2_frame.schem_select.config(text = schemname)

            # Update schematic button
-            if os.path.isfile(rootpath + '/verilog/' + self.schematic + '.v'):
+            if os.path.splitext(self.schematic)[1] == '.v':
                self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
            else:
                self.toppane.title2_frame.schem_label.config(text = 'Schematic netlist:')

+            # Update layout button
+            if os.path.splitext(self.layout)[1] == '.mag':
+                self.toppane.title2_frame.schem_label.config(text = 'Layout:')
+            else:
+                self.toppane.title2_frame.schem_label.config(text = 'Layout netlist:')
+
            # If there is a comparison file that post-dates both netlists, load it.
            self.check_lvs()
        return True
@@ -567,8 +585,8 @@ class LVSManager(ttk.Frame):
        # load LVS results from comp.json
        project_path = self.rootpath
        project_name = self.project
-        layout_path = project_path + '/layout/' + project_name + '.spc'
-        net_path = project_path + '/netlist/' + project_name + '.spi'
+        layout_path = project_path + '/layout/' + project_name + '.spice'
+        net_path = project_path + '/netlist/' + project_name + '.spice'
        comp_path = project_path + '/layout/comp.json'

        if os.path.exists(layout_path) and os.path.exists(net_path) and os.path.exists(comp_path):
@@ -599,7 +617,7 @@ class LVSManager(ttk.Frame):
            mproc.stdin.write("ext2spice cthresh infinite\n")
            mproc.stdin.write("ext2spice rthresh infinite\n")
            mproc.stdin.write("ext2spice blackbox on\n")
-            mproc.stdin.write("ext2spice -o " + self.layout + ".spi\n")
+            mproc.stdin.write("ext2spice -o " + self.layout + ".spice\n")
            mproc.stdin.write("quit -noprompt\n")
            magicout = mproc.communicate()[0]
            self.printwarn(magicout)
@@ -607,8 +625,8 @@ class LVSManager(ttk.Frame):
                print('Failure to generate new layout netlist.')
                return False

-            # Move .spi netlist to project_dir/netlist/lvs/
-            shutil.move(project_path + '/layout/' + self.layout + '.spi', layout_path)
+            # Move .spice netlist to project_dir/netlist/lvs/
+            shutil.move(project_path + '/layout/' + self.layout + '.spice', layout_path)
            # Remove extraction files
            for file in os.listdir(project_path + '/layout'):
                if os.path.splitext(file)[1] == '.ext':
@@ -625,17 +643,37 @@ class LVSManager(ttk.Frame):

        project_path = self.rootpath
        project_name = self.project
-        comp_path = project_path + '/layout/comp.json'
+
+        # Diagnostic:
+        print('project_name is ' + project_name)
+        print('project_path is ' + project_path)
+        print('self.layout is ' + self.layout)
+        print('self.schematic is ' + self.schematic)
+        print('self.lvs_setup is ' + self.lvs_setup)
+
        has_vlog = False
        vlog_path = project_path + '/verilog/' + project_name + '.v'

-        layout_path = project_path + '/netlist/lvs/' + self.layout + '.spi'
-        net_path = project_path + '/netlist/schem/' + self.schematic + '.spi'
-        layout_src = project_path + '/layout/' + self.layout + '.mag'
+        if os.path.isfile(self.layout):
+            layout_path = self.layout
+            layout_src = None
+        else:
+            layout_path = project_path + '/netlist/lvs/' + self.layout + '.spice'
+            layout_src = project_path + '/layout/' + self.layout + '.mag'
+
+        comp_dir = os.path.split(layout_path)[0]
+        comp_path = comp_dir + '/comp.json'
+
+        if os.path.isfile(self.schematic):
+            net_path = self.schematic
+        else:
+            net_path = project_path + '/netlist/schem/' + self.schematic + '.spice'

        # Does the setup file exist (this is optional)?
-        if self.lvs_setup != '' and not os.path.isfile('setup.tcl'):
+        if self.lvs_setup == '' and not os.path.isfile('setup.tcl'):
            print('No technology setup file selected.')
+        elif not os.path.isfile(self.lvs_setup):
+            print("Can't find technology setup file " + self.lvs_setup)

        # Does schematic netlist exist?
        if not os.path.isfile(vlog_path) and not os.path.isfile(net_path):
@@ -643,14 +681,16 @@ class LVSManager(ttk.Frame):
            return

        # Does LVS netlist subdirectory exist?
-        if not os.path.exists(project_path + '/netlist/lvs'):
-            os.makedirs(project_path + '/netlist/lvs')
+        if os.path.exists(project_path + '/netlist'):
+            if not os.path.exists(project_path + '/netlist/lvs'):
+                os.makedirs(project_path + '/netlist/lvs')

        # Does layout netlist exist and is it current?
-        if not self.generate_layout_netlist(layout_path, layout_src, project_path):
-            return False
+        if layout_src:
+            if not self.generate_layout_netlist(layout_path, layout_src, project_path):
+                return False

-        # Final check
+        # Final checks
        if not os.path.isfile(layout_path):
            print('Error:  No netlist generated from magic.')
            return
@@ -662,26 +702,27 @@ class LVSManager(ttk.Frame):
            with open(layout_path) as ifile:
                spitext = ifile.read()

-            # spilines = spitext.replace(',', '|')
-            # with open(layout_path, 'w') as ofile:
-            #     ofile.write(spilines)
-
        # Check the netlist to see if the cell to match is a subcircuit.  If
        # not, then assume it is the top level.

+        layoutcell = os.path.splitext(os.path.split(self.layout)[1])[0]
        is_subckt = False
+        subname = None
        subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
        dutlines = spitext.replace('\n+', ' ').splitlines()
        for line in dutlines:
            lmatch = subrex.match(line)
            if lmatch:
                subname = lmatch.group(1)
-                if subname == self.layout:
+                if subname == layoutcell:
                    is_subckt = True
                    break

        if is_subckt:
-            layout_arg = layout_path + ' ' + self.layout
+            layout_arg = self.layout + ' ' + layoutcell
+            layout_text = '"' + layout_arg + '"'
+        elif subname:
+            layout_arg = self.layout + ' ' + subname
            layout_text = '"' + layout_arg + '"'
        else:
            layout_arg = layout_path
@@ -690,8 +731,39 @@ class LVSManager(ttk.Frame):
        if has_vlog:
            schem_arg = vlog_path + ' ' + self.schematic
        else:
-            schem_arg = net_path + ' ' + self.schematic
-        schem_text = '"' + schem_arg + '"'
+            # Final checks
+            if not os.path.isfile(net_path):
+                print('Error:  No netlist from schematic.')
+                return
+
+            with open(net_path) as ifile:
+                spitext = ifile.read()
+
+            # Check the netlist to see if the cell to match is a subcircuit.  If
+            # not, then assume it is the top level.
+
+            schemcell = os.path.splitext(os.path.split(self.schematic)[1])[0]
+            subname = None
+            is_subckt = False
+            subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
+            dutlines = spitext.replace('\n+', ' ').splitlines()
+            for line in dutlines:
+                lmatch = subrex.match(line)
+                if lmatch:
+                    subname = lmatch.group(1)
+                    if subname == schemcell:
+                        is_subckt = True
+                        break
+
+            if is_subckt:
+                schem_arg = self.schematic + ' ' + schemcell
+                schem_text = '"' + schem_arg + '"'
+            elif subname:
+                schem_arg = self.schematic + ' ' + subname
+                schem_text = '"' + schem_arg + '"'
+            else:
+                schem_arg = net_path
+                schem_text = schem_arg

        # Remove any previous comparison output file
        comp_out_path = os.path.splitext(comp_path)[0] + '.out'
@@ -708,7 +780,7 @@ class LVSManager(ttk.Frame):
        self.lvsproc = subprocess.Popen(['netgen', '-batch', 'lvs',
 		layout_arg, schem_arg,
 		self.lvs_setup, comp_out_path, '-json', '-blackbox'],
-		cwd=project_path + '/layout',
+		cwd=comp_dir,
 		stdout=subprocess.PIPE, stderr=subprocess.PIPE, bufsize=0)
        # This is largely unnecessary as netgen usually runs to completion very quickly.
        self.watchclock(comp_path)
@@ -343,7 +343,7 @@ class LVSManager(ttk.Frame):
            techbase = os.path.split(techname)[1]
            self.tech = os.path.splitext(techbase)[0]
            self.lvs_setup = techname
-            self.toppane.title2_frame.layout_select.config(text = self.tech)
+            self.toppane.title2_frame.tech_select.config(text = self.tech)

    def choose_layout(self):
        try:
@@ -358,30 +358,37 @@ class LVSManager(ttk.Frame):
 			title = "Choose a layout cell to compare.")
        if cellname != '':
            print("Selected compare cell " + cellname)
+            self.layout = cellname
            cellbase = os.path.split(cellname)[1]
-            self.layout = os.path.splitext(cellbase)[0]
-            self.toppane.title2_frame.layout_select.config(text = self.layout)
+            layoutname = os.path.splitext(cellbase)[0]
+            self.toppane.title2_frame.layout_select.config(text = layoutname)
+            fileext = os.path.splitext(cellbase)[1]
+            if fileext == '.mag':
+                self.toppane.title2_frame.layout_label.config(text = 'Layout:')
+            else:
+                self.toppane.title2_frame.layout_label.config(text = 'Layout netlist:')

    def choose_netlist(self):
        try:
            project_path = self.rootpath
-            initdirname = self.rootpath + '/netlist/' + self.project + '.spi'
+            initdirname = self.rootpath + '/netlist/' + self.project + '.spice'
        except:
            print('Must choose a project first.')
            return
        cellname = filedialog.askopenfilename(multiple=False,
 			initialdir = initdirname,
-			filetypes = (("Spice netlist", "*.spi"),("Verilog netlist", "*.v")),
+			filetypes = (("Spice netlist", "*.spice"),("Verilog netlist", "*.v"),("All Files","*.*")),
 			title = "Choose a netlist to compare.")
        if cellname != '':
            print("Selected compare cell " + cellname)
+            self.schematic = cellname
            cellbase = os.path.split(cellname)[1]
-            self.schematic = os.path.splitext(cellbase)[0]
-            self.toppane.title2_frame.schem_select.config(text = self.schematic)
+            schematic_name = os.path.splitext(cellbase)[0]
+            self.toppane.title2_frame.schem_select.config(text = schematic_name)
            fileext = os.path.splitext(cellbase)[1]
            if fileext == '.v':
                self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
-            elif fileext == '.sp' or fileext == '.spi' or fileext == '.spice' or fileext == '.spc' or fileext == '.ckt':
+            elif fileext == '.sp' or fileext == '.spice' or fileext == '.spi' or fileext == '.spc' or fileext == '.ckt':
                self.toppane.title2_frame.schem_label.config(text = 'SPICE netlist:')
            elif fileext == '.cdl':
                self.toppane.title2_frame.schem_label.config(text = 'CDL netlist:')
@@ -433,7 +440,10 @@ class LVSManager(ttk.Frame):
                self.logfile = None

            # Put new log file called 'lvs.log' in the mag/ subdirectory
-            self.logfile = open(rootpath + '/layout/lvs.log', 'w')
+            if os.path.exists(rootpath + '/layout'):
+                self.logfile = open(rootpath + '/layout/lvs.log', 'w')
+            else:
+                self.logfile = open(rootpath + '/lvs.log', 'w')
            # Print some initial information to the logfile.
            self.logprint('Starting new log file ' + datetime.datetime.now().strftime('%c'),
 				doflush=True)
@@ -444,15 +454,23 @@ class LVSManager(ttk.Frame):
            # Cell name is the same as project name initially
            self.layout = self.project
            self.schematic = self.project
-            self.toppane.title2_frame.layout_select.config(text = self.layout)
-            self.toppane.title2_frame.schem_select.config(text = self.schematic)
+            layname = os.path.splitext(os.path.split(self.layout)[1])[0]
+            self.toppane.title2_frame.layout_select.config(text = layname)
+            schemname = os.path.splitext(os.path.split(self.schematic)[1])[0]
+            self.toppane.title2_frame.schem_select.config(text = schemname)

            # Update schematic button
-            if os.path.isfile(rootpath + '/verilog/' + self.schematic + '.v'):
+            if os.path.splitext(self.schematic)[1] == '.v':
                self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
            else:
                self.toppane.title2_frame.schem_label.config(text = 'Schematic netlist:')

+            # Update layout button
+            if os.path.splitext(self.layout)[1] == '.mag':
+                self.toppane.title2_frame.schem_label.config(text = 'Layout:')
+            else:
+                self.toppane.title2_frame.schem_label.config(text = 'Layout netlist:')
+
            # If there is a comparison file that post-dates both netlists, load it.
            self.check_lvs()
        return True
@@ -567,8 +585,8 @@ class LVSManager(ttk.Frame):
        # load LVS results from comp.json
        project_path = self.rootpath
        project_name = self.project
-        layout_path = project_path + '/layout/' + project_name + '.spc'
-        net_path = project_path + '/netlist/' + project_name + '.spi'
+        layout_path = project_path + '/layout/' + project_name + '.spice'
+        net_path = project_path + '/netlist/' + project_name + '.spice'
        comp_path = project_path + '/layout/comp.json'

        if os.path.exists(layout_path) and os.path.exists(net_path) and os.path.exists(comp_path):
@@ -599,7 +617,7 @@ class LVSManager(ttk.Frame):
            mproc.stdin.write("ext2spice cthresh infinite\n")
            mproc.stdin.write("ext2spice rthresh infinite\n")
            mproc.stdin.write("ext2spice blackbox on\n")
-            mproc.stdin.write("ext2spice -o " + self.layout + ".spi\n")
+            mproc.stdin.write("ext2spice -o " + self.layout + ".spice\n")
            mproc.stdin.write("quit -noprompt\n")
            magicout = mproc.communicate()[0]
            self.printwarn(magicout)
@@ -607,8 +625,8 @@ class LVSManager(ttk.Frame):
                print('Failure to generate new layout netlist.')
                return False

-            # Move .spi netlist to project_dir/netlist/lvs/
-            shutil.move(project_path + '/layout/' + self.layout + '.spi', layout_path)
+            # Move .spice netlist to project_dir/netlist/lvs/
+            shutil.move(project_path + '/layout/' + self.layout + '.spice', layout_path)
            # Remove extraction files
            for file in os.listdir(project_path + '/layout'):
                if os.path.splitext(file)[1] == '.ext':
@@ -625,17 +643,37 @@ class LVSManager(ttk.Frame):

        project_path = self.rootpath
        project_name = self.project
-        comp_path = project_path + '/layout/comp.json'
+
+        # Diagnostic:
+        print('project_name is ' + project_name)
+        print('project_path is ' + project_path)
+        print('self.layout is ' + self.layout)
+        print('self.schematic is ' + self.schematic)
+        print('self.lvs_setup is ' + self.lvs_setup)
+
        has_vlog = False
        vlog_path = project_path + '/verilog/' + project_name + '.v'

-        layout_path = project_path + '/netlist/lvs/' + self.layout + '.spi'
-        net_path = project_path + '/netlist/schem/' + self.schematic + '.spi'
-        layout_src = project_path + '/layout/' + self.layout + '.mag'
+        if os.path.isfile(self.layout):
+            layout_path = self.layout
+            layout_src = None
+        else:
+            layout_path = project_path + '/netlist/lvs/' + self.layout + '.spice'
+            layout_src = project_path + '/layout/' + self.layout + '.mag'
+
+        comp_dir = os.path.split(layout_path)[0]
+        comp_path = comp_dir + '/comp.json'
+
+        if os.path.isfile(self.schematic):
+            net_path = self.schematic
+        else:
+            net_path = project_path + '/netlist/schem/' + self.schematic + '.spice'

        # Does the setup file exist (this is optional)?
-        if self.lvs_setup != '' and not os.path.isfile('setup.tcl'):
+        if self.lvs_setup == '' and not os.path.isfile('setup.tcl'):
            print('No technology setup file selected.')
+        elif not os.path.isfile(self.lvs_setup):
+            print("Can't find technology setup file " + self.lvs_setup)

        # Does schematic netlist exist?
        if not os.path.isfile(vlog_path) and not os.path.isfile(net_path):
@@ -643,14 +681,16 @@ class LVSManager(ttk.Frame):
            return

        # Does LVS netlist subdirectory exist?
-        if not os.path.exists(project_path + '/netlist/lvs'):
-            os.makedirs(project_path + '/netlist/lvs')
+        if os.path.exists(project_path + '/netlist'):
+            if not os.path.exists(project_path + '/netlist/lvs'):
+                os.makedirs(project_path + '/netlist/lvs')

        # Does layout netlist exist and is it current?
-        if not self.generate_layout_netlist(layout_path, layout_src, project_path):
-            return False
+        if layout_src:
+            if not self.generate_layout_netlist(layout_path, layout_src, project_path):
+                return False

-        # Final check
+        # Final checks
        if not os.path.isfile(layout_path):
            print('Error:  No netlist generated from magic.')
            return
@@ -662,26 +702,27 @@ class LVSManager(ttk.Frame):
            with open(layout_path) as ifile:
                spitext = ifile.read()

-            # spilines = spitext.replace(',', '|')
-            # with open(layout_path, 'w') as ofile:
-            #     ofile.write(spilines)
-
        # Check the netlist to see if the cell to match is a subcircuit.  If
        # not, then assume it is the top level.

+        layoutcell = os.path.splitext(os.path.split(self.layout)[1])[0]
        is_subckt = False
+        subname = None
        subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
        dutlines = spitext.replace('\n+', ' ').splitlines()
        for line in dutlines:
            lmatch = subrex.match(line)
            if lmatch:
                subname = lmatch.group(1)
-                if subname == self.layout:
+                if subname == layoutcell:
                    is_subckt = True
                    break

        if is_subckt:
-            layout_arg = layout_path + ' ' + self.layout
+            layout_arg = self.layout + ' ' + layoutcell
+            layout_text = '"' + layout_arg + '"'
+        elif subname:
+            layout_arg = self.layout + ' ' + subname
            layout_text = '"' + layout_arg + '"'
        else:
            layout_arg = layout_path
@@ -690,8 +731,39 @@ class LVSManager(ttk.Frame):
        if has_vlog:
            schem_arg = vlog_path + ' ' + self.schematic
        else:
-            schem_arg = net_path + ' ' + self.schematic
-        schem_text = '"' + schem_arg + '"'
+            # Final checks
+            if not os.path.isfile(net_path):
+                print('Error:  No netlist from schematic.')
+                return
+
+            with open(net_path) as ifile:
+                spitext = ifile.read()
+
+            # Check the netlist to see if the cell to match is a subcircuit.  If
+            # not, then assume it is the top level.
+
+            schemcell = os.path.splitext(os.path.split(self.schematic)[1])[0]
+            subname = None
+            is_subckt = False
+            subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
+            dutlines = spitext.replace('\n+', ' ').splitlines()
+            for line in dutlines:
+                lmatch = subrex.match(line)
+                if lmatch:
+                    subname = lmatch.group(1)
+                    if subname == schemcell:
+                        is_subckt = True
+                        break
+
+            if is_subckt:
+                schem_arg = self.schematic + ' ' + schemcell
+                schem_text = '"' + schem_arg + '"'
+            elif subname:
+                schem_arg = self.schematic + ' ' + subname
+                schem_text = '"' + schem_arg + '"'
+            else:
+                schem_arg = net_path
+                schem_text = schem_arg

        # Remove any previous comparison output file
        comp_out_path = os.path.splitext(comp_path)[0] + '.out'
@@ -708,7 +780,7 @@ class LVSManager(ttk.Frame):
        self.lvsproc = subprocess.Popen(['netgen', '-batch', 'lvs',
 		layout_arg, schem_arg,
 		self.lvs_setup, comp_out_path, '-json', '-blackbox'],
-		cwd=project_path + '/layout',
+		cwd=comp_dir,
 		stdout=subprocess.PIPE, stderr=subprocess.PIPE, bufsize=0)
        # This is largely unnecessary as netgen usually runs to completion very quickly.
        self.watchclock(comp_path)
@@ -25,7 +25,7 @@ install-tcl: netgenexec${EXEEXT} $(DESTDIR)${INSTALL_BINDIR}/netgen.sh ${TCL_FIL
 netgenexec${EXEEXT}: netgenexec.c
 	${CC} ${CFLAGS} ${CPPFLAGS} ${DFLAGS_NOSTUB} netgenexec.c \
 		-o netgenexec${EXEEXT} \
-		${LDFLAGS} ${LIBS} ${LIB_SPECS_NOSTUB}
+		${LIB_SPECS_NOSTUB} ${LDFLAGS} ${LIBS} ${GR_LIBS}

 netgen.tcl: netgen.tcl.in
 	sed -e 's%TCL_DIR%${TCLDIR}%g' \
@@ -352,7 +352,7 @@ proc netgen::convert_to_json {filename lvs_final} {
   close $fjson
 }

-#----------------------------------------------------------------
+#-----------------------------------------------------------------------
 # Define the "lvs" command as a way of calling the netgen options
 # for standard compare, essentially the same as the old "netcomp"
 # standalone program.
@@ -361,14 +361,20 @@ proc netgen::convert_to_json {filename lvs_final} {
 # although if the cells have not been read in yet, then the
 # original syntax of filename or {filename cellname} is required.
 #
-# "args" is passed to verify and may therefore contain only the
-# value "-list" or nothing.  If "-list", then output is returned
-# as a nested list.
-#----------------------------------------------------------------
+# "args" may be "-list", "-json", or "-blackbox".
+#    "-list" returns output as a nested list.
+#    "-json" creates a .json-format output file in addition to stdout.
+#    "-blackbox" treats empty cells as black-box entries.
+#    "-noflatten={list}" is a list of cells not to flatten if mismatched.
+#    i.e., the cells are expected to match and any mismatch cannot be
+#    expected to be resolved by flattening the contents of the mismatched
+#    cells.
+#-----------------------------------------------------------------------

 proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
   set dolist 0
   set dojson 0
+   set noflat {}
   foreach arg $args {
      if {$arg == "-list"} {
 	 puts stdout "Generating list result"
@@ -382,6 +388,30 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
      } elseif {$arg == "-blackbox"} {
 	 puts stdout "Treating empty subcircuits as black-box cells"
 	 netgen::model blackbox on
+      } elseif {[string first "-noflatten=" $arg] == 0} {
+	 set value [string range $arg 11 end]
+	 # If argument is a filename then read the list of cells from it;
+	 # otherwise, argument is the list of files itself in quotes or
+	 # braces.
+	 if {![catch {file exists $value}]} {
+	    if {![catch {open $value r} fnf]} {
+	       while {[gets $fnf line] >= 0} {
+		  if {[lindex $line 0] != "#"} {
+		     foreach cell $line {
+		    	lappend noflat $cell
+		     }
+		  }
+	       }
+	       close $fnf
+	    } else {
+	       puts stderr "Cannot open file $value for reading cell list."
+	    }
+	 } else {
+	    set noflat [string trim $value \"\{\}]
+	 }
+	 if {[llength $noflat] > 0} {
+	    puts stdout "Will not flatten these subcells: $noflat"
+	 }
      }
   }

@@ -501,6 +531,8 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
      return
   }
   set properr {}
+   set matcherr {}
+   set pinsgood -1
   while {$endval != {}} {
      if {$dolist == 1} {
         netgen::run -list converge
@@ -528,12 +560,33 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {

 	    # Flatten the non-matching subcircuit (but not the top-level cells)
            if {[netgen::print queue] != {}} {
-	       netgen::log put "  Flattening non-matched subcircuits $endval"
-	       netgen::flatten class "[lindex $endval 0] $fnum1"
-	       netgen::flatten class "[lindex $endval 1] $fnum2"
+	       if {([lsearch $noflat [lindex $endval 0]] == -1) &&
+			([lsearch $noflat [lindex $endval 1]] == -1)} {
+	           netgen::log put "  Flattening non-matched subcircuits $endval\n"
+	           netgen::flatten class "[lindex $endval 0] $fnum1"
+	           netgen::flatten class "[lindex $endval 1] $fnum2"
+	       } else {
+	           netgen::log put "  Continuing with black-boxed subcircuits $endval\n"
+		   lappend matcherr [lindex $endval 0]"($fnum1)"
+		   lappend matcherr [lindex $endval 1]"($fnum2)"
+	           # Match pins
+                   netgen::log echo off
+	           if {$dolist == 1} {
+		       set result [equate -list -force pins "$fnum1 [lindex $endval 0]" \
+				"$fnum2 [lindex $endval 1]"]
+	           } else {
+		       set result [equate -force pins "$fnum1 [lindex $endval 0]" \
+				"$fnum2 [lindex $endval 1]"]
+	           }
+	           if {$result != 0} {
+		       equate classes "$fnum1 [lindex $endval 0]" \
+			        "$fnum2 [lindex $endval 1]"
+	           }
+	           set pinsgood $result
+                   netgen::log echo on
+	       }
 	    }
 	 } else {
-	    # Match pins
            netgen::log echo off
 	    if {$dolist == 1} {
 		set result [equate -list pins "$fnum1 [lindex $endval 0]" \
@@ -546,15 +599,42 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
 		equate classes "$fnum1 [lindex $endval 0]" \
 			 "$fnum2 [lindex $endval 1]"
 	    }
+	    # If $uresult == -1 then these are black-box entries and
+	    # $pinsgood should not be set to the resulting value.
+	    if {$uresult > 0} {
+	        set pinsgood $result
+	    }
            netgen::log echo on
 	 }
 	 if {$uresult == 2} {lappend properr [lindex $endval 0]}
      } else {
 	 # Flatten the non-matching subcircuit (but not the top-level cells)
         if {[netgen::print queue] != {}} {
-	    netgen::log put "  Flattening non-matched subcircuits $endval"
-	    netgen::flatten class "[lindex $endval 0] $fnum1"
-	    netgen::flatten class "[lindex $endval 1] $fnum2"
+	    if {([lsearch $noflat [lindex $endval 0]] == -1) &&
+		    ([lsearch $noflat [lindex $endval 1]] == -1)} {
+	       netgen::log put "  Flattening non-matched subcircuits $endval\n"
+	       netgen::flatten class "[lindex $endval 0] $fnum1"
+	       netgen::flatten class "[lindex $endval 1] $fnum2"
+	    } else {
+	       netgen::log put "  Continuing with black-boxed subcircuits $endval\n"
+	       lappend matcherr [lindex $endval 0]"($fnum1)"
+	       lappend matcherr [lindex $endval 0]"($fnum2)"
+	       # Match pins
+               netgen::log echo off
+	       if {$dolist == 1} {
+		   set result [equate -list -force pins "$fnum1 [lindex $endval 0]" \
+			    "$fnum2 [lindex $endval 1]"]
+	       } else {
+		   set result [equate -force pins "$fnum1 [lindex $endval 0]" \
+			    "$fnum2 [lindex $endval 1]"]
+	       }
+	       if {$result != 0} {
+		   equate classes "$fnum1 [lindex $endval 0]" \
+			    "$fnum2 [lindex $endval 1]"
+	       }
+	       set pinsgood $result
+               netgen::log echo on
+	    }
 	 }
      }
      netgen::log echo off
@@ -569,9 +649,17 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
   netgen::log echo off
   puts stdout "Result: " nonewline
   netgen::log echo on
-   verify only
+   if {$pinsgood == 0} {
+      # NOTE:  Need to disambiguate these two cases. . .
+      netgen::log put "Cells failed matching, or top level cell failed pin matching.\n"
+   } else {
+      verify only
+   }
   if {$properr != {}} {
-      netgen::log put "The following cells had property errors: $properr\n"
+      netgen::log put "The following cells had property errors:\n " [regsub -all { } $properr "\n "] "\n"
+   }
+   if {$matcherr != {}} {
+      netgen::log put "The following subcells failed to match:\n " [regsub -all { } $matcherr "\n "] "\n"
   }
   if {$dolog} {
      netgen::log end
@@ -32,6 +32,9 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include "print.h"
 #include "query.h"	/* for ElementNodes() */
 #include "hash.h"
+#include "xilinx.h"
+#include "tech.h"
+#include "flatten.h"

 #ifndef TRUE
 #define TRUE 1
@@ -94,6 +97,7 @@ int _netcmp_ignore(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_permute(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_property(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_exhaustive(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
+int _netcmp_symmetry(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_restart(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_global(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_convert(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
@@ -244,6 +248,8 @@ Command netcmp_cmds[] = {
 	{"exhaustive",		_netcmp_exhaustive,
 		"\n   "
 		"toggle exhaustive subdivision"},
+	{"symmetry",		_netcmp_symmetry,
+		"(deprecated)"},
 	{"restart",		_netcmp_restart,
 		"\n   "
 		"start over (reset data structures)"},
@@ -973,7 +979,7 @@ _netgen_writenet(ClientData clientData,
         SpiceCell(repstr, filenum, "");
         break;
      case VERILOG_IDX:
-         VerilogModule(repstr, filenum, "");
+         VerilogTop(repstr, filenum, "");
         break;
      case WOMBAT_IDX:
         Wombat(repstr,NULL);
@@ -1532,23 +1538,24 @@ int
 _netgen_model(ClientData clientData,
    Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
 {
-   struct nlist *tp;
+   struct nlist *tp, *tp2;
   char *model, *retclass;
   unsigned char class;
   int fnum = -1;
-   int result, index, nports;
+   int result, index, nports, nports2;

   char *modelclasses[] = {
      "undefined", "nmos", "pmos", "pnp", "npn",
      "resistor", "capacitor", "diode",
      "inductor", "module", "blackbox", "xline",
-      "moscap", "mosfet", "bjt", "subcircuit", NULL
+      "moscap", "mosfet", "bjt", "subcircuit", "copy",
+      NULL
   };
   enum OptionIdx {
      UNDEF_IDX,  NMOS_IDX, PMOS_IDX, PNP_IDX, NPN_IDX,
      RES_IDX, CAP_IDX, DIODE_IDX, INDUCT_IDX,
      MODULE_IDX, BLACKBOX_IDX, XLINE_IDX, MOSCAP_IDX,
-      MOSFET_IDX, BJT_IDX, SUBCKT_IDX
+      MOSFET_IDX, BJT_IDX, SUBCKT_IDX, COPY_IDX
   };

   if (objc != 3 && objc != 2) {
@@ -1580,7 +1587,7 @@ _netgen_model(ClientData clientData,

   if (objc == 3) {
      model = Tcl_GetString(objv[2]);
-      nports = NumberOfPorts(model);
+      nports = NumberOfPorts(model, fnum);

      if (Tcl_GetIndexFromObj(interp, objv[2], (CONST84 char **)modelclasses,
 		"class", 0, &index) != TCL_OK) {
@@ -1644,6 +1651,40 @@ _netgen_model(ClientData clientData,
 	    break;
 	 case SUBCKT_IDX:
 	    class = CLASS_SUBCKT;
+	    break;
+	 case COPY_IDX:
+	    /* "copy" is not a class, but indicates that the cell,  */
+	    /* if undefined or a module, should have its class	    */
+	    /* taken from the other circuit, if that circuit has a  */
+	    /* cell of the same name.				    */
+	    if (Circuit1 == NULL || Circuit2 == NULL) {
+		Tcl_SetResult(interp, "Circuits have not been queued for comparison.",
+			NULL);
+		return TCL_ERROR;
+	    }
+	    if (tp == Circuit1) {
+		tp2 = LookupCellFile(tp->name, Circuit2->file);
+		nports2 = NumberOfPorts(tp2->name, Circuit2->file);
+	    }
+	    else if (tp == Circuit2) {
+		tp2 = LookupCellFile(tp->name, Circuit1->file);
+		nports2 = NumberOfPorts(tp2->name, Circuit1->file);
+	    }
+	    else {
+		Tcl_SetResult(interp, "The referenced netlist is not being compared.",
+			NULL);
+		return TCL_ERROR;
+	    }
+	    /* Should a non-matching number of ports be considered a fatal error? */
+	    // if (nports2 != nports) {
+	    //	Tcl_SetResult(interp, "The number of ports for this cell does not "
+	    //		"match between netlists.", NULL);
+	    //	return TCL_ERROR;
+	    // }
+
+	    class = tp2->class;
+	    /* To do (maybe): Rename tp ports to match tp2? */
+
 	    break;
      }
      tp->class = class;
@@ -2028,6 +2069,7 @@ _netcmp_format(ClientData clientData,
 	Tcl_WrongNumArgs(interp, 1, objv, "[col1_width [col2_width]]");
 	return TCL_ERROR;
    }
+    return TCL_OK;
 }

 /*------------------------------------------------------*/
@@ -2053,8 +2095,9 @@ _netcmp_compare(ClientData clientData,
   int dohierarchy = FALSE;
   int assignonly = FALSE;
   int argstart = 1, qresult, llen, result;
+   int hascontents1, hascontents2;
   struct Correspond *nextcomp;
-   struct nlist *tp;
+   struct nlist *tp1 = NULL, *tp2 = NULL;
   Tcl_Obj *flist = NULL;

   if (objc > 1) {
@@ -2097,24 +2140,24 @@ _netcmp_compare(ClientData clientData,
      }
      else if ((objc - argstart) == 2) {

-	 result = CommonParseCell(interp, objv[argstart], &tp, &fnum1);
+	 result = CommonParseCell(interp, objv[argstart], &tp1, &fnum1);
         if (result != TCL_OK) return TCL_ERROR;
 	 else if (fnum1 == -1) {
 	    Tcl_SetResult(interp, "Cannot use wildcard with compare command.\n",
 			NULL);
 	    return TCL_ERROR;
 	 }
-         name1 = tp->name;
+         name1 = tp1->name;
 	 argstart++;

-	 result = CommonParseCell(interp, objv[argstart], &tp, &fnum2);
+	 result = CommonParseCell(interp, objv[argstart], &tp2, &fnum2);
         if (result != TCL_OK) return TCL_ERROR;
 	 else if (fnum2 == -1) {
 	    Tcl_SetResult(interp, "Cannot use wildcard with compare command.\n",
 			NULL);
 	    return TCL_ERROR;
 	 }
-         name2 = tp->name;
+         name2 = tp2->name;

         if (dohierarchy) {
 	    RemoveCompareQueue();
@@ -2153,11 +2196,34 @@ _netcmp_compare(ClientData clientData,
      ConvertGlobals(name2, fnum2);
   }

-   CreateTwoLists(name1, fnum1, name2, fnum2, dolist);
-   while (PrematchLists(name1, fnum1, name2, fnum2) > 0) {
-      Fprintf(stdout, "Making another compare attempt.\n");
-      CreateTwoLists(name1, fnum1, name2, fnum2, dolist);
+   tp1 = LookupCellFile(name1, fnum1);
+   tp2 = LookupCellFile(name2, fnum2);
+
+   hascontents1 = HasContents(tp1);
+   hascontents2 = HasContents(tp2);
+
+   if (hascontents1 && !hascontents2 && (tp2->flags & CELL_PLACEHOLDER)) {
+       Fprintf(stdout, "Circuit 2 cell %s is a black box; will not flatten "
+                        "Circuit 1\n", name2);
   }
+   else if (hascontents2 && !hascontents1 && (tp1->flags & CELL_PLACEHOLDER)) {
+       Fprintf(stdout, "Circuit 1 cell %s is a black box; will not flatten "
+                        "Circuit 2\n", name1);
+   }
+   else if (hascontents1 || hascontents2) {
+       FlattenUnmatched(tp1, name1, 1, 0);
+       FlattenUnmatched(tp2, name2, 1, 0);
+       DescribeContents(name1, fnum1, name2, fnum2);
+
+       while (PrematchLists(name1, fnum1, name2, fnum2) > 0) {
+          Fprintf(stdout, "Making another compare attempt.\n");
+          Printf("Flattened mismatched instances and attempting compare again.\n");
+          FlattenUnmatched(tp1, name1, 1, 0);
+          FlattenUnmatched(tp2, name2, 1, 0);
+          DescribeContents(name1, fnum1, name2, fnum2);
+       }
+   }
+   CreateTwoLists(name1, fnum1, name2, fnum2, dolist);

   // Return the names of the two cells being compared, if doing "compare
   // hierarchical".  If "-list" was specified, then append the output
@@ -2390,6 +2456,8 @@ _netcmp_run(ClientData clientData,
 	 else {
 	    enable_interrupt();
 	    while (!Iterate() && !InterruptPending);
+	    ExhaustiveSubdivision = 1;
+	    while (!Iterate() && !InterruptPending);
 	    if (dolist) {
 	       result = _netcmp_verify(clientData, interp, 2, objv - 1);
 	    }
@@ -2408,6 +2476,8 @@ _netcmp_run(ClientData clientData,
 	 else {
 	    enable_interrupt();
 	    while (!Iterate() && !InterruptPending);
+	    ExhaustiveSubdivision = 1;
+	    while (!Iterate() && !InterruptPending);
 	    automorphisms = VerifyMatching();
 	    if (automorphisms == -1)
 	       Fprintf(stdout, "Netlists do not match.\n");
@@ -2419,8 +2489,7 @@ _netcmp_run(ClientData clientData,
 	       automorphisms = ResolveAutomorphsByProperty();
 	       if (automorphisms == 0)
 	          Fprintf(stdout, "Netlists match uniquely.\n");
-	       else {
-
+	       else if (automorphisms > 0) {
 	          // Next, attempt to resolve automorphisms uniquely by
 	          // using the pin names
 		  automorphisms = ResolveAutomorphsByPin();
@@ -2428,14 +2497,17 @@ _netcmp_run(ClientData clientData,

 	       if (automorphisms == 0)
 	          Fprintf(stdout, "Netlists match uniquely.\n");
-	       else
+	       else if (automorphisms > 0) {
 	          // Anything left is truly indistinguishable
 	          Fprintf(stdout, "Netlists match with %d symmetr%s.\n",
 				automorphisms, (automorphisms == 1) ? "y" : "ies");

-	       while ((automorphisms = ResolveAutomorphisms()) > 0);
-	       if (automorphisms == -1) Fprintf(stdout, "Netlists do not match.\n");
-		  else Fprintf(stdout, "Circuits match correctly.\n");
+		  while ((automorphisms = ResolveAutomorphisms()) > 0);
+	       }
+	       if (automorphisms == -1)
+		  Fprintf(stdout, "Netlists do not match.\n");
+	       else
+		  Fprintf(stdout, "Circuits match correctly.\n");
 	    }
 	    if (PropertyErrorDetected) {
 	       Fprintf(stdout, "There were property errors.\n");
@@ -2789,11 +2861,13 @@ _netcmp_equate(ClientData clientData,
   char *name1 = NULL, *name2 = NULL, *optstart;
   struct nlist *tp1, *tp2, *SaveC1, *SaveC2;
   struct objlist *ob1, *ob2;
+   struct ElementClass *saveEclass = NULL;
+   struct NodeClass *saveNclass = NULL;
   int file1, file2;
-   int i, l1, l2, ltest, lent, dolist = 0;
+   int i, l1, l2, ltest, lent, dolist = 0, doforce = 0;
   Tcl_Obj *tobj1, *tobj2, *tobj3;

-   if (objc > 1) {
+   while (objc > 1) {
      optstart = Tcl_GetString(objv[1]);
      if (*optstart == '-') optstart++;
      if (!strcmp(optstart, "list")) {
@@ -2801,6 +2875,13 @@ _netcmp_equate(ClientData clientData,
 	 objv++;
 	 objc--;
      }
+      else if (!strcmp(optstart, "force")) {
+	 doforce = 1;
+	 objv++;
+	 objc--;
+      }
+      else
+	 break;
   }

   if ((objc != 2) && (objc != 4) && (objc != 6)) {
@@ -2958,16 +3039,41 @@ _netcmp_equate(ClientData clientData,
 	 break;

      case PINS_IDX:
-	 if ((ElementClasses == NULL) && (auto_blackbox == FALSE)) {
-	    if (CurrentCell == NULL)
-		Fprintf(stderr, "Equate elements:  no current cell.\n");
-	    Fprintf(stderr, "Equate pins:  cell %s and/or %s has no elements.\n",
-			name1, name2);
-	    Tcl_SetObjResult(interp, Tcl_NewBooleanObj(0));
-	    return TCL_OK;
+	 if ((ElementClasses != NULL) && (doforce == TRUE)) {
+	    saveEclass = ElementClasses;
+	    saveNclass = NodeClasses;
+	    ElementClasses = NULL;
+	    NodeClasses = NULL;
 	 }
-	 else if (ElementClasses == NULL) {
-	    /* This has been called outside of a netlist compare,	*/
+	 if ((ElementClasses == NULL) && (auto_blackbox == FALSE)) {
+	    if (CurrentCell == NULL) {
+		Fprintf(stderr, "Equate elements:  no current cell.\n");
+		Tcl_SetObjResult(interp, Tcl_NewBooleanObj(0));
+		return TCL_OK;
+	    }
+	    else if ((tp1->flags & CELL_PLACEHOLDER) ||
+			(tp2->flags & CELL_PLACEHOLDER)) {
+		if (tp1->flags & CELL_PLACEHOLDER) {
+		    Fprintf(stdout, "Warning: Equate pins:  cell %s "
+			"is a placeholder, treated as a black box.\n", name1);
+		}
+		if (tp2->flags & CELL_PLACEHOLDER) {
+		    Fprintf(stdout, "Warning: Equate pins:  cell %s "
+			"is a placeholder, treated as a black box.\n", name2);
+		}
+		// If a cell in either circuit is marked as a black box, then
+		// the cells in both circuits should be marked as a black box.
+		tp1->flags |= CELL_PLACEHOLDER;
+		tp2->flags |= CELL_PLACEHOLDER;
+	    }
+	    else {
+		Fprintf(stdout, "Equate pins:  cell %s and/or %s "
+			"has no elements.\n", name1, name2);
+		/* This is not necessarily an error, so go ahead and match pins. */
+	    }
+	 }
+	 if (ElementClasses == NULL) {
+	    /* This may have been called outside of a netlist compare,	*/
 	    /* probably to force name matching of pins on black-box	*/
 	    /* devices.  But MatchPins only works if tp1 == Circuit1	*/
 	    /* and tp2 == Circuit2, so preserve these values and 	*/
@@ -3001,6 +3107,12 @@ _netcmp_equate(ClientData clientData,
 	    /* Recover temporarily set global variables (see above) */
 	    Circuit1 = SaveC1;
 	    Circuit2 = SaveC2;
+
+	    /* Recover ElementClasses if forcing pins on mismatched circuits */
+	    if (doforce == TRUE) {
+	       ElementClasses = saveEclass;
+	       NodeClasses = saveNclass;
+	    }
 	 }
 	 break;

@@ -3263,10 +3375,10 @@ _netcmp_property(ClientData clientData,
    int result, index, idx2;

    char *suboptions[] = {
-	"integer", "double", "value", "string", NULL
+	"integer", "double", "value", "string", "expression", NULL
    };
    enum SubOptionIdx {
-	INTEGER_IDX, DOUBLE_IDX, VALUE_IDX, STRING_IDX
+	INTEGER_IDX, DOUBLE_IDX, VALUE_IDX, STRING_IDX, EXPRESSION_IDX
    };

    /* Note: "merge" has been deprecated, but kept for backwards compatibility.	*/
@@ -3360,9 +3472,15 @@ _netcmp_property(ClientData clientData,
 	    GlobalParallelNone = FALSE;
 	    SetParallelCombine(TRUE);
 	}
+	else if (!strcmp(Tcl_GetString(objv[2]), "connected")) {
+	    GlobalParallelOpen = FALSE;
+	}
+	else if (!strcmp(Tcl_GetString(objv[2]), "open")) {
+	    GlobalParallelOpen = TRUE;
+	}
 	else {
-	    Tcl_SetResult(interp, "Bad option, should be property parallel none|all",
-			NULL);
+	    Tcl_SetResult(interp, "Bad option, should be property parallel "
+			"none|all|connected", NULL);
 	    return TCL_ERROR;
 	}
 	return TCL_OK;
@@ -3649,6 +3767,11 @@ _netcmp_property(ClientData clientData,
 			 		PropertyString(tp->name, fnum,
 						Tcl_GetString(tobj1), ival, NULL);
 					break;
+				case EXPRESSION_IDX:
+			 		PropertyString(tp->name, fnum,
+						Tcl_GetString(tobj1), 0,
+						Tcl_GetString(tobj3));
+					break;
 			    }
 			    break;
 		    }
@@ -3918,6 +4041,23 @@ _netcmp_permute(ClientData clientData,
   return TCL_OK;
 }

+/*------------------------------------------------------*/
+/* Function name: _netcmp_symmetry			*/
+/* Syntax: netgen::symmetry [fast|full]			*/
+/* Formerly: x						*/
+/* Results:						*/
+/* Side Effects:					*/
+/* Notes:  Deprecated, retained for compatibility.	*/
+/*------------------------------------------------------*/
+
+int
+_netcmp_symmetry(ClientData clientData,
+    Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
+{
+   Printf("Symmetry breaking method has been deprecated.\n");
+   return TCL_OK;
+}
+
 /*------------------------------------------------------*/
 /* Function name: _netcmp_exhaustive			*/
 /* Syntax: netgen::exhaustive [on|off]			*/
@@ -3939,7 +4079,7 @@ _netcmp_exhaustive(ClientData clientData,
   int result, index;

   if (objc == 1)
-      index = YES_IDX;
+      index = -1;
   else {
      if (Tcl_GetIndexFromObj(interp, objv[1], (CONST84 char **)yesno,
 		"option", 0, &index) != TCL_OK)
@@ -1 +1 @@
 .5.136
 .5.215