Merge branch 'master' into netgen-1.5

marked as unneeded, so I simply removed the code rather than
debug the issue, which was that buses got the delimeters erased
for checking but never put back again.  Also:  Modified the verilog
reading code so that if an empty set "()" is given for a pin, then
the initial proxy, which is a single net with the name prefix
"_noconnect_", can be promoted to a bus if further processing
reveals it to be a bus and not a single-bit signal.

README.md

@@ -91,6 +91,49 @@ and IRSIM version 9.7:
 
 Note: For FreeBSD, use 'gmake' instead.
 
+Note: On MacOS (Big Sur) follow the following procedure. If you have installed `xschem` and `magic` already on MacOS then steps (1) and (2) can likely be skipped.
+
+**1) Build Tcl for X11**
+
+We are following the instructions from `xschem` (https://github.com/StefanSchippers/xschem/blob/master/README_MacOS.md). 
+
+* Download `Tcl` from https://prdownloads.sourceforge.net/tcl/tcl8.6.10-src.tar.gz
+
+We are using not `opt` but `opt2` so that this `Tcl` does not interfere with `tcl-tk` from HomeBrew.
+
+```
+./configure --prefix=/usr/local/opt2/tcl-tk  
+make
+make install
+```
+
+**2) Build Tk for X11**
+
+* Download `Tk` from https://prdownloads.sourceforge.net/tcl/tk8.6.10-src.tar.gz
+
+```
+./configure --prefix=/usr/local/opt2/tcl-tk \
+--with-tcl=/usr/local/opt2/tcl-tk/lib --with-x \
+--x-includes=/opt/X11/include --x-libraries=/opt/X11/lib  
+make
+make install
+```
+
+**3) Build netgen**
+
+We need to provide this custom-built `tcl-tk` and suppress compilation errors.
+
+```
+./configure --with-tcl=/usr/local/opt2/tcl-tk/lib \
+--with-tk=/usr/local/opt2/tcl-tk/lib \
+--x-includes=/opt/X11/include \
+--x-libraries=/opt/X11/lib \
+CFLAGS=-Wno-error=implicit-function-declaration
+make
+make install
+```
+
+
 IN CASE OF FAILURE
 -------------------
 Please contact me (tim@opencircuitdesign.com) to report compile-time and

VERSION

@@ -1 +1 @@
-1.5.201
+1.5.215

base/ext.c

@@ -23,12 +23,13 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include <stdio.h>
 #include <stdlib.h>	/* for strtod() */
 #include <stdarg.h>
+#include <ctype.h>
 
 #include "netgen.h"
-#include "hash.h"
 #include "objlist.h"
 #include "netfile.h"
 #include "print.h"
+#include "hash.h"
 
 void extCell(char *name, int filenum)
 {
@@ -186,7 +187,7 @@ char *ReadExt(char *fname, int doflat, int *fnum)
   /* Make sure all .ext file reading is case sensitive */
   matchfunc = match;
   matchintfunc = matchfile;
-  hashfunc = hash;
+  hashfunc = hashcase;
 
   if (LookupCellFile(fname, filenum) != NULL) {
     Printf("Error:  Duplicate cell name \"%s\"!\n", fname);
@@ -652,7 +653,7 @@ char *ReadSim(char *fname, int *fnum)
   /* Make sure all .sim file reading is case sensitive */
   matchfunc = match;
   matchintfunc = matchfile;
-  hashfunc = hash;
+  hashfunc = hashcase;
 
   CellDef(fname, filenum);
 

base/flatten.c

@@ -1421,6 +1421,22 @@ typedef struct ecomplist {
     ECompListPtr next;
 } ECompList;
 
+/*----------------------------------------------------------------------*/
+/* Determine if a cell contains at least one device or subcircuit	*/
+/*----------------------------------------------------------------------*/
+
+int
+HasContents(struct nlist *tc)
+{
+    struct objlist *ob;
+
+    for (ob = tc->cell; ob; ob = ob->next)
+	if (ob->type == FIRSTPIN)
+	    return TRUE;
+
+    return FALSE;
+}
+
 /*------------------------------------------------------*/
 /* Survey the contents of a cell and sort into a hash	*/
 /*------------------------------------------------------*/
@@ -1518,6 +1534,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
     struct hashdict compdict;
     ECompare *ecomp, *ncomp;
     ECompList *list0X, *listX0;
+    int hascontents1, hascontents2;
     int match, modified = 0;
 
     if (file1 == -1)
@@ -1533,6 +1550,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
     if (tc1 == NULL || tc2 == NULL) return 0;
 
     InitializeHashTable(&compdict, OBJHASHSIZE);
+    listX0 = list0X = NULL;
 
     // Gather information about instances of cell "name1"
     SurveyCell(tc1, &compdict, file1, file2, 0);
@@ -1545,7 +1563,6 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
     // in the hierarchy of each instance contain devices
     // or subcircuits that have more in the compared circuit.
 
-    listX0 = list0X = NULL;
     ecomp = (ECompare *)HashFirst(&compdict);
     while (ecomp != NULL) {
 
@@ -1582,7 +1599,8 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 			}
 		    }
 		    else {
-		       match = 0;
+		       // cell exists in one circuit but not the other, so flatten it.
+		       // match = 0;
 		       break;
 		    }
 		}
@@ -1649,7 +1667,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 	}
 
 	/* Case 2:  Cell2 class is a subcircuit, and flattening	*/
-	/* (it without regard to cell1) improves the matching.	*/
+	/* it (without regard to cell1) improves the matching.	*/
 
 	else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell2 != NULL) &&
 			(ecomp->num2 != 0) && (ecomp->cell2->class == CLASS_SUBCKT)) {
@@ -1707,7 +1725,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 	}
 	
 	/* Case 3:  Cell1 class is a subcircuit, and flattening	*/
-	/* (it without regard to cell1) improves the matching.	*/
+	/* it (without regard to cell1) improves the matching.	*/
 
 	else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell1 != NULL) &&
 			(ecomp->num1 != 0) && (ecomp->cell1->class == CLASS_SUBCKT)) {
@@ -2064,6 +2082,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 	}
     }
 
+done:
     // Free the hash table and its contents.
 
     ecomp = (ECompare *)HashFirst(&compdict);

base/flatten.h

@@ -0,0 +1,8 @@
+#ifndef _FLATTEN_H
+#define _FLATTEN_H
+
+extern int UniquePins(char *name, int filenum);
+extern void flattenCell(char *name, int file);
+extern int HasContents(struct nlist *);
+
+#endif /* _FLATTEN_H */

base/hash.c

@@ -30,8 +30,8 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #endif
 
 #include "netgen.h"
-#include "hash.h"
 #include "objlist.h"
+#include "hash.h"
 
 unsigned long (*hashfunc)(char *, int) = NULL;
 int (*matchfunc)(char *, char *) = NULL;
@@ -148,7 +148,7 @@ unsigned long hashnocase(char *s, int hashsize)
 	return (hashsize == 0) ? hashval : (hashval % hashsize);
 }
 
-unsigned long hash(char *s, int hashsize)
+unsigned long hashcase(char *s, int hashsize)
 {
 	unsigned long hashval;
 	

base/hash.h

@@ -48,7 +48,7 @@ extern void *HashFirst(struct hashdict *dict);
 extern void *HashNext(struct hashdict *dict);
 
 extern unsigned long hashnocase(char *s, int hashsize);
-extern unsigned long hash(char *s, int hashsize);
+extern unsigned long hashcase(char *s, int hashsize);
 
 extern int (*matchfunc)(char *, char *);
 /* matchintfunc() compares based on the name and the first	*/

base/netcmp.c

@@ -21,11 +21,13 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include "config.h"
 
 #include <stdio.h>
+#include <stdlib.h>  /* for rand(), abs(), etc */
 #include <setjmp.h>
 #include <signal.h>
 #include <time.h>    /* for time() as a seed for random number generator */
 #include <limits.h>
 #include <math.h>    /* for fabs() */
+#include <ctype.h>   /* for toupper() */
 
 #ifdef IBMPC
 #include <alloc.h>
@@ -45,11 +47,13 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include "netfile.h"
 #include "print.h"
 #include "dbug.h"
+#include "hash.h"
 
 #ifdef TCL_NETGEN
 int InterruptPending = 0;
 void (*oldinthandler)() = SIG_DFL;
 extern Tcl_Interp *netgeninterp;
+extern int check_interrupt();
 #endif
 
 /* define the following to debug core allocation */
@@ -889,9 +893,8 @@ struct FormattedList *FormatBadNodeFragment(struct Node *N)
          WITH THE SAME HASH NUMBER, are on this node */
       for (j = i+1; j < fanout; j++) {
 	if (pins[j] != NULL && 
-	    (*matchfunc) (model,
-		  pins[j]->subelement->element->object->model.class) &&
-	    pins[i]->subelement->pin_magic == pins[j]->subelement->pin_magic) {
+	    (*matchfunc)(model, pins[j]->subelement->element->object->model.class) &&
+	    	    pins[i]->subelement->pin_magic == pins[j]->subelement->pin_magic) {
 	      count++;
 	      nodelist->fanout--;
 	      pins[j] = NULL;
@@ -971,16 +974,36 @@ void PrintBadNodeFragment(struct Node *N)
          WITH THE SAME HASH NUMBER, are on this node */
       for (j = i+1; j < fanout; j++) {
 	if (pins[j] != NULL && 
-	    (*matchfunc)(model,
-		  pins[j]->subelement->element->object->model.class) &&
-	    pins[i]->subelement->pin_magic == pins[j]->subelement->pin_magic) {
-	      count++;
-	      pins[j] = NULL;
-	    }
+	    (*matchfunc)(model, pins[j]->subelement->element->object->model.class) &&
+	    	    pins[i]->subelement->pin_magic == pins[j]->subelement->pin_magic) {
+	   count++;
+	   /* pins[j] = NULL; */ /* Done in diagnostic output, below */
+	 }
       }
 
-      if (i != 0) Fprintf(stdout, ";");
+      if (i != 0) {
+	 /* Fprintf(stdout, ";"); */
+	 Fprintf(stdout, "\n");
+	 Ftab(stdout, 32);
+      }
       Fprintf(stdout, " %s:%s = %d", model, pinname, count);
+
+      /* Diagnostic */
+      Fprintf(stdout, "\n");
+      Ftab(stdout, 25);
+      Fprintf(stdout, ">>>  %s", pins[i]->subelement->element->object->instance);
+      for (j = i+1; j < fanout; j++) {
+	if (pins[j] != NULL && 
+	    (*matchfunc)(model, pins[j]->subelement->element->object->model.class) &&
+	    	    pins[i]->subelement->pin_magic == pins[j]->subelement->pin_magic) {
+	   /* Diagnostic */
+           Fprintf(stdout, "\n");
+           Ftab(stdout, 25);
+           Fprintf(stdout, ">>>  %s", pins[j]->subelement->element->object->instance);
+	   pins[j] = NULL;
+	}
+      }
+
       pins[i] = NULL; /* not really necessary */
     }
   Fprintf(stdout, "\n");
@@ -1363,8 +1386,8 @@ void SortUnmatchedLists(nlists1, nlists2, n1max, n2max)
 		    nlists2[n1] = temp;
 		    HashPtrInstall(nlists2[n1]->name, (void *)((long)n1 + 1), &n2hash);
 		    HashPtrInstall(nlists2[n2]->name, (void *)((long)n2 + 1), &n2hash);
-		    SortFanoutLists(nlists1[n1], nlists2[n1]);
 		}
+		SortFanoutLists(nlists1[n1], nlists2[n1]);
 	    }
 	}
 
@@ -1419,8 +1442,13 @@ void SortUnmatchedLists(nlists1, nlists2, n1max, n2max)
 		    nlists1[n2] = temp;
 		    HashPtrInstall(nlists1[n1]->name, (void *)((long)n1 + 1), &n1hash);
 		    HashPtrInstall(nlists1[n2]->name, (void *)((long)n2 + 1), &n1hash);
-		    SortFanoutLists(nlists2[n2], nlists1[n2]);
 		}
+		SortFanoutLists(nlists2[n2], nlists1[n2]);
+	    }
+	    else if ((n1max == 1) && (n2max == 1)) {
+		/* Names didn't match but there's only one entry on each side,	*/
+		/* so do a sort anyway.						*/
+		SortFanoutLists(nlists2[n2], nlists1[n2]);
 	    }
 	}
 	/* For all nets that didn't match by name, match by content */
@@ -3125,7 +3153,7 @@ int FirstElementPass(struct Element *E, int noflat, int dolist)
   ostr = CALLOC(right_col_end + 2, sizeof(char));
 
   if (Debug == 0) {
-     Fprintf(stdout, "\nSubcircuit summary:\n");
+     Fprintf(stdout, "Subcircuit summary:\n");
      *(ostr + left_col_end) =  '|';
      *(ostr + right_col_end) = '\n';
      *(ostr + right_col_end + 1) = '\0';
@@ -3639,12 +3667,19 @@ int CreateCompareQueue(char *name1, int file1, char *name2, int file2)
          Fprintf(stdout, "Descend level %d circuit 2\n", level);
       DescendCompareQueue(tc2, tc1, level, 0, 1);
 
+      /* NOTE:  Preemptive flattening is inefficient and can cause
+       * unnecessary flattening of cells that will never be compared.
+       * let the prematch stage take care of this.
+       */
+      /*--------------------------------------
       if (Debug == TRUE)
          Fprintf(stdout, "Flatten level %d circuit 1\n", level);
       FlattenUnmatched(tc1, name1, level, 0);
       if (Debug == TRUE)
          Fprintf(stdout, "Flatten level %d circuit 2\n", level);
       FlattenUnmatched(tc2, name2, level, 0);
+      ---------------------------------------*/
+
       level--;
    }
 
@@ -3723,8 +3758,23 @@ void RemoveCompareQueue()
    CompareQueue = NULL;
 }
 
+/*----------------------------------------------------------------------*/
+/* Output a summary of the contents of the two circuits being compared	*/
+/*----------------------------------------------------------------------*/
+
+void DescribeContents(char *name1, int file1, char *name2, int file2)
+{
+    Fprintf(stdout, "\n");  // blank line before new circuit diagnostics in log file
+    /* print preliminary statistics */
+    Printf("\nContents of circuit 1:  ");
+    DescribeInstance(name1, file1);
+    Printf("Contents of circuit 2:  ");
+    DescribeInstance(name2, file2);
+    Printf("\n");
+}
+
 /*----------------------------------*/
-/* create an initial data structure */
+/* Create an initial data structure */
 /*----------------------------------*/
 
 void CreateTwoLists(char *name1, int file1, char *name2, int file2, int dolist)
@@ -3736,13 +3786,6 @@ void CreateTwoLists(char *name1, int file1, char *name2, int file2, int dolist)
 
     ResetState();
 
-    /* print preliminary statistics */
-    Printf("Contents of circuit 1:  ");
-    DescribeInstance(name1, file1);
-    Printf("Contents of circuit 2:  ");
-    DescribeInstance(name2, file2);
-    Printf("\n");
-
     if (file1 == -1)
         tc1 = LookupCell(name1);
     else
@@ -3756,7 +3799,7 @@ void CreateTwoLists(char *name1, int file1, char *name2, int file2, int dolist)
     /* determine if matching will be case sensitive or case insensitive */
     matchfunc = match;
     matchintfunc = matchfile;
-    hashfunc = hash;
+    hashfunc = hashcase;
     if (tc1 != NULL && tc2 != NULL) {
         if ((tc1->flags & CELL_NOCASE) && (tc2->flags & CELL_NOCASE)) {
 	   matchfunc = matchnocase;
@@ -6892,11 +6935,6 @@ int reorderpins(struct hashlist *p, int file)
 		"Ordering will be arbitrary.\n", tc2->name);
 
     for (ob = ptr->cell; ob != NULL; ) {
-        /* Catch badness */
-	if (ob->next && (ob->next->node > 100000)) {
-	    Fprintf(stdout, "Bad.\n");
-	} 
-
 	if (ob->type == FIRSTPIN) {
 	    if ((*matchfunc)(ob->model.class, tc2->name)) {
 		char *sptr = ob->instance.name;
@@ -7907,6 +7945,7 @@ int Compare(char *cell1, char *cell2)
 {
   int automorphisms;
 
+  DescribeContents(cell1, -1, cell2, -1);
   CreateTwoLists(cell1, -1, cell2, -1, 0);
   Permute();
   while (!Iterate()); 
@@ -7967,6 +8006,7 @@ void NETCOMP(void)
     case 'c':
       promptstring("Enter cell 1: ",name);
       promptstring("Enter cell 2: ",name2);
+      DescribeContents(name, -1, name2, -1);
       CreateTwoLists(name, -1, name2, -1, 0);
 #ifdef DEBUG_ALLOC
       PrintCoreStats();

base/netcmp.h

@@ -26,6 +26,7 @@ extern void PrintCoreStats(void);
 extern void ResetState(void);
 extern void CreateTwoLists(char *name1, int file1, char *name2, int file2,
 		int dolist);
+extern void DescribeContents(char *name1, int file1, char *name2, int file2);
 extern int Iterate(void);
 extern int VerifyMatching(void);
 extern void PrintAutomorphisms(void);
@@ -46,6 +47,7 @@ extern int  CreateCompareQueue(char *, int, char *, int);
 extern int  GetCompareQueueTop(char **, int *, char **, int *);
 extern int  PeekCompareQueueTop(char **, int *, char **, int *);
 extern void RemoveCompareQueue();
+extern int FlattenUnmatched(struct nlist *, char *, int, int);
 
 extern void PrintIllegalClasses();
 extern void PrintIllegalNodeClasses();
@@ -54,6 +56,15 @@ extern void PrintIllegalElementClasses();
 extern void DumpNetwork(struct objlist *ob, int cidx);
 extern void DumpNetworkAll(char *name, int file);
 
+extern void RegroupDataStructures();
+extern void FormatIllegalElementClasses();
+extern void FormatIllegalNodeClasses();
+extern int ResolveAutomorphsByProperty();
+extern int ResolveAutomorphsByPin();
+extern void SummarizeElementClasses(struct ElementClass *EC);
+extern int remove_group_tags(struct objlist *ob);
+
+
 #ifdef TCL_NETGEN
 extern int EquivalentNode();
 extern int EquivalentElement();

base/netgen.c

@@ -3441,7 +3441,7 @@ int CombineParallel(char *model, int file)
    }
    HashKill(&devdict);
    if (dcnt > 0) {
-      Fprintf(stdout, "Class %s:  Merged %d devices.\n", model, dcnt);
+      Fprintf(stdout, "Class %s(%d):  Merged %d parallel devices.\n", model, file, dcnt);
    }
    FREE(nodecount);
    return dcnt;
@@ -3738,6 +3738,9 @@ int CombineSeries(char *model, int file)
       }
    }
    FREE(instlist);
+   if (scnt > 0) {
+      Fprintf(stdout, "Class %s(%d):  Merged %d series devices.\n", model, file, scnt);
+   }
    return scnt;
 }
 

base/objlist.c

@@ -22,6 +22,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 #include <stdio.h>
 #include <ctype.h>
+#include <limits.h>
 #ifdef IBMPC
 #include <alloc.h>
 #endif
@@ -31,13 +32,13 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #endif
 
 #include "netgen.h"
-#include "hash.h"
 #include "objlist.h"
 #include "regexp.h"
 #include "dbug.h"
 #include "print.h"
 #include "netfile.h"
 #include "netcmp.h"
+#include "hash.h"
 
 #ifdef TCL_NETGEN
 extern Tcl_Interp *netgeninterp;
@@ -288,7 +289,7 @@ static struct hashdict cell_dict;
 
 void InitCellHashTable(void)
 {
-    hashfunc = hash;
+    hashfunc = hashcase;
     matchfunc = NULL;
     matchintfunc = matchfile;
     InitializeHashTable(&cell_dict, CELLHASHSIZE);

base/objlist.h

@@ -312,6 +312,19 @@ extern void GarbageCollect(void);
 extern void InitGarbageCollection(void);
 extern void AddToGarbageList(struct objlist *head);
 
+extern void DeleteProperties(struct keyvalue **topptr);
+extern void AddProperty(struct keyvalue **topptr, char *key, char *value);
+extern void AddScaledProperty(struct keyvalue **topptr, char *key, char *value, double scale);
+extern void DeleteProperties(struct keyvalue **topptr);
+extern struct objlist *LinkProperties(char *model, struct keyvalue *topptr);
+
+extern void ClassDelete(char *class, int file);
+extern void RemoveShorted(char *class, int file);
+extern void CellRehash(char *name, char *newname, int file);
+
+/* defined in netgen.c */
+extern int ConvertStringToInteger(char *string, int *ival);
+
 #ifdef HAVE_MALLINFO
 void PrintMemoryStats(void);
 #endif

base/query.c

@@ -805,11 +805,13 @@ void DescribeInstance(char *name, int file)
       /* All black-box modules and placeholders by definition have all	*/
       /* disconnected pins, so don't report those.			*/
 
-      if (!(tp->flags & CELL_PLACEHOLDER) && (tp->class != CLASS_MODULE))
-      {
-	if (disconnectednodes == 0) Fprintf(stderr, "\n");
+      if ((!(tp->flags & CELL_PLACEHOLDER)) && (tp->class != CLASS_MODULE)) {
+	// if (disconnectednodes == 0) Fprintf(stderr, "\n");
         disconnectednodes++;
-        Fprintf(stderr, "Cell %s disconnected node: %s\n", tp->name, ob->name);
+	/* Don't report on ports marked "port_match_error", which is just confusing. */
+	if (strcmp(ob->name, "port_match_error")) {
+           Fprintf(stderr, "Cell %s(%d) disconnected node: %s\n", tp->name, tp->file, ob->name);
+	}
       }
     }
   }
@@ -1033,7 +1035,7 @@ void Query(void)
       break;
     case 'v':
       promptstring("Write Verilog: circuit name: ", repstr);
-      VerilogModule(repstr, filenum, "");
+      VerilogTop(repstr, filenum, "");
       break;
     case 'E':
       promptstring("Write ESACAP: circuit name: ", repstr);

base/spice.c

@@ -26,6 +26,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #endif
 
 #include <stdlib.h>  /* for calloc(), free(), getenv() */
+#include <ctype.h>  /* for toupper(), isascii() */
 #ifndef IBMPC
 #include <sys/types.h>	/* for getpwnam() tilde expansion */
 #include <pwd.h>
@@ -40,6 +41,8 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include "objlist.h"
 #include "netfile.h"
 #include "print.h"
+#include "query.h"
+#include "objlist.h"
 
 // Global storage for parameters from .PARAM
 struct hashdict spiceparams;
@@ -937,7 +940,7 @@ skip_ends:
 	 goto baddevice;
       }
 
-      snprintf(instname, 255, "%s%s", model, inst);
+      snprintf(instname, 255, "%s:%s", model, inst);
       Cell(instname, model, collector, base, emitter);
       pobj = LinkProperties(model, kvlist);
       ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
@@ -1010,7 +1013,7 @@ skip_ends:
 	 goto baddevice;
       }
 
-      snprintf(instname, 255, "%s%s", model, inst);
+      snprintf(instname, 255, "%s:%s", model, inst);
       Cell(instname, model, drain, gate, source, bulk);
       pobj = LinkProperties(model, kvlist);
       ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
@@ -1101,7 +1104,7 @@ skip_ends:
 	   usemodel = 1;
 	}
 
-	snprintf(instname, 255, "%s%s", model, inst);
+	snprintf(instname, 255, "%s:%s", model, inst);
 	if (usemodel)
            Cell(instname, model, ctop, cbot);
 	else
@@ -1194,7 +1197,7 @@ skip_ends:
 	else
 	   strcpy(model, "r");		/* Use default resistor model */
 
-	snprintf(instname, 255, "%s%s", model, inst);
+	snprintf(instname, 255, "%s:%s", model, inst);
 	if (usemodel)
 	   Cell(instname, model, rtop, rbot);
 	else
@@ -1252,7 +1255,7 @@ skip_ends:
 	 Fprintf(stderr, "Device \"%s\" has wrong number of ports for a diode.\n");
 	 goto baddevice;
       }
-      snprintf(instname, 255, "%s%s", model, inst);
+      snprintf(instname, 255, "%s:%s", model, inst);
       Cell(instname, model, anode, cathode);
       pobj = LinkProperties(model, kvlist);
       ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
@@ -1331,7 +1334,7 @@ skip_ends:
 	else
 	   strcpy(model, "t");		/* Use default xline model */
 
-	snprintf(instname, 255, "%s%s", model, inst);
+	snprintf(instname, 255, "%s:%s", model, inst);
 
 	if (usemodel)
 	   Cell(instname, model, node1, node2, node3, node4);
@@ -1414,7 +1417,7 @@ skip_ends:
       else
 	 strcpy(model, "l");		/* Use default inductor model */
 
-      snprintf(instname, 255, "%s%s", model, inst);
+      snprintf(instname, 255, "%s:%s", model, inst);
       if (usemodel)
 	 Cell(instname, model, end_a, end_b);
       else
@@ -1726,7 +1729,7 @@ skip_ends:
       /* names.								  */
 
       if (strncmp(instancename, scan->name, strlen(scan->name))) {
-         snprintf(subcktname, 99, "%s%s", scan->name, instancename);
+         snprintf(subcktname, 99, "%s:%s", scan->name, instancename);
          strcpy(instancename, subcktname);
       }
       else {

base/tech.h

@@ -0,0 +1,8 @@
+#ifndef _TECH_H
+#define _TECH_H
+
+extern int ActelLibPresent(void);
+extern void ActelLib(void);
+extern void VerilogTop(char *name, int fnum, char *filename);
+
+#endif /* _TECH_H */

base/verilog.c

@@ -52,10 +52,10 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #endif
 
 #include "netgen.h"
-#include "hash.h"
 #include "objlist.h"
 #include "netfile.h"
 #include "print.h"
+#include "hash.h"
 
 // See netfile.c for explanation of delimiters.  'X'
 // separates single-character delimiters from two-character delimiters.
@@ -1778,54 +1778,6 @@ nextinst:
 	    scan->width = width;
 
 	    result = GetBus(scan->net, &wb);
-	    if (result == -1) {
-		/* CHECK:  THIS CODE SHOULD BE DELETED, IT IS NOT THE ISSUE */
-		/* Not bus notation, but check if signal was defined as a bus */
-		wb.start = wb.end = -1;
-		minnet = maxnet = -1;
-
-		/* Pins should be in index order start->end.  Other nodes */
-		/* should be in order start->end by node number.	  */
-
-		for (bobj = CurrentCell->cell; bobj; bobj = bobj->next) {
-		    if (bobj->type == PORT) {
-			if ((bptr = strvchr(bobj->name, '[')) != NULL) {
-			    *bptr = '\0';
-			    if (!strcmp(bobj->name, scan->net)) {
-				*bptr = '[';
-				if (wb.start == -1)
-				    sscanf(bptr + 1, "%d", &wb.start);
-				else
-				    sscanf(bptr + 1, "%d", &wb.end);
-			    }
-			}
-		    }
-		    else if (bobj->type == NODE) {
-			if ((bptr = strvchr(bobj->name, '[')) != NULL) {
-			    *bptr = '\0';
-			    if (!strcmp(bobj->name, scan->net)) {
-				if (sscanf(bptr + 1, "%d", &testidx) == 1) {
-				    if (minnet == -1) {
-					minnet = maxnet = bobj->node;
-					wb.start = wb.end = testidx;
-				    }
-				    else if (bobj->node < minnet) {
-					minnet = bobj->node;
-					wb.start = testidx;
-				    }
-				    else if (bobj->node > maxnet) {
-					maxnet = bobj->node;
-					wb.end = testidx;
-				    }
-				}
-			    }
-			    *bptr = '[';
-			}
-		    }
-		}
-		if (wb.start != -1) result = 0;
-	    }
-
 	    if (result == 0) {
 	       int match = 0;
 	       int wblen, arraylen;
@@ -1935,7 +1887,25 @@ nextinst:
 	       }
 	    }
 	    else if (portstart != portend) {
-	       Fprintf(stderr, "Error:  Single net %s is connected to bus port %s\n",
+	       /* If the name starts with "_noconnect_", then it was an
+		* auto-generated name that incorrectly assumed a single-bit
+		* wide signal because it did not have a module prototype.
+		* Rewrite the noconnect name as an array.  This just means
+		* that the verilog had an empty list "()" and the initial
+		* assumption was wrong.  If not all instances agree on the
+		* size, then this will eventually generate an error.
+		*/
+	       if (!strncmp(scan->net, "_noconnect_", 11) &&
+			(strchr(scan->net, '\[') == NULL) && (width > 1)) {
+		  char *savenet = scan->net;
+		  char *newnet = MALLOC(strlen(scan->net) + 12);
+		  sprintf(newnet, "%s[%d:0]", scan->net, scan->width - 1);
+		  FREE(savenet);
+		  scan->net = newnet;
+		  continue;	/* Re-process this entry */
+	       }
+	       else
+	          Fprintf(stderr, "Error:  Single net %s is connected to bus port %s\n",
 			scan->net, scan->name);
 	    }
 	 }
@@ -2117,7 +2087,7 @@ nextinst:
 					sobj = sobj->next) {
 			      if (sobj->type == FIRSTPIN) {
 				 if (match(sobj->model.class, obptr->model.class)) {
-				    while (sobj->next->type > FIRSTPIN)
+				    while (sobj->next && (sobj->next->type > FIRSTPIN))
 				       sobj = sobj->next;
 				    /* Stop when reaching the current instance */
 				    if (sobj->type == obptr->type + 1) break;
@@ -2239,7 +2209,7 @@ char *ReadVerilogTop(char *fname, int *fnum, int blackbox)
   else {
      matchfunc = match;
      matchintfunc = matchfile;
-     hashfunc = hash;
+     hashfunc = hashcase;
   }
 
   InitializeHashTable(&verilogparams, OBJHASHSIZE);

base/xilinx.c

@@ -23,6 +23,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include <stdio.h>
 #include <stdarg.h>
 #include <ctype.h>
+#include <time.h>
 
 #ifdef IBMPC
 #include <stdlib.h>  /* for strtol on PC */
@@ -33,6 +34,8 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include "netfile.h"
 #include "hash.h"
 #include "print.h"
+#include "xilinx.h"
+#include "flatten.h"
 
 #define XILINXHASHSIZE 99
 static long xilinxhashbase = 0xA00;
@@ -132,10 +135,8 @@ char *xilinx_class(model)
 	}
 	return(model);
 }
-void
-Xilinx(cellname, filename)
-	char *cellname;
-	char *filename;
+
+void Xilinx(char *cellname, char *filename)
 {
 	char Path[500];
 	char FileName[500];
@@ -163,8 +164,7 @@ Xilinx(cellname, filename)
 	CloseFile(FileName);
 }
 
-xilinxCell(cell)
-	char *cell;
+int xilinxCell(char *cell)
 {
 	struct nlist *nl;
 	struct objlist *ob;
@@ -252,9 +252,7 @@ struct objlist *xilinx_gate(ob,nl)
 	return(nob);
 }
 
-xilinx_sym(nl,gob)
-	struct nlist *nl;
-	struct objlist *gob;
+void xilinx_sym(struct nlist *nl, struct objlist *gob)
 {
 	struct objlist *ob;
 	char *cp,*rindex();

base/xilinx.h

@@ -0,0 +1,10 @@
+#ifndef _XILINX_H
+#define _XILINX_H
+
+extern void xilinx_sym(struct nlist *nl, struct objlist *gob);
+extern void Xilinx(char *cellname, char *filename);
+extern int xilinxCell(char *cell);
+extern int XilinxLibPresent(void);
+extern void XilinxLib(void);
+
+#endif /* _XILINX_H */

python/lvs_manager.py

@@ -0,0 +1,891 @@
+#!/bin/env python3
+#
+#--------------------------------------------------------
+# LVS Manager GUI.
+#
+# This is a Python tkinter script that handles the
+# process of running LVS and interpreting results.
+#
+#--------------------------------------------------------
+# Written by Tim Edwards
+# efabless, inc.
+# Version 1.  November 30, 2016
+# Version 2.  March 6, 2017.  Reads JSON format output
+# Version 3.  April 25, 2018. Handles layout vs. verilog
+#--------------------------------------------------------
+
+import io
+import os
+import re
+import sys
+import json
+import shutil
+import signal
+import socket
+import select
+import datetime
+import contextlib
+import subprocess
+
+import tkinter
+from tkinter import ttk
+from tkinter import filedialog
+
+import tksimpledialog
+import tooltip
+from consoletext import ConsoleText
+from helpwindow import HelpWindow
+from treeviewsplit import TreeViewSplit
+
+# User preferences file (if it exists)
+prefsfile = '~/.profile/prefs.json'
+
+netgen_script_dir = '/usr/local/lib/netgen/python'
+
+#------------------------------------------------------
+# Simple dialog for confirming quit
+#------------------------------------------------------
+
+class ConfirmDialog(tksimpledialog.Dialog):
+    def body(self, master, warning, seed):
+        if warning:
+            ttk.Label(master, text=warning, wraplength=500).grid(row = 0, columnspan = 2, sticky = 'wns')
+        return self
+
+    def apply(self):
+        return 'okay'
+
+#------------------------------------------------------
+# Main class for this application
+#------------------------------------------------------
+
+class LVSManager(ttk.Frame):
+    """LVS Manager GUI."""
+
+    def __init__(self, parent, *args, **kwargs):
+        ttk.Frame.__init__(self, parent, *args, **kwargs)
+        self.root = parent
+        self.init_gui()
+        parent.protocol("WM_DELETE_WINDOW", self.on_quit)
+
+    def on_quit(self):
+        """Exits program."""
+        if self.msock:
+            self.msock.close()
+        quit()
+
+    def init_gui(self):
+        """Builds GUI."""
+        global prefsfile
+
+        message = []
+        fontsize = 11
+
+        # Read user preferences file, get default font size from it.
+        prefspath = os.path.expanduser(prefsfile)
+        if os.path.exists(prefspath):
+            with open(prefspath, 'r') as f:
+                self.prefs = json.load(f)
+            if 'fontsize' in self.prefs:
+                fontsize = self.prefs['fontsize']
+        else:
+            self.prefs = {}
+
+        s = ttk.Style()
+
+        available_themes = s.theme_names()
+        s.theme_use(available_themes[0])
+
+        s.configure('bg.TFrame', background='gray40')
+        s.configure('italic.TLabel', font=('Helvetica', fontsize, 'italic'))
+        s.configure('title.TLabel', font=('Helvetica', fontsize, 'bold italic'),
+                        foreground = 'brown', anchor = 'center')
+        s.configure('normal.TLabel', font=('Helvetica', fontsize))
+        s.configure('red.TLabel', font=('Helvetica', fontsize), foreground = 'red')
+        s.configure('green.TLabel', font=('Helvetica', fontsize), foreground = 'green3')
+        s.configure('blue.TLabel', font=('Helvetica', fontsize), foreground = 'blue')
+        s.configure('normal.TButton', font=('Helvetica', fontsize),
+                        border = 3, relief = 'raised')
+        s.configure('red.TButton', font=('Helvetica', fontsize), foreground = 'red',
+                        border = 3, relief = 'raised')
+        s.configure('green.TButton', font=('Helvetica', fontsize), foreground = 'green3',
+                        border = 3, relief = 'raised')
+        s.configure('blue.TButton', font=('Helvetica', fontsize), foreground = 'blue',
+                        border = 3, relief = 'raised')
+        s.configure('redtitle.TButton', font=('Helvetica', fontsize, 'bold italic'),
+                        foreground = 'red', border = 3, relief = 'raised')
+        s.configure('bluetitle.TButton', font=('Helvetica', fontsize, 'bold italic'),
+                        foreground = 'blue', border = 3, relief = 'raised')
+
+        # These values to be overridden from arguments
+        self.rootpath = None
+        self.project = None
+        self.logfile = None
+        self.msock = None
+        self.help = None
+
+        # Create the help window
+        if os.path.exists(netgen_script_dir + '/netgen_help.txt'):
+            self.help = HelpWindow(self, fontsize = fontsize)
+            with io.StringIO() as buf, contextlib.redirect_stdout(buf):
+                self.help.add_pages_from_file('lvs_help.txt')
+                message = buf.getvalue()
+
+            # Set the help display to the first page
+            self.help.page(0)
+
+        # Variables used by option menus and other stuff
+        self.project = "(no selection)"
+        self.layout = "(default)"
+        self.schematic = "(default)"
+        self.tech = "(none)"
+        self.lvs_setup = ''
+        self.lvsdata = {}
+
+        # Root window title
+        self.root.title('LVS Manager')
+        self.root.option_add('*tearOff', 'FALSE')
+        self.pack(side = 'top', fill = 'both', expand = 'true')
+
+        pane = tkinter.PanedWindow(self, orient = 'vertical', sashrelief='groove', sashwidth=6)
+        pane.pack(side = 'top', fill = 'both', expand = 'true')
+        self.toppane = ttk.Frame(pane)
+        self.botpane = ttk.Frame(pane)
+
+        # Get username
+        if 'username' in self.prefs:
+            username = self.prefs['username']
+        else:
+            username = os.environ['USER']
+
+        # Label with the user
+        self.toppane.title_frame = ttk.Frame(self.toppane)
+        self.toppane.title_frame.pack(side = 'top', fill = 'x')
+
+        self.toppane.title_frame.title = ttk.Label(self.toppane.title_frame, text='User:', style = 'red.TLabel')
+        self.toppane.title_frame.user = ttk.Label(self.toppane.title_frame, text=username, style = 'blue.TLabel')
+
+        self.toppane.title_frame.title.grid(column=0, row=0, ipadx = 5)
+        self.toppane.title_frame.user.grid(column=1, row=0, ipadx = 5)
+
+        self.toppane.title2_frame = ttk.Frame(self.toppane)
+        self.toppane.title2_frame.pack(side = 'top', fill = 'x')
+        self.toppane.title2_frame.project_label = ttk.Label(self.toppane.title2_frame, text="Project:",
+                style = 'title.TLabel')
+        self.toppane.title2_frame.project_label.grid(column=0, row=0, ipadx = 5)
+
+        # New project select button
+        self.toppane.title2_frame.project_select = ttk.Button(self.toppane.title2_frame,
+                text=self.project, style='normal.TButton', command=self.choose_project)
+        self.toppane.title2_frame.project_select.grid(column=1, row=0, ipadx = 5)
+
+        tooltip.ToolTip(self.toppane.title2_frame.project_select,
+                        text = "Select new project")
+
+        # Show path to project
+        self.toppane.title2_frame.path_label = ttk.Label(self.toppane.title2_frame, text=self.project,
+                style = 'normal.TLabel')
+        self.toppane.title2_frame.path_label.grid(column=2, row=0, ipadx = 5, padx = 10)
+
+        # Show top-level layout cellname with select button.  Initial cell name is the top-level cell.
+        self.toppane.title2_frame.tech_label = ttk.Label(self.toppane.title2_frame, text="Technology setup:",
+                style = 'title.TLabel')
+
+        self.toppane.title2_frame.tech_label.grid(column=3, row=0, ipadx = 5)
+        self.toppane.title2_frame.tech_select = ttk.Button(self.toppane.title2_frame,
+                text=self.tech, style='normal.TButton', command=self.choose_tech)
+        self.toppane.title2_frame.tech_select.grid(column=4, row=0, ipadx = 3, padx = 3)
+
+        self.toppane.title2_frame.layout_label = ttk.Label(self.toppane.title2_frame, text="Layout:",
+                style = 'title.TLabel')
+        self.toppane.title2_frame.layout_label.grid(column=0, row=1, ipadx = 5)
+        self.toppane.title2_frame.layout_select = ttk.Button(self.toppane.title2_frame,
+                text=self.layout, style='normal.TButton', command=self.choose_layout)
+        self.toppane.title2_frame.layout_select.grid(column=1, row=1, ipadx = 3, padx = 3)
+
+        # Show top-level schematic cellname with select button.  Initial cell name is the top-level cell.
+        self.toppane.title2_frame.schem_label = ttk.Label(self.toppane.title2_frame, text="Schematic:",
+                style = 'title.TLabel')
+        self.toppane.title2_frame.schem_label.grid(column=3, row=1, ipadx = 5)
+        self.toppane.title2_frame.schem_select = ttk.Button(self.toppane.title2_frame,
+                text=self.schematic, style='normal.TButton', command=self.choose_netlist)
+        self.toppane.title2_frame.schem_select.grid(column=4, row=1, ipadx = 3, padx = 3)
+
+        tooltip.ToolTip(self.toppane.title2_frame.project_select,
+                        text = "Select new project")
+        tooltip.ToolTip(self.toppane.title2_frame.layout_select,
+                        text = "Select a layout subcirucit to compare")
+        tooltip.ToolTip(self.toppane.title2_frame.schem_select,
+                        text = "Select a schematic subcirucit to compare")
+
+        #---------------------------------------------
+        ttk.Separator(self.toppane, orient='horizontal').pack(side = 'top', fill = 'x')
+        #---------------------------------------------
+
+        # Create listbox of Circuit1 vs. Circuit2 results
+        height = 10
+        self.toppane.lvsreport = TreeViewSplit(self.toppane, fontsize = fontsize)
+        self.toppane.lvsreport.populate("Layout:", [], "Schematic:", [],
+			[["Run", True, self.run_lvs],
+			# ["Find", True, self.findrecord]
+			], height = height)
+        self.toppane.lvsreport.set_title("Line")
+        self.toppane.lvsreport.pack(side = 'top', fill = 'both', expand = 'true')
+
+        tooltip.ToolTip(self.toppane.lvsreport.get_button(0), text="Run LVS")
+
+        #---------------------------------------------
+        # ttk.Separator(self, orient='horizontal').grid(column=0, row=3, sticky='ew')
+        #---------------------------------------------
+
+        # Add a text window below the project name to capture output.  Redirect
+        # print statements to it.
+
+        self.botpane.console = ttk.Frame(self.botpane)
+        self.botpane.console.pack(side = 'top', fill = 'both', expand = 'true')
+
+        self.text_box = ConsoleText(self.botpane.console, wrap='word', height = 4)
+        self.text_box.pack(side='left', fill='both', expand='true')
+        console_scrollbar = ttk.Scrollbar(self.botpane.console)
+        console_scrollbar.pack(side='right', fill='y')
+        # attach console to scrollbar
+        self.text_box.config(yscrollcommand = console_scrollbar.set)
+        console_scrollbar.config(command = self.text_box.yview)
+
+        # Add button bar at the bottom of the window
+        self.botpane.bbar = ttk.Frame(self.botpane)
+        self.botpane.bbar.pack(side = 'top', fill = 'x')
+
+        # Define the "quit" button and action
+        self.botpane.bbar.quit_button = ttk.Button(self.botpane.bbar, text='Quit', command=self.on_quit,
+                style = 'normal.TButton')
+        self.botpane.bbar.quit_button.grid(column=0, row=0, padx = 5)
+
+        # Define help button
+        if self.help:
+            self.botpane.bbar.help_button = ttk.Button(self.botpane.bbar, text='Help',
+		command=self.help.open, style = 'normal.TButton')
+            self.botpane.bbar.help_button.grid(column = 2, row = 0, padx = 5)
+            tooltip.ToolTip(self.botpane.bbar.help_button, text = "Show help window")
+
+        # Add the panes once the internal geometry is known.
+        pane.add(self.toppane)
+        pane.add(self.botpane)
+        pane.paneconfig(self.toppane, stretch='first')
+
+        # Redirect stdout and stderr to the console as the last thing to do. . .
+        # Otherwise errors in the GUI get sucked into the void.
+
+        self.stdout = sys.stdout
+        self.stderr = sys.stderr
+        sys.stdout = ConsoleText.StdoutRedirector(self.text_box)
+        sys.stderr = ConsoleText.StderrRedirector(self.text_box)
+
+        if message:
+            print(message)
+
+    def logprint(self, message, doflush=False):
+        if self.logfile:
+            self.logfile.buffer.write(message.encode('utf-8'))
+            self.logfile.buffer.write('\n'.encode('utf-8'))
+            if doflush:
+                self.logfile.flush()
+
+    def printout(self, output):
+        # Generate output
+        if not output:
+            return
+
+        outlines = output.splitlines()
+        for line in outlines:
+            try:
+                print(line)
+            except TypeError:
+                line = line.decode('utf-8')
+                pritn(line)
+
+    def printwarn(self, output):
+        # Check output for warning or error
+        if not output:
+            return 0
+
+        warnrex = re.compile('.*warning', re.IGNORECASE)
+        errrex = re.compile('.*error', re.IGNORECASE)
+
+        errors = 0
+        outlines = output.splitlines()
+        for line in outlines:
+            try:
+                wmatch = warnrex.match(line)
+            except TypeError:
+                line = line.decode('utf-8')
+                wmatch = warnrex.match(line)
+            ematch = errrex.match(line)
+            if ematch:
+                errors += 1
+            if ematch or wmatch:
+                print(line)
+        return errors
+
+    def choose_tech(self):
+        try:
+            project_path = self.rootpath
+            initdirname = self.rootpath + '/tech',
+        except:
+            print('Must choose a project first.')
+            return
+        techname = filedialog.askopenfilename(multiple=False,
+			initialdir = initdirname,
+			filetypes = (("Tcl script", "*.tcl"),("All Files","*.*")),
+			title = "Choose a netgen technology setup script.")
+        if techname != '':
+            print("Selected technology setup script " + techname)
+            techbase = os.path.split(techname)[1]
+            self.tech = os.path.splitext(techbase)[0]
+            self.lvs_setup = techname
+            self.toppane.title2_frame.tech_select.config(text = self.tech)
+
+    def choose_layout(self):
+        try:
+            project_path = self.rootpath
+            initdirname = self.rootpath + '/layout',
+        except:
+            print('Must choose a project first.')
+            return
+        cellname = filedialog.askopenfilename(multiple=False,
+			initialdir = initdirname,
+			filetypes = (("Magic layout", "*.mag"),("All Files","*.*")),
+			title = "Choose a layout cell to compare.")
+        if cellname != '':
+            print("Selected compare cell " + cellname)
+            self.layout = cellname
+            cellbase = os.path.split(cellname)[1]
+            layoutname = os.path.splitext(cellbase)[0]
+            self.toppane.title2_frame.layout_select.config(text = layoutname)
+            fileext = os.path.splitext(cellbase)[1]
+            if fileext == '.mag':
+                self.toppane.title2_frame.layout_label.config(text = 'Layout:')
+            else:
+                self.toppane.title2_frame.layout_label.config(text = 'Layout netlist:')
+
+    def choose_netlist(self):
+        try:
+            project_path = self.rootpath
+            initdirname = self.rootpath + '/netlist/' + self.project + '.spice'
+        except:
+            print('Must choose a project first.')
+            return
+        cellname = filedialog.askopenfilename(multiple=False,
+			initialdir = initdirname,
+			filetypes = (("Spice netlist", "*.spice"),("Verilog netlist", "*.v"),("All Files","*.*")),
+			title = "Choose a netlist to compare.")
+        if cellname != '':
+            print("Selected compare cell " + cellname)
+            self.schematic = cellname
+            cellbase = os.path.split(cellname)[1]
+            schematic_name = os.path.splitext(cellbase)[0]
+            self.toppane.title2_frame.schem_select.config(text = schematic_name)
+            fileext = os.path.splitext(cellbase)[1]
+            if fileext == '.v':
+                self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
+            elif fileext == '.sp' or fileext == '.spice' or fileext == '.spi' or fileext == '.spc' or fileext == '.ckt':
+                self.toppane.title2_frame.schem_label.config(text = 'SPICE netlist:')
+            elif fileext == '.cdl':
+                self.toppane.title2_frame.schem_label.config(text = 'CDL netlist:')
+            else:
+                self.toppane.title2_frame.schem_label.config(text = 'Unknown netlist:')
+
+    def choose_project(self):
+        project = filedialog.askdirectory(initialdir = os.getcwd(),
+			title = "Find a project.")
+        if project != '':
+            print("Selected project " + str(project))
+            result = self.set_project(project)
+
+    def set_project(self, rootpath, project_name=None):
+
+        # Check if rootpath is valid.  For LVS, there should be subdirectories
+        # "layout/" and "netlist/" or "verilog/".
+
+        haslay = os.path.isdir(rootpath + '/layout')
+        hasvlog = os.path.isdir(rootpath + '/verilog')
+        hasnet = os.path.isdir(rootpath + '/netlist')
+        if not haslay or not (hasvlog or hasnet):
+            if not haslay:
+                print("Project path has no layout (/layout) subdirectory.")
+            if not (hasvlog or hasnet):
+                print("Project path has no verilog (/verilog), or netlist (/netlist) subdirectory.")
+            # Continue anyway;  assume that netlists will be selected manually
+
+        if self.logfile:
+            self.logfile.close()
+            self.logfile = None
+
+        if not project_name:
+            project = os.path.split(rootpath)[1]
+        else:
+            project = project_name
+
+        if self.project != project:
+
+            self.rootpath = rootpath
+            self.project = project
+
+            # Clear out old project data
+            self.toppane.lvsreport.repopulate([], [])
+
+            # Close any open logfile.
+            if self.logfile:
+                self.logfile.close()
+                self.logfile = None
+
+            # Put new log file called 'lvs.log' in the mag/ subdirectory
+            if os.path.exists(rootpath + '/layout'):
+                self.logfile = open(rootpath + '/layout/lvs.log', 'w')
+            else:
+                self.logfile = open(rootpath + '/lvs.log', 'w')
+            # Print some initial information to the logfile.
+            self.logprint('Starting new log file ' + datetime.datetime.now().strftime('%c'),
+				doflush=True)
+
+            # Update project button
+            self.toppane.title2_frame.project_select.config(text = self.project)
+            self.toppane.title2_frame.path_label.config(text = self.rootpath)
+            # Cell name is the same as project name initially
+            self.layout = self.project
+            self.schematic = self.project
+            layname = os.path.splitext(os.path.split(self.layout)[1])[0]
+            self.toppane.title2_frame.layout_select.config(text = layname)
+            schemname = os.path.splitext(os.path.split(self.schematic)[1])[0]
+            self.toppane.title2_frame.schem_select.config(text = schemname)
+
+            # Update schematic button
+            if os.path.splitext(self.schematic)[1] == '.v':
+                self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
+            else:
+                self.toppane.title2_frame.schem_label.config(text = 'Schematic netlist:')
+
+            # Update layout button
+            if os.path.splitext(self.layout)[1] == '.mag':
+                self.toppane.title2_frame.schem_label.config(text = 'Layout:')
+            else:
+                self.toppane.title2_frame.schem_label.config(text = 'Layout netlist:')
+
+            # If there is a comparison file that post-dates both netlists, load it.
+            self.check_lvs()
+        return True
+
+    def check_layout_out_of_date(self, spipath, layoutpath):
+        # Check if a netlist (spipath) is out-of-date relative to the layouts
+        # (layoutpath).  Need to read the netlist and check all of the subcells.
+        need_capture = False
+        if not os.path.isfile(spipath):
+            return True
+        if os.path.isfile(layoutpath):
+            spi_statbuf = os.stat(spipath)
+            lay_statbuf = os.stat(layoutpath)
+            if spi_statbuf.st_mtime < lay_statbuf.st_mtime:
+                # netlist exists but is out-of-date
+                need_capture = True
+            else:
+                # only found that the top-level-layout is older than the
+                # netlist.  Now need to read the netlist, find all subcircuits,
+                # and check those dates, too.
+                layoutdir = os.path.split(layoutpath)[0]
+                subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
+                with open(spipath, 'r') as ifile:
+                    duttext = ifile.read()
+ 
+                dutlines = duttext.replace('\n+', ' ').splitlines()
+                for line in dutlines:
+                    lmatch = subrex.match(line)
+                    if lmatch:
+                        subname = lmatch.group(1)
+                        sublayout = layoutdir + '/' + subname + '.mag'
+                        # subcircuits that cannot be found in the current directory are
+                        # assumed to be library components and therefore never out-of-date.
+                        if os.path.exists(sublayout):
+                            sub_statbuf = os.stat(sublayout)
+                            if spi_statbuf.st_mtime < lay_statbuf.st_mtime:
+                                # netlist exists but is out-of-date
+                                need_capture = True
+                                break
+        return need_capture
+
+    def check_schematic_out_of_date(self, spipath, schempath):
+        # Check if a netlist (spipath) is out-of-date relative to the schematics
+        # (schempath).  Need to read the netlist and check all of the subcells.
+        need_capture = False
+        if not os.path.isfile(spipath):
+            return True
+        if os.path.isfile(schempath):
+            spi_statbuf = os.stat(spipath)
+            sch_statbuf = os.stat(schempath)
+            if spi_statbuf.st_mtime < sch_statbuf.st_mtime:
+                # netlist exists but is out-of-date
+                need_capture = True
+            else:
+                # only found that the top-level-schematic is older than the
+                # netlist.  Now need to read the netlist, find all subcircuits,
+                # and check those dates, too.
+                schemdir = os.path.split(schempath)[0]
+                subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
+                with open(spipath, 'r') as ifile:
+                    duttext = ifile.read()
+ 
+                dutlines = duttext.replace('\n+', ' ').splitlines()
+                for line in dutlines:
+                    lmatch = subrex.match(line)
+                    if lmatch:
+                        subname = lmatch.group(1)
+                        # NOTE: Electric uses library:cell internally to track libraries,
+                        # and maps the ":" to "__" in the netlist.  Not entirely certain that
+                        # the double-underscore uniquely identifies the library:cell. . .
+                        librex = re.compile('(.*)__(.*)', re.IGNORECASE)
+                        lmatch = librex.match(subname)
+                        if lmatch:
+                            elecpath = os.path.split(os.path.split(schempath)[0])[0]
+                            libname = lmatch.group(1)
+                            subschem = elecpath + '/' + libname + '.delib/' + lmatch.group(2) + '.sch'
+                        else:
+                            libname = {}
+                            subschem = schemdir + '/' + subname + '.sch'
+                        # subcircuits that cannot be found in the current directory are
+                        # assumed to be library components and therefore never out-of-date.
+                        if os.path.exists(subschem):
+                            sub_statbuf = os.stat(subschem)
+                            if spi_statbuf.st_mtime < sub_statbuf.st_mtime:
+                                # netlist exists but is out-of-date
+                                need_capture = True
+                                break
+                        # mapping of characters to what's allowed in SPICE makes finding
+                        # the associated schematic file a bit difficult.  Requires wild-card
+                        # searching.
+                        elif libname:
+                            restr = lmatch.group(2) + '.sch'
+                            restr = restr.replace('.', '\.')
+                            restr = restr.replace('_', '.')
+                            schrex = re.compile(restr, re.IGNORECASE)
+                            libpath = elecpath + '/' + libname + '.delib'
+                            if os.path.exists(libpath):
+                                liblist = os.listdir(libpath)
+                                for file in liblist:
+                                    lmatch = schrex.match(file)
+                                    if lmatch:
+                                        subschem = libpath + '/' + file
+                                        sub_statbuf = os.stat(subschem)
+                                        if spi_statbuf.st_mtime < sch_statbuf.st_mtime:
+                                            # netlist exists but is out-of-date
+                                            need_capture = True
+                                        break
+        return need_capture
+
+    def check_lvs(self):
+        # If both netlists exist, and comp.json is more recent than both, then
+        # load LVS results from comp.json
+        project_path = self.rootpath
+        project_name = self.project
+        layout_path = project_path + '/layout/' + project_name + '.spice'
+        net_path = project_path + '/netlist/' + project_name + '.spice'
+        comp_path = project_path + '/layout/comp.json'
+
+        if os.path.exists(layout_path) and os.path.exists(net_path) and os.path.exists(comp_path):
+            magtime = os.stat(layout_path).st_mtime
+            schemtime = os.stat(net_path).st_mtime
+            comptime = os.stat(comp_path).st_mtime
+            if comptime > magtime and comptime > schemtime:
+                print("Loading LVS results from file.")
+                self.generate(comp_path)
+
+    def generate_layout_netlist(self, layout_path, layout_src, project_path):
+        # Does layout netlist exist and is it current?
+        if self.check_layout_out_of_date(layout_path, layout_src):
+            print('Generating layout netlist.')
+            self.update_idletasks()
+            mproc = subprocess.Popen(['magic', '-dnull', '-noconsole',
+			self.layout], stdin = subprocess.PIPE, stdout = subprocess.PIPE,
+			stderr = subprocess.PIPE, cwd = project_path + '/layout',
+			universal_newlines = True)
+            mproc.stdin.write("select top cell\n")
+            mproc.stdin.write("expand\n")
+            mproc.stdin.write("extract all\n")
+            mproc.stdin.write("ext2spice hierarchy on\n")
+            mproc.stdin.write("ext2spice format ngspice\n")
+            mproc.stdin.write("ext2spice scale off\n")
+            mproc.stdin.write("ext2spice renumber off\n")
+            mproc.stdin.write("ext2spice subcircuit top auto\n")
+            mproc.stdin.write("ext2spice cthresh infinite\n")
+            mproc.stdin.write("ext2spice rthresh infinite\n")
+            mproc.stdin.write("ext2spice blackbox on\n")
+            mproc.stdin.write("ext2spice -o " + self.layout + ".spice\n")
+            mproc.stdin.write("quit -noprompt\n")
+            magicout = mproc.communicate()[0]
+            self.printwarn(magicout)
+            if mproc.returncode != 0:
+                print('Failure to generate new layout netlist.')
+                return False
+
+            # Move .spice netlist to project_dir/netlist/lvs/
+            shutil.move(project_path + '/layout/' + self.layout + '.spice', layout_path)
+            # Remove extraction files
+            for file in os.listdir(project_path + '/layout'):
+                if os.path.splitext(file)[1] == '.ext':
+                    os.remove(project_path + '/layout/' + file)
+        else:
+            print('Layout netlist is up-to-date, not regenerating.')
+        return True
+
+    def run_lvs(self, value):
+        # "value" is ignored (?)
+
+        # Check if netlists exist and are current;  otherwise create them.
+        # Then run LVS.
+
+        project_path = self.rootpath
+        project_name = self.project
+
+        # Diagnostic:
+        print('project_name is ' + project_name)
+        print('project_path is ' + project_path)
+        print('self.layout is ' + self.layout)
+        print('self.schematic is ' + self.schematic)
+        print('self.lvs_setup is ' + self.lvs_setup)
+
+        has_vlog = False
+        vlog_path = project_path + '/verilog/' + project_name + '.v'
+
+        if os.path.isfile(self.layout):
+            layout_path = self.layout
+            layout_src = None
+        else:
+            layout_path = project_path + '/netlist/lvs/' + self.layout + '.spice'
+            layout_src = project_path + '/layout/' + self.layout + '.mag'
+
+        comp_dir = os.path.split(layout_path)[0]
+        comp_path = comp_dir + '/comp.json'
+
+        if os.path.isfile(self.schematic):
+            net_path = self.schematic
+        else:
+            net_path = project_path + '/netlist/schem/' + self.schematic + '.spice'
+
+        # Does the setup file exist (this is optional)?
+        if self.lvs_setup == '' and not os.path.isfile('setup.tcl'):
+            print('No technology setup file selected.')
+        elif not os.path.isfile(self.lvs_setup):
+            print("Can't find technology setup file " + self.lvs_setup)
+
+        # Does schematic netlist exist?
+        if not os.path.isfile(vlog_path) and not os.path.isfile(net_path):
+            print('Error:  No schematic netlist or verilog netlist.')
+            return
+
+        # Does LVS netlist subdirectory exist?
+        if os.path.exists(project_path + '/netlist'):
+            if not os.path.exists(project_path + '/netlist/lvs'):
+                os.makedirs(project_path + '/netlist/lvs')
+
+        # Does layout netlist exist and is it current?
+        if layout_src:
+            if not self.generate_layout_netlist(layout_path, layout_src, project_path):
+                return False
+
+        # Final checks
+        if not os.path.isfile(layout_path):
+            print('Error:  No netlist generated from magic.')
+            return
+
+        else:
+            # Read in netlist and convert commas from [X,Y] arrays to vertical bars
+            # as something that can be converted back as necessary.  ngspice treats
+            # commas as special characters for some reason.
+            with open(layout_path) as ifile:
+                spitext = ifile.read()
+
+        # Check the netlist to see if the cell to match is a subcircuit.  If
+        # not, then assume it is the top level.
+
+        layoutcell = os.path.splitext(os.path.split(self.layout)[1])[0]
+        is_subckt = False
+        subname = None
+        subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
+        dutlines = spitext.replace('\n+', ' ').splitlines()
+        for line in dutlines:
+            lmatch = subrex.match(line)
+            if lmatch:
+                subname = lmatch.group(1)
+                if subname == layoutcell:
+                    is_subckt = True
+                    break
+
+        if is_subckt:
+            layout_arg = self.layout + ' ' + layoutcell
+            layout_text = '"' + layout_arg + '"'
+        elif subname:
+            layout_arg = self.layout + ' ' + subname
+            layout_text = '"' + layout_arg + '"'
+        else:
+            layout_arg = layout_path
+            layout_text = layout_arg
+
+        if has_vlog:
+            schem_arg = vlog_path + ' ' + self.schematic
+        else:
+            # Final checks
+            if not os.path.isfile(net_path):
+                print('Error:  No netlist from schematic.')
+                return
+
+            with open(net_path) as ifile:
+                spitext = ifile.read()
+
+            # Check the netlist to see if the cell to match is a subcircuit.  If
+            # not, then assume it is the top level.
+
+            schemcell = os.path.splitext(os.path.split(self.schematic)[1])[0]
+            subname = None
+            is_subckt = False
+            subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
+            dutlines = spitext.replace('\n+', ' ').splitlines()
+            for line in dutlines:
+                lmatch = subrex.match(line)
+                if lmatch:
+                    subname = lmatch.group(1)
+                    if subname == schemcell:
+                        is_subckt = True
+                        break
+
+            if is_subckt:
+                schem_arg = self.schematic + ' ' + schemcell
+                schem_text = '"' + schem_arg + '"'
+            elif subname:
+                schem_arg = self.schematic + ' ' + subname
+                schem_text = '"' + schem_arg + '"'
+            else:
+                schem_arg = net_path
+                schem_text = schem_arg
+
+        # Remove any previous comparison output file
+        comp_out_path = os.path.splitext(comp_path)[0] + '.out'
+        if os.path.exists(comp_out_path):
+            os.remove(comp_out_path)
+
+        # Run netgen as subprocess
+        print('Running: netgen -batch lvs ' + layout_text + 
+		' ' + schem_text + ' ' + self.lvs_setup + ' ' + comp_out_path +
+		' -json -blackbox')
+        # Note: Because arguments to subprocess are list items, the {filename cell}
+        # pair does *not* have to be quoted or braced.  Doing so causes a parse
+        # error.
+        self.lvsproc = subprocess.Popen(['netgen', '-batch', 'lvs',
+		layout_arg, schem_arg,
+		self.lvs_setup, comp_out_path, '-json', '-blackbox'],
+		cwd=comp_dir,
+		stdout=subprocess.PIPE, stderr=subprocess.PIPE, bufsize=0)
+        # This is largely unnecessary as netgen usually runs to completion very quickly.
+        self.watchclock(comp_path)
+
+    def watchclock(self, filename):
+        if self.lvsproc == None:
+            return
+
+        lvs_status = self.lvsproc.poll()
+        sresult = select.select([self.lvsproc.stdout, self.lvsproc.stderr], [], [], 0)[0]
+        if self.lvsproc.stdout in sresult:
+            outstring = self.lvsproc.stdout.readline().decode().strip()
+            self.logprint(outstring, doflush=True)
+            print(outstring)
+        elif self.lvsproc.stderr in sresult:
+            errstring = self.lvsproc.stderr.readline().decode().strip()
+            self.logprint(errstring, doflush = True)
+            print(errstring, file=sys.stderr)
+
+        if lvs_status != None:
+            print("netgen LVS exited with status " + str(lvs_status))
+            self.lvsproc = None
+            if lvs_status != 0:
+                print('Errors encountered in LVS.')
+                self.logprint('Errors in LVS, lvs status = ' + str(lvs_status), doflush=True)
+            # Done;  now read comp.json and fill the treeview listbox.
+            self.generate(filename)
+        else:
+            self.after(500, lambda: self.watchclock(filename))
+
+    # Generate display from "comp.out" file (json file now preferred)
+
+    def generate_orig(self, lvspath):
+        lefttext = []
+        righttext = []
+        print("Reading LVS output file " + lvspath)
+        if os.path.exists(lvspath):
+            with open(lvspath, 'r') as ifile:
+                lvslines = ifile.read().splitlines()
+            for line in lvslines:
+                if '|' in line:
+                    # parts = line.split('|')
+                    # lefttext.append(parts[0])
+                    # righttext.append(parts[1])
+                    lefttext.append(line[0:42].strip())
+                    righttext.append(line[44:].strip())
+                else:
+                    lefttext.append(line)
+                    righttext.append('')
+            # Populate treeview with text
+            self.toppane.lvsreport.repopulate(lefttext, righttext)
+ 
+        else:
+            print("Error:  No output file generated from LVS.")
+
+    # Generate output from LVS report JSON file comp.json
+
+    def generate(self, lvspath):
+        lefttext = []
+        righttext = []
+        print("Reading LVS output file " + lvspath)
+        if os.path.exists(lvspath):
+            with open(lvspath, 'r') as ifile:
+                self.lvsdata = json.load(ifile)
+
+            # Populate treeview with text
+            self.toppane.lvsreport.json_repopulate(self.lvsdata)
+ 
+        else:
+            print("Error:  No output file generated from LVS.")
+
+    def findrecord(self, value):
+        print("Unimplemented function")
+
+    def findrecord_test(self, value):
+        # Check if socket is defined;  if not, attempt to open one
+        if not self.msock:
+            try:
+                self.msock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+            except:
+                 print("No response from layout tool.")
+
+            if self.msock:
+                self.msock.connect(("0.0.0.0", 12946))
+                self.msock.setblocking(False)
+        if self.msock:
+            # Pull name of net or device from 'value'
+            # This is a test:
+            self.msock.sendall(b'box 0 0 100 100\r\n')
+
+if __name__ == '__main__':
+    options = []
+    arguments = []
+    for item in sys.argv[1:]:
+        if item.find('-', 0) == 0:
+            options.append(item)
+        else:
+            arguments.append(item)
+
+    root = tkinter.Tk()
+    app = LVSManager(root)
+    if arguments:
+        if len(arguments) >= 2:
+            app.set_project(arguments[0], project_name=arguments[1])
+        else:
+            app.set_project(arguments[0])
+
+    root.mainloop()

tcltk/netgen.tcl.in

@@ -562,12 +562,13 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
             if {[netgen::print queue] != {}} {
 	       if {([lsearch $noflat [lindex $endval 0]] == -1) &&
 			([lsearch $noflat [lindex $endval 1]] == -1)} {
-	           netgen::log put "  Flattening non-matched subcircuits $endval"
+	           netgen::log put "  Flattening non-matched subcircuits $endval\n"
 	           netgen::flatten class "[lindex $endval 0] $fnum1"
 	           netgen::flatten class "[lindex $endval 1] $fnum2"
 	       } else {
-	           netgen::log put "  Continuing with black-boxed subcircuits $endval"
-		   lappend matcherr [lindex $endval 0]
+	           netgen::log put "  Continuing with black-boxed subcircuits $endval\n"
+		   lappend matcherr [lindex $endval 0]"($fnum1)"
+		   lappend matcherr [lindex $endval 1]"($fnum2)"
 	           # Match pins
                    netgen::log echo off
 	           if {$dolist == 1} {
@@ -609,16 +610,15 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
       } else {
 	 # Flatten the non-matching subcircuit (but not the top-level cells)
          if {[netgen::print queue] != {}} {
-	    if {([lsearch $noflat [lindex $endval 1]] == -1) &&
+	    if {([lsearch $noflat [lindex $endval 0]] == -1) &&
 		    ([lsearch $noflat [lindex $endval 1]] == -1)} {
-	       netgen::log put "  Flattening non-matched subcircuits $endval"
+	       netgen::log put "  Flattening non-matched subcircuits $endval\n"
 	       netgen::flatten class "[lindex $endval 0] $fnum1"
 	       netgen::flatten class "[lindex $endval 1] $fnum2"
 	    } else {
-	       netgen::log put "  Continuing with black-boxed subcircuits $endval"
-	       lappend matcherr [lindex $endval 0]
-	       netgen::log put "  Continuing with black-boxed subcircuits $endval"
-	       lappend matcherr [lindex $endval 0]
+	       netgen::log put "  Continuing with black-boxed subcircuits $endval\n"
+	       lappend matcherr [lindex $endval 0]"($fnum1)"
+	       lappend matcherr [lindex $endval 0]"($fnum2)"
 	       # Match pins
                netgen::log echo off
 	       if {$dolist == 1} {
@@ -656,10 +656,10 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
       verify only
    }
    if {$properr != {}} {
-      netgen::log put "The following cells had property errors: $properr\n"
+      netgen::log put "The following cells had property errors:\n " [regsub -all { } $properr "\n "] "\n"
    }
    if {$matcherr != {}} {
-      netgen::log put "The following subcells failed to match: $matcherr\n"
+      netgen::log put "The following subcells failed to match:\n " [regsub -all { } $matcherr "\n "] "\n"
    }
    if {$dolog} {
       netgen::log end

tcltk/tclnetgen.c

@@ -32,6 +32,9 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include "print.h"
 #include "query.h"	/* for ElementNodes() */
 #include "hash.h"
+#include "xilinx.h"
+#include "tech.h"
+#include "flatten.h"
 
 #ifndef TRUE
 #define TRUE 1
@@ -976,7 +979,7 @@ _netgen_writenet(ClientData clientData,
          SpiceCell(repstr, filenum, "");
          break;
       case VERILOG_IDX:
-         VerilogModule(repstr, filenum, "");
+         VerilogTop(repstr, filenum, "");
          break;
       case WOMBAT_IDX:
          Wombat(repstr,NULL);
@@ -2066,6 +2069,7 @@ _netcmp_format(ClientData clientData,
 	Tcl_WrongNumArgs(interp, 1, objv, "[col1_width [col2_width]]");
 	return TCL_ERROR;
     }
+    return TCL_OK;
 }
 
 /*------------------------------------------------------*/
@@ -2091,8 +2095,9 @@ _netcmp_compare(ClientData clientData,
    int dohierarchy = FALSE;
    int assignonly = FALSE;
    int argstart = 1, qresult, llen, result;
+   int hascontents1, hascontents2;
    struct Correspond *nextcomp;
-   struct nlist *tp;
+   struct nlist *tp1 = NULL, *tp2 = NULL;
    Tcl_Obj *flist = NULL;
 
    if (objc > 1) {
@@ -2135,24 +2140,24 @@ _netcmp_compare(ClientData clientData,
       }
       else if ((objc - argstart) == 2) {
 
-	 result = CommonParseCell(interp, objv[argstart], &tp, &fnum1);
+	 result = CommonParseCell(interp, objv[argstart], &tp1, &fnum1);
          if (result != TCL_OK) return TCL_ERROR;
 	 else if (fnum1 == -1) {
 	    Tcl_SetResult(interp, "Cannot use wildcard with compare command.\n",
 			NULL);
 	    return TCL_ERROR;
 	 }
-         name1 = tp->name;
+         name1 = tp1->name;
 	 argstart++;
 
-	 result = CommonParseCell(interp, objv[argstart], &tp, &fnum2);
+	 result = CommonParseCell(interp, objv[argstart], &tp2, &fnum2);
          if (result != TCL_OK) return TCL_ERROR;
 	 else if (fnum2 == -1) {
 	    Tcl_SetResult(interp, "Cannot use wildcard with compare command.\n",
 			NULL);
 	    return TCL_ERROR;
 	 }
-         name2 = tp->name;
+         name2 = tp2->name;
 
          if (dohierarchy) {
 	    RemoveCompareQueue();
@@ -2191,11 +2196,34 @@ _netcmp_compare(ClientData clientData,
       ConvertGlobals(name2, fnum2);
    }
 
-   CreateTwoLists(name1, fnum1, name2, fnum2, dolist);
-   while (PrematchLists(name1, fnum1, name2, fnum2) > 0) {
-      Fprintf(stdout, "Making another compare attempt.\n");
-      CreateTwoLists(name1, fnum1, name2, fnum2, dolist);
+   tp1 = LookupCellFile(name1, fnum1);
+   tp2 = LookupCellFile(name2, fnum2);
+
+   hascontents1 = HasContents(tp1);
+   hascontents2 = HasContents(tp2);
+
+   if (hascontents1 && !hascontents2 && (tp2->flags & CELL_PLACEHOLDER)) {
+       Fprintf(stdout, "Circuit 2 cell %s is a black box; will not flatten "
+                        "Circuit 1\n", name2);
    }
+   else if (hascontents2 && !hascontents1 && (tp1->flags & CELL_PLACEHOLDER)) {
+       Fprintf(stdout, "Circuit 1 cell %s is a black box; will not flatten "
+                        "Circuit 2\n", name1);
+   }
+   else if (hascontents1 || hascontents2) {
+       FlattenUnmatched(tp1, name1, 1, 0);
+       FlattenUnmatched(tp2, name2, 1, 0);
+       DescribeContents(name1, fnum1, name2, fnum2);
+
+       while (PrematchLists(name1, fnum1, name2, fnum2) > 0) {
+          Fprintf(stdout, "Making another compare attempt.\n");
+          Printf("Flattened mismatched instances and attempting compare again.\n");
+          FlattenUnmatched(tp1, name1, 1, 0);
+          FlattenUnmatched(tp2, name2, 1, 0);
+          DescribeContents(name1, fnum1, name2, fnum2);
+       }
+   }
+   CreateTwoLists(name1, fnum1, name2, fnum2, dolist);
 
    // Return the names of the two cells being compared, if doing "compare
    // hierarchical".  If "-list" was specified, then append the output
@@ -3027,11 +3055,11 @@ _netcmp_equate(ClientData clientData,
 			(tp2->flags & CELL_PLACEHOLDER)) {
 		if (tp1->flags & CELL_PLACEHOLDER) {
 		    Fprintf(stdout, "Warning: Equate pins:  cell %s "
-			"has no definition, treated as a black box.\n", name1);
+			"is a placeholder, treated as a black box.\n", name1);
 		}
 		if (tp2->flags & CELL_PLACEHOLDER) {
 		    Fprintf(stdout, "Warning: Equate pins:  cell %s "
-			"has no definition, treated as a black box.\n", name2);
+			"is a placeholder, treated as a black box.\n", name2);
 		}
 		// If a cell in either circuit is marked as a black box, then
 		// the cells in both circuits should be marked as a black box.