Merge branch 'master' into netgen-1.5

marked as unneeded, so I simply removed the code rather than
debug the issue, which was that buses got the delimeters erased
for checking but never put back again.  Also:  Modified the verilog
reading code so that if an empty set "()" is given for a pin, then
the initial proxy, which is a single net with the name prefix
"_noconnect_", can be promoted to a bus if further processing
reveals it to be a bus and not a single-bit signal.

.github/workflows/main.yml

@@ -0,0 +1,40 @@
+# This is a basic workflow to help you get started with Actions
+
+name: CI
+
+# Controls when the workflow will run
+on:
+  # Triggers the workflow on push or pull request events but only for the master branch
+  push:
+    branches: [ master ]
+  pull_request:
+    branches: [ master ]
+
+  # Allows you to run this workflow manually from the Actions tab
+  workflow_dispatch:
+
+# A workflow run is made up of one or more jobs that can run sequentially or in parallel
+jobs:
+  # This workflow contains a single job called "build"
+  build:
+    # The type of runner that the job will run on
+    runs-on: ubuntu-latest
+
+    # Steps represent a sequence of tasks that will be executed as part of the job
+    steps:
+      # Runs a set of commands using the runners shell
+      #- name: Logging into Dockerhub
+      #  run: docker login -u ${{ secrets.DOCKERHUB_USERNAME }} -p ${{ secrets.DOCKERHUB_PASSWORD }}
+        
+      - name: Pulling the docker image
+        run: docker pull vezzal/vezzal:v1
+        
+      - name: Start the container with the docker image
+        run: docker run -id --name test_netgen vezzal/vezzal:v1 bash | exit
+        
+      - name: Run the testing on the container and send the mail
+        run: docker exec test_netgen /vezzal/test_netgen.sh "[email protected],[email protected]" ${{ secrets.MAILING_KEY }}
+        
+  
+      
+          

README.md

@@ -1,4 +1,8 @@
-NETGEN:  VERSION 1.5
+![Continuous Integration](https://github.com/RTimothyEdwards/netgen/actions/workflows/main.yml/badge.svg)
+
+# NETGEN
+
+### VERSION 1.5
 
 NETGEN is a general-purpose netlist management system.  It can read
 and write several netlist formats, including NTK (Caltech, CMU),
@@ -87,6 +91,49 @@ and IRSIM version 9.7:
 
 Note: For FreeBSD, use 'gmake' instead.
 
+Note: On MacOS (Big Sur) follow the following procedure. If you have installed `xschem` and `magic` already on MacOS then steps (1) and (2) can likely be skipped.
+
+**1) Build Tcl for X11**
+
+We are following the instructions from `xschem` (https://github.com/StefanSchippers/xschem/blob/master/README_MacOS.md). 
+
+* Download `Tcl` from https://prdownloads.sourceforge.net/tcl/tcl8.6.10-src.tar.gz
+
+We are using not `opt` but `opt2` so that this `Tcl` does not interfere with `tcl-tk` from HomeBrew.
+
+```
+./configure --prefix=/usr/local/opt2/tcl-tk  
+make
+make install
+```
+
+**2) Build Tk for X11**
+
+* Download `Tk` from https://prdownloads.sourceforge.net/tcl/tk8.6.10-src.tar.gz
+
+```
+./configure --prefix=/usr/local/opt2/tcl-tk \
+--with-tcl=/usr/local/opt2/tcl-tk/lib --with-x \
+--x-includes=/opt/X11/include --x-libraries=/opt/X11/lib  
+make
+make install
+```
+
+**3) Build netgen**
+
+We need to provide this custom-built `tcl-tk` and suppress compilation errors.
+
+```
+./configure --with-tcl=/usr/local/opt2/tcl-tk/lib \
+--with-tk=/usr/local/opt2/tcl-tk/lib \
+--x-includes=/opt/X11/include \
+--x-libraries=/opt/X11/lib \
+CFLAGS=-Wno-error=implicit-function-declaration
+make
+make install
+```
+
+
 IN CASE OF FAILURE
 -------------------
 Please contact me (tim@opencircuitdesign.com) to report compile-time and

VERSION

@@ -1 +1 @@
-1.5.179
+1.5.215

base/ext.c

@@ -23,12 +23,13 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include <stdio.h>
 #include <stdlib.h>	/* for strtod() */
 #include <stdarg.h>
+#include <ctype.h>
 
 #include "netgen.h"
-#include "hash.h"
 #include "objlist.h"
 #include "netfile.h"
 #include "print.h"
+#include "hash.h"
 
 void extCell(char *name, int filenum)
 {
@@ -186,7 +187,7 @@ char *ReadExt(char *fname, int doflat, int *fnum)
   /* Make sure all .ext file reading is case sensitive */
   matchfunc = match;
   matchintfunc = matchfile;
-  hashfunc = hash;
+  hashfunc = hashcase;
 
   if (LookupCellFile(fname, filenum) != NULL) {
     Printf("Error:  Duplicate cell name \"%s\"!\n", fname);
@@ -652,7 +653,7 @@ char *ReadSim(char *fname, int *fnum)
   /* Make sure all .sim file reading is case sensitive */
   matchfunc = match;
   matchintfunc = matchfile;
-  hashfunc = hash;
+  hashfunc = hashcase;
 
   CellDef(fname, filenum);
 

base/flatten.c

@@ -254,9 +254,10 @@ void flattenCell(char *name, int file)
 int flattenInstancesOf(char *name, int fnum, char *instance)
 {
   struct objlist *ParentParams;
-  struct objlist *ParentProps;
+  struct objlist *ParentProps, *CurrentProp;
   struct objlist *NextObj, *LastObj, *prepp;
-  struct objlist *ChildObjList;
+  struct objlist *ChildObjList, *ChildListEnd;
+  struct objlist *ChildStart, *ChildEnd, *ParentEnd, *ParentNext;
   struct nlist *ThisCell;
   struct  nlist *ChildCell;
   struct objlist *tmp, *ob2, *ob3;
@@ -334,215 +335,264 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
 		ParentProps = ParentProps->next) {
 	 if (ParentProps->type == PROPERTY) break;
       }
-      if (ParentProps && (ParentProps->type != PROPERTY)) ParentProps = NULL;
-
-      /* not primitive, so need to flatten this instance */
-      notdone = 1;
-      /* if this is a new instance, flatten it */
-      /* if (ChildCell->dumped == 0) flattenCell(ParentParams->model.class, file); */
-
-      ChildObjList = CopyObjList(ChildCell->cell, 1);
-      numflat++;
-
-      /* update node numbers in child to unique numbers */
-      oldmax = 0;
-      for (tmp = ChildObjList; tmp != NULL; tmp = tmp->next) 
-	if (tmp->node > oldmax) oldmax = tmp->node;
-      if (nextnode <= oldmax) nextnode = oldmax + 1;
-
-      for (tmp = ChildObjList; tmp != NULL; tmp = tmp->next) 
-	if (tmp->node <= oldmax && tmp->node > 0) {
-	  if (Debug) Printf("Update node %d --> %d\n", tmp->node, nextnode);
-	  UpdateNodeNumbers(ChildObjList, tmp->node, nextnode);
-	  nextnode++;
-	}
-
-      /* copy nodenumbers of ports from parent */
-      ob2 = ParentParams;
-      for (tmp = ChildObjList; tmp != NULL; tmp = tmp->next) 
-	if (IsPort(tmp)) {
-	  if (tmp->node > 0) {
-	    if (ob2->node == -1) {
-
-	       // Before commiting to attaching to a unconnected node, see
-	       // if there is another node in ParentParams with the same
-	       // name and a valid node number.  If so, connect them.  In
-	       // the broader case, it may be necessary to consider all
-	       // nodes, not just those with node == -1, and call join()
-	       // here to update all node numbers in the parent cell.
-	       // In that case, a more efficient method is needed for
-	       // tracking same-name ports.
-
-	       for (ob3 = ParentParams; ob3 && ob3->type >= FIRSTPIN; ob3 = ob3->next) {
-		   if (ob3 == ob2) continue;
-		   if ((*matchfunc)(ob3->name, ob2->name) && ob3->node != -1) {
-		       ob2->node = ob3->node;
-		       break;
-		   }
-	       }
-	    }
-	    if (Debug) {
-	       // Printf("  Sealing port: %d to node %d\n", tmp->node, ob2->node);
-	       Printf("Update node %d --> %d\n", tmp->node, ob2->node);
-	    }
-	    UpdateNodeNumbers(ChildObjList, tmp->node, ob2->node);
-	  }
-
-	/* in pathological cases, the lengths of the port lists may
-         * change.  This is an error, but that is no reason to allow
-         * the code to core dump.  We avoid this by placing a 
-         * superfluous check on ob2->type
-         */
-
-	  if (ob2 != NULL)
-	    ob2 = ob2->next;
-
-	  if (ob2 == NULL) break;
-	}
-
-      /* Using name == NULL to indicate that a .ext file is being */
-      /* flattened on the fly.  This is quick & dirty.		  */
-
-      if (name != NULL) {
-        /* delete all port elements from child */
-        while ((ChildObjList != NULL) && IsPort(ChildObjList)) {
-	  /* delete all ports at beginning of list */
-	  if (Debug) Printf("deleting leading port from child\n");
-	  tmp = ChildObjList->next;
-	  // FreeObjectAndHash(ChildObjList, ChildCell);
-	  FreeObject(ChildObjList);
-	  ChildObjList = tmp;
-        }
-        tmp = ChildObjList;
-        while (tmp && (tmp->next != NULL)) {
-	  if (IsPort(tmp->next)) {
-	    ob2 = (tmp->next)->next;
-	    if (Debug) Printf("deleting a port from child\n");
-	    // FreeObjectAndHash(tmp->next, ChildCell);
-	    FreeObject(tmp->next);
-	    tmp->next = ob2;
-	  } 
-	  else tmp = tmp->next;
-        }
+      if (ParentProps && (ParentProps->type != PROPERTY)) {
+	  ParentProps = NULL;
+	  CurrentProp = NULL;
       }
+      else
+	  CurrentProp = ParentProps;
 
-      /* for each element in child, prepend 'prefix' */
+      /* Find the end record of the parent cell and save it */
+      for (ParentEnd = (ParentProps) ? ParentProps : ParentParams;
+		ParentEnd && ParentEnd->next &&
+		/* Stop on a node or the next instance */
+		((ParentEnd->next->type > FIRSTPIN) ||
+		    (ParentEnd->next->type == PROPERTY));
+		ParentEnd = ParentEnd->next);
+
+      /* Not primitive, so need to flatten this instance */
+      notdone = 1;
+
+      /* Loop over property records.  Need to flatten once per	*/
+      /* property record (or more, if property has M > 1)	*/
+
+      ob2 = NULL;
+      ChildObjList = NULL;
+      ChildListEnd = NULL;
+      while (1) {
+
+         ChildStart = CopyObjList(ChildCell->cell, 1);
+         numflat++;
+
+         /* Find the end record of the child cell and save it */
+         for (ChildEnd = ChildStart; ChildEnd && ChildEnd->next;
+			ChildEnd = ChildEnd->next);
+
+         if (ChildListEnd == NULL) ChildListEnd = ChildEnd;
+
+         /* update node numbers in child to unique numbers */
+         oldmax = 0;
+         for (tmp = ChildStart; tmp != NULL; tmp = tmp->next) 
+	    if (tmp->node > oldmax) oldmax = tmp->node;
+         if (nextnode <= oldmax) nextnode = oldmax + 1;
+
+         for (tmp = ChildStart; tmp != NULL; tmp = tmp->next) 
+	    if (tmp->node <= oldmax && tmp->node > 0) {
+	       if (Debug) Printf("Update node %d --> %d\n", tmp->node, nextnode);
+	       UpdateNodeNumbers(ChildStart, tmp->node, nextnode);
+	       nextnode++;
+	    }
+
+         /* copy nodenumbers of ports from parent */
+         ob2 = ParentParams;
+         for (tmp = ChildStart; tmp != NULL; tmp = tmp->next)  {
+	    if (IsPort(tmp)) {
+	       if (tmp->node > 0) {
+	          if (ob2->node == -1) {
+
+	             // Before commiting to attaching to a unconnected node, see
+	             // if there is another node in ParentParams with the same
+	             // name and a valid node number.  If so, connect them.  In
+	             // the broader case, it may be necessary to consider all
+	             // nodes, not just those with node == -1, and call join()
+	             // here to update all node numbers in the parent cell.
+	             // In that case, a more efficient method is needed for
+	             // tracking same-name ports.
+
+	             for (ob3 = ParentParams; ob3 && ob3->type >= FIRSTPIN;
+					ob3 = ob3->next) {
+		        if (ob3 == ob2) continue;
+		        if ((*matchfunc)(ob3->name, ob2->name) && ob3->node != -1) {
+		           ob2->node = ob3->node;
+		           break;
+		        }
+	             }
+	          }
+	          if (Debug) {
+	             // Printf("  Sealing port: %d to node %d\n", tmp->node, ob2->node);
+	             Printf("Update node %d --> %d\n", tmp->node, ob2->node);
+	          }
+	          UpdateNodeNumbers(ChildStart, tmp->node, ob2->node);
+	       }
+
+	       /* in pathological cases, the lengths of the port lists may
+                * change.  This is an error, but that is no reason to allow
+                * the code to core dump.  We avoid this by placing a 
+                * superfluous check on ob2->type
+                */
+	       if (ob2 != NULL) ob2 = ob2->next;
+
+	       if (ob2 == NULL) break;
+	    }
+	 }
+
+         /* Using name == NULL to indicate that a .ext file is being 	*/
+         /* flattened on the fly.  This is quick & dirty.		*/
+
+         if (name != NULL) {
+            /* delete all port elements from child */
+            while ((ChildStart != NULL) && IsPort(ChildStart)) {
+	       /* delete all ports at beginning of list */
+	       if (Debug) Printf("deleting leading port from child\n");
+	       tmp = ChildStart->next;
+	       FreeObject(ChildStart);
+	       ChildStart = tmp;
+            }
+            tmp = ChildStart;
+            while (tmp && (tmp->next != NULL)) {
+	       if (IsPort(tmp->next)) {
+	          ob2 = (tmp->next)->next;
+	          if (Debug) Printf("deleting a port from child\n");
+	          FreeObject(tmp->next);
+	          tmp->next = ob2;
+	       } 
+	       else tmp = tmp->next;
+            }
+	    if (ChildStart == NULL) {
+	       if (ChildListEnd == ChildEnd) ChildListEnd = NULL;
+	       ChildEnd = NULL;
+	    }
+         }
+
+         /* for each element in child, prepend 'prefix' */
 #if !OLDPREFIX
-      /* replaces all the sprintf's below */
-      strcpy(tmpstr,ParentParams->instance.name);
-      strcat(tmpstr,SEPARATOR);
-      prefixlength = strlen(tmpstr);
+         /* replaces all the sprintf's below */
+         strcpy(tmpstr,ParentParams->instance.name);
+         strcat(tmpstr,SEPARATOR);
+         prefixlength = strlen(tmpstr);
 #endif
-      for (tmp = ChildObjList; tmp != NULL; tmp = tmp->next) {
-	if (tmp->type == PROPERTY)
-	    continue;
+         for (tmp = ChildStart; tmp != NULL; tmp = tmp->next) {
+	    if (tmp->type == PROPERTY)
+	       continue;
 
-	else if (IsGlobal(tmp)) {
-	   /* Keep the name but search for node of same name in parent	*/
-	   /* and replace the node number, if found.			*/
+	    else if (IsGlobal(tmp)) {
+	       /* Keep the name but search for node of same name in parent	*/
+	       /* and replace the node number, if found.			*/
 
-	   for (ob2 = ThisCell->cell; ob2 != NULL; ob2 = ob2->next) {
-	      /* Type in parent may be a port, not a global */
-	      if (ob2->type == tmp->type || ob2->type == PORT) {
-	         if ((*matchfunc)(tmp->name, ob2->name)) {
-		    if (ob2->node >= 0) {
-		       // Replace all child objects with this node number
-		       rnodenum = tmp->node;
-		       for (ob3 = ChildObjList; ob3 != NULL; ob3 = ob3->next) {
-			  if (ob3->node == rnodenum)
-			     ob3->node = ob2->node;
-		       }
-		       break;
-		    }
-		 }
-	      }
-	   }
-	   // Don't hash this if the parent had a port of this name
-	   if (!ob2 || ob2->type != PORT)
-	      HashPtrInstall(tmp->name, tmp, &(ThisCell->objdict));
-	   continue;
-	}
+	       for (ob2 = ThisCell->cell; ob2 != NULL; ob2 = ob2->next) {
+	          /* Type in parent may be a port, not a global */
+	          if (ob2->type == tmp->type || ob2->type == PORT) {
+	             if ((*matchfunc)(tmp->name, ob2->name)) {
+		        if (ob2->node >= 0) {
+		           // Replace all child objects with this node number
+		           rnodenum = tmp->node;
+		           for (ob3 = ChildStart; ob3 != NULL; ob3 = ob3->next) {
+			      if (ob3->node == rnodenum)
+			         ob3->node = ob2->node;
+		           }
+		           break;
+		        }
+		     }
+	          }
+	       }
+	       // Don't hash this if the parent had a port of this name
+	       if (!ob2 || ob2->type != PORT)
+	          HashPtrInstall(tmp->name, tmp, &(ThisCell->objdict));
+	       continue;
+	    }
 
 #if OLDPREFIX	
-	sprintf(tmpstr, "%s%s%s", ParentParams->instance.name, SEPARATOR,
-		tmp->name);
+	    sprintf(tmpstr, "%s%s%s", ParentParams->instance.name, SEPARATOR,
+				tmp->name);
 #else
-	strcpy(tmpstr+prefixlength,tmp->name);
+	    strcpy(tmpstr+prefixlength,tmp->name);
 #endif
-	if (Debug) Printf("Renaming %s to %s\n", tmp->name, tmpstr);
-	FreeString(tmp->name);
-	tmp->name = strsave(tmpstr);
-	HashPtrInstall(tmp->name, tmp, &(ThisCell->objdict));
-	if ((tmp->type != NODE) && (tmp->instance.name != NULL)) {
+	    if (Debug) Printf("Renaming %s to %s\n", tmp->name, tmpstr);
+	    FreeString(tmp->name);
+	    tmp->name = strsave(tmpstr);
+	    HashPtrInstall(tmp->name, tmp, &(ThisCell->objdict));
+	    if ((tmp->type != NODE) && (tmp->instance.name != NULL)) {
 #if OLDPREFIX
-	   sprintf(tmpstr, "%s%s%s", ParentParams->instance.name, SEPARATOR,
-		    tmp->instance.name);
+	       sprintf(tmpstr, "%s%s%s", ParentParams->instance.name, SEPARATOR,
+		    		tmp->instance.name);
 #else
-	   strcpy(tmpstr+prefixlength,tmp->instance.name);
+	       strcpy(tmpstr+prefixlength,tmp->instance.name);
 #endif
-	   FreeString(tmp->instance.name);
-	   tmp->instance.name = strsave(tmpstr);
-	   if (tmp->type == FIRSTPIN) 
-	      HashPtrInstall(tmp->instance.name, tmp, &(ThisCell->instdict));
-        }
-      }
-
-      /* Do property inheritance */
-
-      if (ParentProps) {
-         for (ob2 = ChildObjList; ob2 != NULL; ob2=ob2->next) {
-
-	    /* If the parent cell has properties to declare, then	*/
-	    /* pass them on to children.  Use globals only if the	*/
-	    /* spiceparams dictionary is active (during file reading	*/
-	    /* only).							*/
-
-	    if (ob2->type == PROPERTY)
-		ReduceExpressions(ob2, ParentProps, ChildCell,
-			(spiceparams.hashtab == NULL) ? 0 : 1);
+	       FreeString(tmp->instance.name);
+	       tmp->instance.name = strsave(tmpstr);
+	       if (tmp->type == FIRSTPIN) 
+	          HashPtrInstall(tmp->instance.name, tmp, &(ThisCell->instdict));
+            }
          }
+
+         /* Do property inheritance */
+
+         /* NOTE:  Need to do:  Check properties for M > 1 and decrement
+          * and repeat without moving CurrentProp
+          */
+
+         if (CurrentProp) {
+            for (ob2 = ChildStart; ob2 != NULL; ob2=ob2->next) {
+
+	       /* If the parent cell has properties to declare, then	*/
+	       /* pass them on to children.  Use globals only if the	*/
+	       /* spiceparams dictionary is active (during file		*/
+	       /* reading only).					*/
+
+	       if (ob2->type == PROPERTY)
+		  ReduceExpressions(ob2, CurrentProp, ChildCell,
+				(spiceparams.hashtab == NULL) ? 0 : 1);
+            }
+
+            /* Repeat for each property record, as each property represents a
+             * unique instance that must be flattened individually.
+             */
+
+	    CurrentProp = CurrentProp->next;
+	    if ((CurrentProp == NULL) || (CurrentProp->type != PROPERTY)) break;
+         }
+         else break;
+
+         /* Put the child cell at the start of ChildObjList */
+         ChildEnd->next = ChildObjList;
+         ChildObjList = ChildStart;
       }
 
-      /* splice instance out of parent */
-      if ((ParentParams == ThisCell->cell) && (ChildObjList == NULL)) {
-	ThisCell->cell = ob2;	/* Child cell was empty */
-	tmp = ob2;
+      /* Put the child cell at the start of ChildObjList */
+      if (ChildEnd) {
+         ChildEnd->next = ChildObjList;
+         ChildObjList = ChildStart;
       }
-      else {
+
+      /* Pull the instance out of the parent */
+
+      if ((ParentParams != ThisCell->cell) || (ChildObjList != NULL)) {
          if (ParentParams == ThisCell->cell) {
-	   /* ParentParams are the very first thing in the list */
-	   ThisCell->cell = ChildObjList;
-	   for (ob2 = ChildObjList; ob2 && ob2->next != NULL; ob2 = ob2->next) ;
+	    /* ParentParams are the very first thing in the list */
+	    ThisCell->cell = ChildObjList;
          }
-         else {
-	   /* find ParentParams in ThisCell list.  In most cases, LastObj   */
-	   /* should be pointing to it.					    */
-	   if (LastObj && (LastObj->next == ParentParams)) {
-	       ob2 = LastObj;
-	   }
-	   else {
-	      for (ob2 = LastObj; ob2 && ob2->next != ParentParams; ob2=ob2->next); 
-	      if (ob2 == NULL) {
-		 /* It should not happen that LastObj is ahead of ParentParams	*/
-		 /* but just in case, this long loop will find it.		*/
-	         for (ob2 = ThisCell->cell; ob2 && ob2->next != ParentParams; ob2=ob2->next); 
-	      }
-	   }
-	   if (ob2)
-	         for (ob2->next = ChildObjList; ob2->next != NULL; ob2 = ob2->next) ;
+         else if (ChildObjList) {
+	    /* find ParentParams in ThisCell list.  In most cases, LastObj  */
+	    /* should be pointing to it.				    */
+	    if (LastObj && (LastObj->next == ParentParams)) {
+	       LastObj->next = ChildObjList;
+	    }
+	    else {
+	       for (ob2 = LastObj; ob2 && ob2->next != ParentParams;
+			ob2 = ob2->next); 
+	       if (ob2 == NULL) {
+		  /* It should not happen that LastObj is ahead of ParentParams	*/
+		  /* but just in case, this long loop will find it.		*/
+	          for (ob2 = ThisCell->cell; ob2 && ob2->next != ParentParams;
+				ob2 = ob2->next); 
+	       }
+	       ob2->next = ChildObjList;
+	    }
          }
-         /* now, ob2 is last element in child list, so skip and reclaim parent */
+	 else {
+	    /* The child was completely optimized out, so close list around it */
+	    LastObj->next = ParentEnd->next;
+	 }
 
-         tmp = ParentParams;
-         do {
-	   tmp = tmp->next;
-         } while ((tmp != NULL) && ((tmp->type > FIRSTPIN) || (tmp->type == PROPERTY)));
-         if (ob2) ob2->next = tmp;
+         /* Link end of child list into the parent */
+	 if (ChildListEnd && ParentEnd)
+	    ChildListEnd->next = ParentEnd->next;
       }
-      while (ParentParams != tmp) {
-	ob2 = ParentParams->next;
-	FreeObjectAndHash(ParentParams, ThisCell);
-	ParentParams = ob2;
+      ParentNext = (ParentEnd) ? ParentEnd->next : NULL;
+      while (ParentParams != ParentNext) {
+	 ob2 = ParentParams->next;
+	 FreeObjectAndHash(ParentParams, ThisCell);
+	 ParentParams = ob2;
       }
       NextObj = ParentParams;
     }				/* repeat until no more instances found */
@@ -1371,6 +1421,22 @@ typedef struct ecomplist {
     ECompListPtr next;
 } ECompList;
 
+/*----------------------------------------------------------------------*/
+/* Determine if a cell contains at least one device or subcircuit	*/
+/*----------------------------------------------------------------------*/
+
+int
+HasContents(struct nlist *tc)
+{
+    struct objlist *ob;
+
+    for (ob = tc->cell; ob; ob = ob->next)
+	if (ob->type == FIRSTPIN)
+	    return TRUE;
+
+    return FALSE;
+}
+
 /*------------------------------------------------------*/
 /* Survey the contents of a cell and sort into a hash	*/
 /*------------------------------------------------------*/
@@ -1468,6 +1534,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
     struct hashdict compdict;
     ECompare *ecomp, *ncomp;
     ECompList *list0X, *listX0;
+    int hascontents1, hascontents2;
     int match, modified = 0;
 
     if (file1 == -1)
@@ -1483,6 +1550,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
     if (tc1 == NULL || tc2 == NULL) return 0;
 
     InitializeHashTable(&compdict, OBJHASHSIZE);
+    listX0 = list0X = NULL;
 
     // Gather information about instances of cell "name1"
     SurveyCell(tc1, &compdict, file1, file2, 0);
@@ -1495,7 +1563,6 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
     // in the hierarchy of each instance contain devices
     // or subcircuits that have more in the compared circuit.
 
-    listX0 = list0X = NULL;
     ecomp = (ECompare *)HashFirst(&compdict);
     while (ecomp != NULL) {
 
@@ -1532,19 +1599,20 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 			}
 		    }
 		    else {
-		       match = 0;
+		       // cell exists in one circuit but not the other, so flatten it.
+		       // match = 0;
 		       break;
 		    }
 		}
 	    }
 	    if (match) {
-		if (ecomp->cell1) {
+		if (ecomp->cell1 && (ecomp->num1 > 0)) {
 		    Fprintf(stdout, "Flattening instances of %s in cell %s"
 				" makes a better match\n", ecomp->cell1->name,
 				name1);
 		    flattenInstancesOf(name1, file1, ecomp->cell1->name); 
 		}
-		if (ecomp->cell2) {
+		if (ecomp->cell2 && (ecomp->num2 > 0)) {
 		    Fprintf(stdout, "Flattening instances of %s in cell %s"
 				" makes a better match\n", ecomp->cell2->name,
 				name2);
@@ -1599,7 +1667,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 	}
 
 	/* Case 2:  Cell2 class is a subcircuit, and flattening	*/
-	/* (it without regard to cell1) improves the matching.	*/
+	/* it (without regard to cell1) improves the matching.	*/
 
 	else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell2 != NULL) &&
 			(ecomp->num2 != 0) && (ecomp->cell2->class == CLASS_SUBCKT)) {
@@ -1657,7 +1725,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 	}
 	
 	/* Case 3:  Cell1 class is a subcircuit, and flattening	*/
-	/* (it without regard to cell1) improves the matching.	*/
+	/* it (without regard to cell1) improves the matching.	*/
 
 	else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell1 != NULL) &&
 			(ecomp->num1 != 0) && (ecomp->cell1->class == CLASS_SUBCKT)) {
@@ -2014,6 +2082,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 	}
     }
 
+done:
     // Free the hash table and its contents.
 
     ecomp = (ECompare *)HashFirst(&compdict);

base/flatten.h

@@ -0,0 +1,8 @@
+#ifndef _FLATTEN_H
+#define _FLATTEN_H
+
+extern int UniquePins(char *name, int filenum);
+extern void flattenCell(char *name, int file);
+extern int HasContents(struct nlist *);
+
+#endif /* _FLATTEN_H */

base/hash.c

@@ -30,8 +30,8 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #endif
 
 #include "netgen.h"
-#include "hash.h"
 #include "objlist.h"
+#include "hash.h"
 
 unsigned long (*hashfunc)(char *, int) = NULL;
 int (*matchfunc)(char *, char *) = NULL;
@@ -148,7 +148,7 @@ unsigned long hashnocase(char *s, int hashsize)
 	return (hashsize == 0) ? hashval : (hashval % hashsize);
 }
 
-unsigned long hash(char *s, int hashsize)
+unsigned long hashcase(char *s, int hashsize)
 {
 	unsigned long hashval;
 	

base/hash.h

@@ -48,7 +48,7 @@ extern void *HashFirst(struct hashdict *dict);
 extern void *HashNext(struct hashdict *dict);
 
 extern unsigned long hashnocase(char *s, int hashsize);
-extern unsigned long hash(char *s, int hashsize);
+extern unsigned long hashcase(char *s, int hashsize);
 
 extern int (*matchfunc)(char *, char *);
 /* matchintfunc() compares based on the name and the first	*/

base/netcmp.c

@@ -21,11 +21,13 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include "config.h"
 
 #include <stdio.h>
+#include <stdlib.h>  /* for rand(), abs(), etc */
 #include <setjmp.h>
 #include <signal.h>
 #include <time.h>    /* for time() as a seed for random number generator */
 #include <limits.h>
 #include <math.h>    /* for fabs() */
+#include <ctype.h>   /* for toupper() */
 
 #ifdef IBMPC
 #include <alloc.h>
@@ -45,11 +47,13 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include "netfile.h"
 #include "print.h"
 #include "dbug.h"
+#include "hash.h"
 
 #ifdef TCL_NETGEN
 int InterruptPending = 0;
 void (*oldinthandler)() = SIG_DFL;
 extern Tcl_Interp *netgeninterp;
+extern int check_interrupt();
 #endif
 
 /* define the following to debug core allocation */
@@ -620,15 +624,15 @@ struct FormattedList *FormatBadElementFragment(struct Element *E)
          for (elems = nodes[i]->node->elementlist; elems != NULL;
 			elems = elems->next)
 	    count++;
-
-         elemlist->flist[k].count = count;
-	 if (*ob->name != *ob->instance.name)	// e.g., "port_match_error"
-            elemlist->flist[k].name = ob->name;
-	 else
-            elemlist->flist[k].name = ob->name + strlen(ob->instance.name) + 1;
-         elemlist->flist[k].permute = (char)1;
-         k++;
       }
+
+      elemlist->flist[k].count = count;
+      if (*ob->name != *ob->instance.name)	// e.g., "port_match_error"
+         elemlist->flist[k].name = ob->name;
+      else
+         elemlist->flist[k].name = ob->name + strlen(ob->instance.name) + 1;
+      elemlist->flist[k].permute = (char)1;
+      k++;
     }
     else {				/* handle multiple permutable pins */
       struct objlist *ob2;
@@ -665,13 +669,16 @@ struct FormattedList *FormatBadElementFragment(struct Element *E)
 	    struct ElementList *elems;
 
 	    count = 0;
-	    if (nodes[j]->node == NULL) continue;	// ?
-	    for (elems = nodes[j]->node->elementlist; elems != NULL;
-		 elems = elems->next) 
-	      count++;
+	    if (nodes[j]->node == NULL)	/* Under what condition is the node NULL? */
+	       count++;
+	    else {
+	       for (elems = nodes[j]->node->elementlist; elems != NULL;
+			elems = elems->next) 
+	          count++;
+	    }
 	    if (count >= maxcount) {
-	      maxcount = count;
-	      maxindex = j;
+	       maxcount = count;
+	       maxindex = j;
 	    }
 	  }
 	}
@@ -867,10 +874,10 @@ struct FormattedList *FormatBadNodeFragment(struct Node *N)
       ob = pins[i]->subelement->element->object;
       for (n = pins[i]->subelement->element->nodelist; n != NULL; n = n->next){
 	if (n->pin_magic == pins[i]->subelement->pin_magic) {
-	  if (permute == 0) {
+	  if ((permute == 0) && (ob->instance.name != NULL)) {
 	     pinname = ob->name + strlen(ob->instance.name) + 1;
 	  }
-	  else {
+	  else if (ob->instance.name != NULL) {
 	     char *pinsave = pinname;
 	     pinname = (char *)MALLOC(strlen(pinsave) + strlen(ob->name +
 			strlen(ob->instance.name) + 1) + 2);
@@ -886,9 +893,8 @@ struct FormattedList *FormatBadNodeFragment(struct Node *N)
          WITH THE SAME HASH NUMBER, are on this node */
       for (j = i+1; j < fanout; j++) {
 	if (pins[j] != NULL && 
-	    (*matchfunc) (model,
-		  pins[j]->subelement->element->object->model.class) &&
-	    pins[i]->subelement->pin_magic == pins[j]->subelement->pin_magic) {
+	    (*matchfunc)(model, pins[j]->subelement->element->object->model.class) &&
+	    	    pins[i]->subelement->pin_magic == pins[j]->subelement->pin_magic) {
 	      count++;
 	      nodelist->fanout--;
 	      pins[j] = NULL;
@@ -968,16 +974,36 @@ void PrintBadNodeFragment(struct Node *N)
          WITH THE SAME HASH NUMBER, are on this node */
       for (j = i+1; j < fanout; j++) {
 	if (pins[j] != NULL && 
-	    (*matchfunc)(model,
-		  pins[j]->subelement->element->object->model.class) &&
-	    pins[i]->subelement->pin_magic == pins[j]->subelement->pin_magic) {
-	      count++;
-	      pins[j] = NULL;
-	    }
+	    (*matchfunc)(model, pins[j]->subelement->element->object->model.class) &&
+	    	    pins[i]->subelement->pin_magic == pins[j]->subelement->pin_magic) {
+	   count++;
+	   /* pins[j] = NULL; */ /* Done in diagnostic output, below */
+	 }
       }
 
-      if (i != 0) Fprintf(stdout, ";");
+      if (i != 0) {
+	 /* Fprintf(stdout, ";"); */
+	 Fprintf(stdout, "\n");
+	 Ftab(stdout, 32);
+      }
       Fprintf(stdout, " %s:%s = %d", model, pinname, count);
+
+      /* Diagnostic */
+      Fprintf(stdout, "\n");
+      Ftab(stdout, 25);
+      Fprintf(stdout, ">>>  %s", pins[i]->subelement->element->object->instance);
+      for (j = i+1; j < fanout; j++) {
+	if (pins[j] != NULL && 
+	    (*matchfunc)(model, pins[j]->subelement->element->object->model.class) &&
+	    	    pins[i]->subelement->pin_magic == pins[j]->subelement->pin_magic) {
+	   /* Diagnostic */
+           Fprintf(stdout, "\n");
+           Ftab(stdout, 25);
+           Fprintf(stdout, ">>>  %s", pins[j]->subelement->element->object->instance);
+	   pins[j] = NULL;
+	}
+      }
+
       pins[i] = NULL; /* not really necessary */
     }
   Fprintf(stdout, "\n");
@@ -1360,8 +1386,8 @@ void SortUnmatchedLists(nlists1, nlists2, n1max, n2max)
 		    nlists2[n1] = temp;
 		    HashPtrInstall(nlists2[n1]->name, (void *)((long)n1 + 1), &n2hash);
 		    HashPtrInstall(nlists2[n2]->name, (void *)((long)n2 + 1), &n2hash);
-		    SortFanoutLists(nlists1[n1], nlists2[n1]);
 		}
+		SortFanoutLists(nlists1[n1], nlists2[n1]);
 	    }
 	}
 
@@ -1416,8 +1442,13 @@ void SortUnmatchedLists(nlists1, nlists2, n1max, n2max)
 		    nlists1[n2] = temp;
 		    HashPtrInstall(nlists1[n1]->name, (void *)((long)n1 + 1), &n1hash);
 		    HashPtrInstall(nlists1[n2]->name, (void *)((long)n2 + 1), &n1hash);
-		    SortFanoutLists(nlists2[n2], nlists1[n2]);
 		}
+		SortFanoutLists(nlists2[n2], nlists1[n2]);
+	    }
+	    else if ((n1max == 1) && (n2max == 1)) {
+		/* Names didn't match but there's only one entry on each side,	*/
+		/* so do a sort anyway.						*/
+		SortFanoutLists(nlists2[n2], nlists1[n2]);
 	    }
 	}
 	/* For all nets that didn't match by name, match by content */
@@ -3122,7 +3153,7 @@ int FirstElementPass(struct Element *E, int noflat, int dolist)
   ostr = CALLOC(right_col_end + 2, sizeof(char));
 
   if (Debug == 0) {
-     Fprintf(stdout, "\nSubcircuit summary:\n");
+     Fprintf(stdout, "Subcircuit summary:\n");
      *(ostr + left_col_end) =  '|';
      *(ostr + right_col_end) = '\n';
      *(ostr + right_col_end + 1) = '\0';
@@ -3636,12 +3667,19 @@ int CreateCompareQueue(char *name1, int file1, char *name2, int file2)
          Fprintf(stdout, "Descend level %d circuit 2\n", level);
       DescendCompareQueue(tc2, tc1, level, 0, 1);
 
+      /* NOTE:  Preemptive flattening is inefficient and can cause
+       * unnecessary flattening of cells that will never be compared.
+       * let the prematch stage take care of this.
+       */
+      /*--------------------------------------
       if (Debug == TRUE)
          Fprintf(stdout, "Flatten level %d circuit 1\n", level);
       FlattenUnmatched(tc1, name1, level, 0);
       if (Debug == TRUE)
          Fprintf(stdout, "Flatten level %d circuit 2\n", level);
       FlattenUnmatched(tc2, name2, level, 0);
+      ---------------------------------------*/
+
       level--;
    }
 
@@ -3720,8 +3758,23 @@ void RemoveCompareQueue()
    CompareQueue = NULL;
 }
 
+/*----------------------------------------------------------------------*/
+/* Output a summary of the contents of the two circuits being compared	*/
+/*----------------------------------------------------------------------*/
+
+void DescribeContents(char *name1, int file1, char *name2, int file2)
+{
+    Fprintf(stdout, "\n");  // blank line before new circuit diagnostics in log file
+    /* print preliminary statistics */
+    Printf("\nContents of circuit 1:  ");
+    DescribeInstance(name1, file1);
+    Printf("Contents of circuit 2:  ");
+    DescribeInstance(name2, file2);
+    Printf("\n");
+}
+
 /*----------------------------------*/
-/* create an initial data structure */
+/* Create an initial data structure */
 /*----------------------------------*/
 
 void CreateTwoLists(char *name1, int file1, char *name2, int file2, int dolist)
@@ -3733,13 +3786,6 @@ void CreateTwoLists(char *name1, int file1, char *name2, int file2, int dolist)
 
     ResetState();
 
-    /* print preliminary statistics */
-    Printf("Contents of circuit 1:  ");
-    DescribeInstance(name1, file1);
-    Printf("Contents of circuit 2:  ");
-    DescribeInstance(name2, file2);
-    Printf("\n");
-
     if (file1 == -1)
         tc1 = LookupCell(name1);
     else
@@ -3753,7 +3799,7 @@ void CreateTwoLists(char *name1, int file1, char *name2, int file2, int dolist)
     /* determine if matching will be case sensitive or case insensitive */
     matchfunc = match;
     matchintfunc = matchfile;
-    hashfunc = hash;
+    hashfunc = hashcase;
     if (tc1 != NULL && tc2 != NULL) {
         if ((tc1->flags & CELL_NOCASE) && (tc2->flags & CELL_NOCASE)) {
 	   matchfunc = matchnocase;
@@ -4118,6 +4164,7 @@ void series_sort(struct objlist *ob1, struct nlist *tp1, int idx1, int run)
    sval = 1;
    cval = slop = 0.0;
    for (i = 0; i < run; i++) {
+      sl = NULL;
       merge_type = MERGE_NONE;
       for (p = 0;; p++) {
 	 vl = &(obp->instance.props[p]);
@@ -4146,13 +4193,13 @@ void series_sort(struct objlist *ob1, struct nlist *tp1, int idx1, int run)
 	 proplist[i].value = cval * (double)sval;
          proplist[i].slop = slop;
          proplist[i].avalue = 0;
-	 sl->value.ival = 1;
+	 if (sl) sl->value.ival = 1;
       }
       else if (merge_type == MERGE_S_PAR) {
 	 proplist[i].value = cval / (double)sval;
          proplist[i].slop = slop;
          proplist[i].avalue = 0;
-	 sl->value.ival = 1;
+	 if (sl) sl->value.ival = 1;
       }
       else {
 	 /* Components which declare no series addition method stay unsorted */
@@ -4254,10 +4301,12 @@ void parallel_sort(struct objlist *ob1, struct nlist *tp1, int idx1, int run)
    struct objlist *obn, *obp;
    propsort *proplist;
    struct property *kl;
-   struct valuelist *vl, *ml;
-   int i, p, mval, merge_type, has_crit = FALSE;
-   char c, *subs_crit = NULL;
-   double cval, tval, aval, slop, tslop;
+   struct valuelist *vl;
+   int i, p, mval, merge_type;
+   int has_crit;
+   char ca, co;
+   double tval, tslop;
+   double aval, pval, oval, aslop, pslop;
 
    obn = ob1->next;
    for (i = 0; i < idx1; i++) obn = obn->next;
@@ -4266,96 +4315,99 @@ void parallel_sort(struct objlist *ob1, struct nlist *tp1, int idx1, int run)
     * value and index.  Then sort that list, then use the sorted
     * indexes to sort the actual property linked list.
     *
-    * If there is no critical property listed, then it will sort on
-    * M first, and any additive property second, or any property at
-    * all if no additive property was found.  It is doubtful that any
-    * use case requires more than two properties for sorting.
+    * Collect properties of interest that we can potentially sort on.
+    * That includes the M value, critical parameter, additive value(s),
+    * and finally any parameter.  Keep these values and their slop.
+    * If there is a critical value, then sort on additive values * M.
+    * If not, then sort on M and additive values.
     */
 
    proplist = (propsort *)MALLOC(run * sizeof(propsort));
 
    obp = obn;
    mval = 1;
-   cval = aval = slop = 0.0;
+   pval = aval = oval = 0.0;
    for (i = 0; i < run; i++) {
+      has_crit = FALSE;
       merge_type = MERGE_NONE;
-      ml = NULL;
-      c = (char)0;
+      ca = co = (char)0;
+
       for (p = 0;; p++) {
 	 vl = &(obp->instance.props[p]);
 	 if (vl->type == PROP_ENDLIST) break;
 	 if (vl->key == NULL) continue;
          if ((*matchfunc)(vl->key, "M")) {
 	    mval = vl->value.ival;
-	    ml = vl;
+	    continue;
 	 }
          kl = (struct property *)HashLookup(vl->key, &(tp1->propdict));
 	 if (kl == NULL) continue;		/* Ignored property */
-         if (kl->merge & MERGE_P_CRIT)
-	    has_crit = TRUE;
-	 else if (kl->merge & (MERGE_P_ADD | MERGE_P_PAR)) {
-	    if ((vl->type == PROP_STRING || vl->type == PROP_EXPRESSION) &&
-		  	(kl->type != vl->type))
-		PromoteProperty(kl, vl, obp, tp1);
-	    if (vl->type == PROP_INTEGER) {
-	        tval = (double)vl->value.ival;
-	        tslop = (double)kl->slop.ival;
-	    }
-	    else if (vl->type == PROP_STRING) {
-		/* This is unlikely---no method to merge string properties! */
-		tval = (double)vl->value.string[0]
-			+ (double)vl->value.string[1] / 10.0;
-	        tslop = (double)0;
-	    }
-	    else {
-	        tval = vl->value.dval;
-	        tslop = kl->slop.dval;
-	    }
 
-	    if (merge_type == MERGE_NONE)
-	    {
-	       merge_type = kl->merge & (MERGE_P_ADD | MERGE_P_PAR);
-	       cval = tval;
-	       slop = tslop;
-	    }
-	    else {
-	       if ((c == (char)0) || (toupper(vl->key[0]) > c)) {
-		  c = toupper(vl->key[0]);
-		  aval = tval;
-	       }
-	    }
+	 /* Get the property value and slop.  Promote if needed.  Save	*/
+	 /* property and slop as type double so they can be sorted.	*/
+
+	 if ((vl->type == PROP_STRING || vl->type == PROP_EXPRESSION) &&
+		  	(kl->type != vl->type))
+	    PromoteProperty(kl, vl, obp, tp1);
+	 if (vl->type == PROP_INTEGER) {
+	    tval = (double)vl->value.ival;
+	    tslop = (double)kl->slop.ival;
+	 }
+	 else if (vl->type == PROP_STRING) {
+	    /* This is unlikely---no method to merge string properties! */
+	    tval = (double)vl->value.string[0]
+			+ (double)vl->value.string[1] / 10.0;
+	    tslop = (double)0;
 	 }
 	 else {
-	    if ((c == (char)0) || (toupper(vl->key[0]) > c)) {
-	       if (vl->type == PROP_INTEGER) {
-	           aval = (double)vl->value.ival;
-	           c = toupper(vl->key[0]);
-	       }
-	       else if (vl->type == PROP_DOUBLE) {
-	           aval = vl->value.dval;
-	           c = toupper(vl->key[0]);
-	       }
+	    tval = vl->value.dval;
+	    tslop = kl->slop.dval;
+	 }
+
+	 if (kl->merge & MERGE_P_CRIT) {
+	    has_crit = TRUE;
+	    pval = tval;
+	    pslop = tslop;
+	 }
+	 else if (kl->merge & (MERGE_P_ADD | MERGE_P_PAR)) {
+	    if ((ca == (char)0) || (toupper(vl->key[0]) > ca)) {
+	       merge_type = kl->merge & (MERGE_P_ADD | MERGE_P_PAR);
+	       aval = tval;
+	       aslop = tslop;
+	       ca = toupper(vl->key[0]);
 	    }
-         }
+	 }
+	 else if ((co == (char)0) || (toupper(vl->key[0]) > co)) {
+	    oval = tval;
+	    co = toupper(vl->key[0]);
+	 }
       }
-      if (merge_type == MERGE_P_ADD) {
-	 proplist[i].value = cval * (double)mval;
-	 proplist[i].avalue = aval;
-	 proplist[i].slop = tslop;
-	 if (ml) ml->value.ival = 1;
-      }
-      else if (merge_type == MERGE_P_PAR) {
-	 proplist[i].value = cval / (double)mval;
-	 proplist[i].avalue = aval;
-	 proplist[i].slop = tslop;
-	 if (ml) ml->value.ival = 1;
+      if (has_crit == TRUE) {
+	 /* If there is a critical value, then sort first   */
+	 /* by critical value				    */
+	 proplist[i].value = pval;
+	 proplist[i].slop = pslop;
+
+	 /* then sort on additive value times M	*/
+	 /* or on non-additive value.		*/
+         if (merge_type == MERGE_P_ADD)
+	    proplist[i].avalue = aval * (double)mval;
+         else if (merge_type == MERGE_P_PAR)
+	    proplist[i].avalue = aval / (double)mval;
+	 else
+	    proplist[i].avalue = (double)mval;
       }
       else {
-	 /* If there are no additive values, then sort first by M   */
-	 /* and second by aval					    */
-	 proplist[i].value = (double)mval;
-	 proplist[i].avalue = aval;
-	 proplist[i].slop = (double)0;
+         if (merge_type != MERGE_NONE) {
+	    proplist[i].value = aval;
+	    proplist[i].slop = aslop;
+	    proplist[i].avalue = (double)mval;
+	 }
+	 else {
+	    proplist[i].value = (double)mval;
+	    proplist[i].slop = (double)0;
+	    proplist[i].avalue = oval;
+	 }
       }
       proplist[i].idx = i;
       proplist[i].ob = obp;
@@ -4692,7 +4744,7 @@ int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run, int series,
    struct objlist *ob2, *obt;
    struct property *kl, *m_rec, **plist;
    unsigned char **clist;
-   struct valuelist ***vlist, *vl, *vl2, *newvlist;
+   struct valuelist ***vlist, *vl, *vl2, *newvlist, critval;
    proplinkptr plink, ptop;
    int pcount, p, i, j, k, pmatch, ival, ctype;
    double dval;
@@ -4780,12 +4832,12 @@ int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run, int series,
  	 else if (kl != NULL) {
 	    vlist[kl->idx][i] = vl;
 	    if (series == FALSE) {
-		if (kl->merge & (MERGE_P_ADD | MERGE_P_PAR))
+		if (kl->merge & (MERGE_P_ADD | MERGE_P_PAR | MERGE_P_CRIT))
 		    clist[kl->idx][i] = kl->merge &
 			    (MERGE_P_ADD | MERGE_P_PAR | MERGE_P_CRIT);
 	    }
 	    else if (series == TRUE) {
-		if (kl->merge & (MERGE_S_ADD | MERGE_S_PAR))
+		if (kl->merge & (MERGE_S_ADD | MERGE_S_PAR | MERGE_S_CRIT))
 		    clist[kl->idx][i] = kl->merge &
 			    (MERGE_S_ADD | MERGE_S_PAR | MERGE_S_CRIT);
 	    }
@@ -4940,24 +4992,44 @@ int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run, int series,
    // (if any)
 
    if (comb == TRUE) {
-      int mult;
+      int mult, cidx = -1;
+      struct valuelist *avl, *cvl = NULL;
+      critval.type = PROP_ENDLIST;
+      critval.value.dval = 0.0;
       for (i = 0; i < run; i++) {
+         avl = NULL;
 	 if (vlist[0][i] == NULL) continue;
 	 mult = vlist[0][i]->value.ival;
-	 if (mult > 1) {
-	    changed = 0;
+	 changed = 0;
 
-	    /* For all properties that are not M, S, or crit,		*/
-	    /* combine as specified by the merge type of the property.	*/
+	 /* For all properties that are not M, S, or crit,		*/
+	 /* combine as specified by the merge type of the property.	*/
 
-	    for (p = 1; p < pcount; p++) {
-		vl = vlist[p][i];
-		ctype = clist[p][i];
+	 for (p = 1; p < pcount; p++) {
+	    vl = vlist[p][i];
+	    ctype = clist[p][i];
 
-		/* critical properties never combine */
-		if ((series == TRUE) && (ctype & MERGE_S_CRIT)) continue;
-		if ((series == FALSE) && (ctype & MERGE_P_CRIT)) continue;
+	    /* critical properties never combine, but track them */
+	    if ((series == TRUE) && (ctype & MERGE_S_CRIT)) {
+		if ((vl->type != critval.type) || (vl->value.dval != critval.value.dval))
+		{
+		    critval.type = vl->type;
+		    critval.value = vl->value;
+		    cidx = i;
+		}
+		continue;
+	    }
+	    if ((series == FALSE) && (ctype & MERGE_P_CRIT)) {
+		if ((vl->type != critval.type) || (vl->value.dval != critval.value.dval))
+		{
+		    critval.type = vl->type;
+		    critval.value = vl->value;
+		    cidx = i;
+		}
+		continue;
+	    }
 
+	    if (mult > 1) {
 		if (ctype & (MERGE_S_ADD | MERGE_P_ADD)) {
 		    if (vl->type == PROP_INTEGER)
 			vl->value.ival *= mult;
@@ -4977,14 +5049,68 @@ int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run, int series,
 		    vlist[0][i]->value.ival = 1;
 		    changed += mult;
 		}
-		if (changed > 0) {
-		    if (series)
-			Printf("Combined %d series devices.\n", changed);
-		    else
-			Printf("Combined %d parallel devices.\n", changed);
+	    }
+	    if (ctype & (MERGE_S_ADD | MERGE_P_ADD | MERGE_S_PAR | MERGE_P_PAR))
+		avl = vl;
+         }
+	 if (cidx == i) cvl = avl;
+
+	 /* Sorting should have put all records with the same critical	*/
+	 /* value together sequentially.  So if there are still		*/
+	 /* multiple property records, then merge them into the first	*/
+	 /* record with the same critical property value.		*/
+
+	 if ((i > 0) && (cidx >= 0) && (cidx < i)) {
+	    for (p = 1; p < pcount; p++) {
+		vl = vlist[p][i];
+		ctype = clist[p][i];
+
+		if (ctype & (MERGE_S_ADD | MERGE_P_ADD)) {
+		    vlist[0][i]->value.ival = 0;	/* set M to 0 */
+		    if (cvl && (cvl->type == PROP_INTEGER))
+		    {
+			if (vl->type == PROP_INTEGER)
+			    cvl->value.ival += vl->value.ival;
+			else {
+			    cvl->type = PROP_DOUBLE;
+			    cvl->value.dval = (double)cvl->value.ival + vl->value.dval;
+			}
+		    }
+		    else if ((cvl && vl->type == PROP_DOUBLE))
+		    {
+			if (vl->type == PROP_INTEGER)
+			    cvl->value.dval += (double)vl->value.ival;
+			else
+			    cvl->value.dval += vl->value.dval;
+		    }
+		}
+		else if (ctype & (MERGE_S_PAR | MERGE_P_PAR)) {
+		    vlist[0][i]->value.ival = 0;    /* set M to 0 */
+		    /* To do parallel combination, both types need to
+		     * be double, so recast them if they are integer.
+		     */
+		    if (vl->type == PROP_INTEGER) {
+			vl->type = PROP_DOUBLE;
+			vl->value.dval = (double)(vl->value.ival);
+		    }
+		    if (cvl && (cvl->type == PROP_INTEGER)) {
+			cvl->type = PROP_DOUBLE;
+			cvl->value.dval = (double)cvl->value.ival;
+		    }
+		    if ((cvl && (vl->type == PROP_DOUBLE))) {
+		        cvl->value.dval =
+				sqrt(cvl->value.dval * cvl->value.dval
+				+ vl->value.dval * vl->value.dval);
+		    }
 		}
 	    }
-         }
+	 }
+	 if (changed > 0) {
+	    if (series)
+		Printf("Combined %d series devices.\n", changed);
+	    else
+		Printf("Combined %d parallel devices.\n", changed);
+	 }
       }
    }
 
@@ -5289,8 +5415,8 @@ PropertyCheckMismatch(struct objlist *tp1, struct nlist *tc1,
       }
 
       /* Promote properties as necessary to make sure they all match */
-      if (kl1->type != vl1->type) PromoteProperty(kl1, vl1, tc1, tp1);
-      if (kl2->type != vl2->type) PromoteProperty(kl2, vl2, tc2, tp2);
+      if (kl1->type != vl1->type) PromoteProperty(kl1, vl1, tp1, tc1);
+      if (kl2->type != vl2->type) PromoteProperty(kl2, vl2, tp2, tc2);
 
       /* If kl1 and kl2 types differ, choose one type to target. Prefer	*/
       /* double if either type is double, otherwise string.		*/
@@ -5310,8 +5436,8 @@ PropertyCheckMismatch(struct objlist *tp1, struct nlist *tc1,
       else
 	 klt = kl1;
 
-      if (vl2->type != klt->type) PromoteProperty(klt, vl2, tc2, tp2);
-      if (vl1->type != klt->type) PromoteProperty(klt, vl1, tc1, tp1);
+      if (vl2->type != klt->type) PromoteProperty(klt, vl2, tp2, tc2);
+      if (vl1->type != klt->type) PromoteProperty(klt, vl1, tp1, tc1);
 
       if (vl1->type != vl2->type) {
 	 if (do_print && (vl1->type != vl2->type)) {
@@ -5590,10 +5716,10 @@ PropertyMatch(struct objlist *ob1, int file1,
 		int do_print, int do_list, int *retval)
 {
    struct nlist *tc1, *tc2;
-   struct objlist *tp1, *tp2, *obn1, *obn2;
+   struct objlist *tp1, *tp2, *obn1, *obn2, *tpc;
    struct property *kl1, *kl2;
    struct valuelist *vl1, *vl2;
-   int t1type, t2type;
+   int t1type, t2type, run1, run2;
    int i, mismatches = 0, checked_one;
    int rval = 1;
    char *inst1, *inst2;
@@ -5686,13 +5812,12 @@ PropertyMatch(struct objlist *ob1, int file1,
 #endif
    }
 
-   /* WIP---Check for no-connect pins in merged devices on both sides.	*/
+   /* Check for no-connect pins in merged devices on both sides.	*/
    /* Both sides should either have no-connects marked, or neither.	*/
    /* (Permutable pins may need to be handled correctly. . .		*/
 
    for (tp1 = ob1, tp2 = ob2; (tp1 != NULL) && tp1->type >= FIRSTPIN &&
-	    (tp2 != NULL) && tp2->type >= FIRSTPIN; tp1 = tp1->next, tp2 = tp2->next)
-   {
+	    (tp2 != NULL) && tp2->type >= FIRSTPIN; tp1 = tp1->next, tp2 = tp2->next) {
       struct objlist *node1, *node2;
 
       if (file1 == Circuit1->file)
@@ -5705,17 +5830,20 @@ PropertyMatch(struct objlist *ob1, int file1,
       else
          node2 = Circuit2->nodename_cache[tp2->node];
 
-      if (node1->instance.flags != node2->instance.flags)
-      {
+      /* NOTE: A "no-connect" node (multiple no-connects represented by a
+       * single node) has non-zero flags.  A non-node entry in the cache
+       * implies a node with zero flags.
+       */
+      if (node1->flags != node1->flags) {
 	 Fprintf(stdout, "  Parallelized instances disagree on pin connections.\n");
 	 Fprintf(stdout, "    Circuit1 instance %s pin %s connections are %s (%d)\n",
 		    tp1->instance.name, node1->name,
-		    (node1->instance.flags == 0) ? "tied together" : "no connects",
-		    node1->instance.flags);
+		    (node1->flags == 0) ? "tied together" : "no connects",
+		    node1->flags);
 	 Fprintf(stdout, "    Circuit2 instance %s pin %s connections are %s (%d)\n",
 		    tp2->instance.name, node2->name,
-		    (node2->instance.flags == 0) ? "tied together" : "no connects",
-		    node2->instance.flags);
+		    (node2->flags == 0) ? "tied together" : "no connects",
+		    node2->flags);
 	 mismatches++;
       }
    }
@@ -5741,10 +5869,12 @@ PropertyMatch(struct objlist *ob1, int file1,
       if ((t1type != PROPERTY) && (checked_one == TRUE)) {
 	 // t2 has more property records than t1, and they did not get
 	 // merged equally by PropertySortAndCombine().
-	 Fprintf(stdout, "Circuit 1 parallel/series network does not match"
+	 if (do_print) {
+	    Fprintf(stdout, "Circuit 1 parallel/series network does not match"
 			" Circuit 2\n");
-	 DumpNetwork(ob1, 1);
-	 DumpNetwork(ob2, 2);
+	    DumpNetwork(ob1, 1);
+	    DumpNetwork(ob2, 2);
+	 }
 	 mismatches++;
       }
       else if (t1type != PROPERTY) {
@@ -5846,13 +5976,19 @@ PropertyMatch(struct objlist *ob1, int file1,
 			inst2, FALSE, FALSE, &multmatch, NULL);
 	 if (multmatch == 1) {
 	    /* Final attempt:  Reduce M to 1 on both devices */
-	    PropertyOptimize(tp1, tc1, 1, FALSE, TRUE);
-	    PropertyOptimize(tp2, tc2, 1, FALSE, TRUE);
+	    run1 = run2 = 0;
+	    for (tpc = tp1; tpc && (tpc->type == PROPERTY); tpc = tpc->next) run1++;
+	    for (tpc = tp2; tpc && (tpc->type == PROPERTY); tpc = tpc->next) run2++;
+	    PropertyOptimize(tp1, tc1, run1, FALSE, TRUE);
+	    PropertyOptimize(tp2, tc2, run2, FALSE, TRUE);
 	 }
 	 else if (multmatch == 2) {
 	    /* Final attempt:  Reduce S to 1 on both devices */
-	    PropertyOptimize(tp1, tc1, 1, TRUE, TRUE);
-	    PropertyOptimize(tp2, tc2, 1, TRUE, TRUE);
+	    run1 = run2 = 0;
+	    for (tpc = tp1; tpc && (tpc->type == PROPERTY); tpc = tpc->next) run1++;
+	    for (tpc = tp2; tpc && (tpc->type == PROPERTY); tpc = tpc->next) run2++;
+	    PropertyOptimize(tp1, tc1, run1, TRUE, TRUE);
+	    PropertyOptimize(tp2, tc2, run2, TRUE, TRUE);
 	 }
 #ifdef TCL_NETGEN
 	 mlist =
@@ -6817,6 +6953,7 @@ int reorderpins(struct hashlist *p, int file)
 		        nodes[ob2->model.port] = ob->node;
 		        names[ob2->model.port] = ob->name;
 		    }
+
 		    ob = ob->next;
 		    ob2 = ob2->next;
 		    if (i < numports - 1) {
@@ -7126,8 +7263,13 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 			      snprintf(ostr, left_col_end, "%s", obn->name);
 			      if ((*matchfunc)(obn->name, obp->name))
 			         snprintf(ostr + left_col_end + 1, left_col_end, "%s", obp->name);
-			      else
+			      else {
 			         snprintf(ostr + left_col_end + 1, left_col_end, "%s **Mismatch**", obp->name);
+				 /* Pins with different names are on different nets,
+				  * so this should trigger an error return code.
+				  */
+				 result = 0;
+			      }
 			      for (m = 0; m < right_col_end + 1; m++)
 				 if (*(ostr + m) == '\0') *(ostr + m) = ' ';
 			      Fprintf(stdout, ostr);
@@ -7235,8 +7377,9 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
       }
    }
 
-   /* Do any unmatched pins have the same name? 		  */
-   /* (This should not happen if unconnected pins are eliminated) */
+   /* Do any unmatched pins have the same name? 		*/
+   /* This should not happen if unconnected pins are eliminated	*/
+   /* so apply only to black-box (CELL_PLACEHOLDER) entries.	*/ 
    /* (Semi-hack: Allow "!" global flag) */
 
    ob1 = tc1->cell;
@@ -7261,45 +7404,59 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 	    name1 = ob1->name;
 	    name2 = ob2->name;
 
-	    /* Recognize proxy pins as matching */
-	    if (!strncmp(name1, "proxy", 5)) name1 +=5;
-	    if (!strncmp(name2, "proxy", 5)) name2 +=5;
+	    /* Recognize proxy pins as matching unconnected pins */
+	    if (!strncmp(name1, "proxy", 5) && (ob2->node == -1)) name1 +=5;
+	    if (!strncmp(name2, "proxy", 5) && (ob1->node == -1)) name2 +=5;
 
 	    if ((*matchfunc)(name1, name2)) {
-	       ob2->model.port = i;		/* save order */
-	       *(cover + i) = (char)1;
 
-	       if (Debug == 0) {
-		  for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
-		  for (m = left_col_end + 1; m < right_col_end; m++) *(ostr + m) = ' ';
-		  snprintf(ostr, left_col_end, "%s", ob1->name);
-		  snprintf(ostr + left_col_end + 1, left_col_end, "%s", ob2->name);
-		  for (m = 0; m < right_col_end + 1; m++)
-		     if (*(ostr + m) == '\0') *(ostr + m) = ' ';
-		  Fprintf(stdout, ostr);
-	       }
-	       else {
-		  Fprintf(stdout, "Circuit %s port %d \"%s\""
+	       /* If both sides have unconnected nodes, then pins with	*/
+	       /* matching names are an automatic match.  Otherwise, if	*/
+	       /* matching black-box entries, then pins are always	*/
+	       /* matched by name.					*/
+
+	       if (((ob1->node == -1) && (ob2->node == -1)) ||
+			(((tc1->flags & CELL_PLACEHOLDER) &&
+			(tc2->flags & CELL_PLACEHOLDER)) ||
+			(NodeClasses == NULL))) {
+
+	          ob2->model.port = i;		/* save order */
+	          *(cover + i) = (char)1;
+
+	          if (Debug == 0) {
+		     for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
+		     for (m = left_col_end + 1; m < right_col_end; m++) *(ostr + m) = ' ';
+		     snprintf(ostr, left_col_end, "%s", ob1->name);
+		     snprintf(ostr + left_col_end + 1, left_col_end, "%s", ob2->name);
+		     for (m = 0; m < right_col_end + 1; m++)
+		        if (*(ostr + m) == '\0') *(ostr + m) = ' ';
+		     Fprintf(stdout, ostr);
+	          }
+	          else {
+		     Fprintf(stdout, "Circuit %s port %d \"%s\""
 				" = cell %s port %d \"%s\"\n",
 				tc1->name, i, ob1->name,
 				tc2->name, j, ob2->name);
-	       }
+	          }
 #ifdef TCL_NETGEN
-	       if (dolist) {
-		  Tcl_ListObjAppendElement(netgeninterp, plist1,
+	          if (dolist) {
+		     Tcl_ListObjAppendElement(netgeninterp, plist1,
 				Tcl_NewStringObj(ob1->name, -1));
-		  Tcl_ListObjAppendElement(netgeninterp, plist2,
+		     Tcl_ListObjAppendElement(netgeninterp, plist2,
 				Tcl_NewStringObj(ob2->name, -1));
-	       }
+	          }
 #endif
+	          if (bangptr2) *bangptr2 = '!';
+		  break;
+	       }
 	    }
 	    if (bangptr2) *bangptr2 = '!';
 	    j++;
-	 }
+         }
       }
       ob1 = ob1->next;
+      if (bangptr1) *bangptr1 = '!';
    }
-   if (bangptr1) *bangptr1 = '!';
 
    /* Find the end of the pin list in tc1, for adding proxy pins */
 
@@ -7333,15 +7490,6 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 	    Fprintf(stderr, "No netlist match for cell %s pin %s\n",
 				tc2->name, ob2->name);
 	 }
-#ifdef TCL_NETGEN
-         if (dolist) {
-	    Tcl_ListObjAppendElement(netgeninterp, plist1,
-			Tcl_NewStringObj("(no matching pin)", -1));
-	    Tcl_ListObjAppendElement(netgeninterp, plist2,
-			Tcl_NewStringObj(ob2->name, -1));
-         }
-#endif
-	 result = 0;
 
 	 /* Before making a proxy pin, check to see if	*/
 	 /* flattening instances has left a port with a	*/
@@ -7358,8 +7506,34 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 	 if ((obt == NULL) && (notempty == 1)) {
 	    ob2->node = -2;	// Will run this through cleanuppins
 	    needclean2 = 1;
+
+	    /* On the top level, missing pins are an error, even if	*/
+	    /* they appear to match unconnected pins on the other side. */
+	    if (CompareQueue == NULL)
+		result = 0;
+
+#ifdef TCL_NETGEN
+            if (dolist) {
+	       Tcl_ListObjAppendElement(netgeninterp, plist1,
+			Tcl_NewStringObj("(no pin)", -1));
+	       Tcl_ListObjAppendElement(netgeninterp, plist2,
+			Tcl_NewStringObj(ob2->name, -1));
+            }
+#endif
 	    continue;
 	 }
+	 else if (notempty == 1) {
+	    /* Flag this as an error */
+	    result = 0;
+#ifdef TCL_NETGEN
+            if (dolist) {
+	       Tcl_ListObjAppendElement(netgeninterp, plist1,
+			Tcl_NewStringObj("(no matching pin)", -1));
+	       Tcl_ListObjAppendElement(netgeninterp, plist2,
+			Tcl_NewStringObj(ob2->name, -1));
+            }
+#endif
+	 }
 	 ob2->model.port = numnodes++;	// Assign a port order
 
 	 /* Add a proxy pin to tc1 */
@@ -7425,7 +7599,8 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
       }
 
       if (ob1 == NULL || ob1->type != PORT || ob1->node >= 0
-		|| (ob1->node < 0 && tc1->class == CLASS_MODULE)) {
+		|| (ob1->node < 0 && tc1->class == CLASS_MODULE)
+		|| (ob1->node < 0 && ob1->model.port == -1)) {
 
 	 /* Add a proxy pin to tc2 */
          obn = (struct objlist *)CALLOC(1, sizeof(struct objlist));
@@ -7442,8 +7617,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
          obn->instance.name = NULL;
          obn->node = -1;
 
-#if 0
-	 /* Note:  This pin has already been accounted for */
+	 /* Note:  Has this pin already been accounted for? */
 	 if (Debug == 0) {
 	    if (strcmp(ob1->name, "(no pins)")) {
 	       for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
@@ -7459,7 +7633,6 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 	    Fprintf(stderr, "No netlist match for cell %s pin %s\n",
 				tc1->name, ob1->name);
 	 }
-#endif
 
 	 if (ob2 == tc2->cell) {
 	    obn->next = ob2;
@@ -7772,6 +7945,7 @@ int Compare(char *cell1, char *cell2)
 {
   int automorphisms;
 
+  DescribeContents(cell1, -1, cell2, -1);
   CreateTwoLists(cell1, -1, cell2, -1, 0);
   Permute();
   while (!Iterate()); 
@@ -7832,6 +8006,7 @@ void NETCOMP(void)
     case 'c':
       promptstring("Enter cell 1: ",name);
       promptstring("Enter cell 2: ",name2);
+      DescribeContents(name, -1, name2, -1);
       CreateTwoLists(name, -1, name2, -1, 0);
 #ifdef DEBUG_ALLOC
       PrintCoreStats();

base/netcmp.h

@@ -26,6 +26,7 @@ extern void PrintCoreStats(void);
 extern void ResetState(void);
 extern void CreateTwoLists(char *name1, int file1, char *name2, int file2,
 		int dolist);
+extern void DescribeContents(char *name1, int file1, char *name2, int file2);
 extern int Iterate(void);
 extern int VerifyMatching(void);
 extern void PrintAutomorphisms(void);
@@ -46,6 +47,7 @@ extern int  CreateCompareQueue(char *, int, char *, int);
 extern int  GetCompareQueueTop(char **, int *, char **, int *);
 extern int  PeekCompareQueueTop(char **, int *, char **, int *);
 extern void RemoveCompareQueue();
+extern int FlattenUnmatched(struct nlist *, char *, int, int);
 
 extern void PrintIllegalClasses();
 extern void PrintIllegalNodeClasses();
@@ -54,6 +56,15 @@ extern void PrintIllegalElementClasses();
 extern void DumpNetwork(struct objlist *ob, int cidx);
 extern void DumpNetworkAll(char *name, int file);
 
+extern void RegroupDataStructures();
+extern void FormatIllegalElementClasses();
+extern void FormatIllegalNodeClasses();
+extern int ResolveAutomorphsByProperty();
+extern int ResolveAutomorphsByPin();
+extern void SummarizeElementClasses(struct ElementClass *EC);
+extern int remove_group_tags(struct objlist *ob);
+
+
 #ifdef TCL_NETGEN
 extern int EquivalentNode();
 extern int EquivalentElement();

base/netfile.c

@@ -896,7 +896,9 @@ char *ReadNetlist(char *fname, int *fnum)
 
   /* make first pass looking for extension */
   for (index = 0; formats[index].extension != NULL; index++) {
-    if (strstr(fname, formats[index].extension) != NULL) {
+    int extlen = strlen(formats[index].extension);
+    int flen = strlen(fname);
+    if (!strcmp(fname + flen - extlen, formats[index].extension)) {
       return (*(formats[index].proc))(fname, fnum);
     }
   }

base/netgen.c

@@ -1352,7 +1352,8 @@ void Node(char *name)
 	tp->name = strsave(name);
 	tp->type = NODE;  /* internal node type */
 	tp->model.class = NULL;
-	tp->instance.flags = 0;
+	tp->instance.name = NULL;
+	tp->flags = 0;
 	tp->node = -1;  /* null node */
 	tp->next = NULL;
 	AddToCurrentCell (tp);
@@ -3259,7 +3260,7 @@ int CombineParallel(char *model, int file)
 	    if ((ob2->node >= 0) && (nodecount[ob2->node] == 1))
 	    {
 	       nob = (tp->nodename_cache)[ob2->node];
-	       nob->instance.flags = NO_CONNECT;
+	       nob->flags = NO_CONNECT;
 	       strcat(pptr, "_nc");
 	    }
 	    else
@@ -3440,7 +3441,7 @@ int CombineParallel(char *model, int file)
    }
    HashKill(&devdict);
    if (dcnt > 0) {
-      Fprintf(stdout, "Class %s:  Merged %d devices.\n", model, dcnt);
+      Fprintf(stdout, "Class %s(%d):  Merged %d parallel devices.\n", model, file, dcnt);
    }
    FREE(nodecount);
    return dcnt;
@@ -3737,6 +3738,9 @@ int CombineSeries(char *model, int file)
       }
    }
    FREE(instlist);
+   if (scnt > 0) {
+      Fprintf(stdout, "Class %s(%d):  Merged %d series devices.\n", model, file, scnt);
+   }
    return scnt;
 }
 

base/objlist.c

@@ -22,6 +22,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 #include <stdio.h>
 #include <ctype.h>
+#include <limits.h>
 #ifdef IBMPC
 #include <alloc.h>
 #endif
@@ -31,13 +32,13 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #endif
 
 #include "netgen.h"
-#include "hash.h"
 #include "objlist.h"
 #include "regexp.h"
 #include "dbug.h"
 #include "print.h"
 #include "netfile.h"
 #include "netcmp.h"
+#include "hash.h"
 
 #ifdef TCL_NETGEN
 extern Tcl_Interp *netgeninterp;
@@ -288,7 +289,7 @@ static struct hashdict cell_dict;
 
 void InitCellHashTable(void)
 {
-    hashfunc = hash;
+    hashfunc = hashcase;
     matchfunc = NULL;
     matchintfunc = matchfile;
     InitializeHashTable(&cell_dict, CELLHASHSIZE);
@@ -975,10 +976,8 @@ struct objlist *CopyObjList(struct objlist *oldlist, unsigned char doforall)
           newob->model.class = NULL;
        else
           newob->model.class = strsave(tmp->model.class);
-       if (newob->type == NODE)
-	  newob->instance.flags = tmp->instance.flags;
-       else
-          newob->instance.name = (tmp->instance.name) ?
+       newob->flags = tmp->flags;
+       newob->instance.name = (tmp->instance.name) ?
 		strsave(tmp->instance.name) : NULL;
     }
     newob->node = tmp->node;
@@ -1098,8 +1097,8 @@ void FreeObject(struct objlist *ob)
 	FREE(ob->instance.props);
      }
   }
-  else if (ob->type != NODE) {
-     /* All other records except NODE, which uses this for flags */
+  else {
+     /* All other records */
      if (ob->instance.name != NULL) FreeString(ob->instance.name);
   }
   if (ob->model.class != NULL) FreeString(ob->model.class);

base/objlist.h

@@ -162,9 +162,9 @@ struct objlist {
   union {
      char *name;		/* unique name for the instance, or */
 				/* (string) value of property for properties */
-     int  flags;		/* Used by NODE type to flag isolated net */
      struct valuelist *props;	/* Property record */
   } instance;
+  unsigned char flags;	/* Used by NODE type to flag isolated net */
   int node;		/* the electrical node number of the port/node/pin */
   struct objlist *next;
 };
@@ -312,6 +312,19 @@ extern void GarbageCollect(void);
 extern void InitGarbageCollection(void);
 extern void AddToGarbageList(struct objlist *head);
 
+extern void DeleteProperties(struct keyvalue **topptr);
+extern void AddProperty(struct keyvalue **topptr, char *key, char *value);
+extern void AddScaledProperty(struct keyvalue **topptr, char *key, char *value, double scale);
+extern void DeleteProperties(struct keyvalue **topptr);
+extern struct objlist *LinkProperties(char *model, struct keyvalue *topptr);
+
+extern void ClassDelete(char *class, int file);
+extern void RemoveShorted(char *class, int file);
+extern void CellRehash(char *name, char *newname, int file);
+
+/* defined in netgen.c */
+extern int ConvertStringToInteger(char *string, int *ival);
+
 #ifdef HAVE_MALLINFO
 void PrintMemoryStats(void);
 #endif

base/query.c

@@ -805,11 +805,13 @@ void DescribeInstance(char *name, int file)
       /* All black-box modules and placeholders by definition have all	*/
       /* disconnected pins, so don't report those.			*/
 
-      if (!(tp->flags & CELL_PLACEHOLDER) && (tp->class != CLASS_MODULE))
-      {
-	if (disconnectednodes == 0) Fprintf(stderr, "\n");
+      if ((!(tp->flags & CELL_PLACEHOLDER)) && (tp->class != CLASS_MODULE)) {
+	// if (disconnectednodes == 0) Fprintf(stderr, "\n");
         disconnectednodes++;
-        Fprintf(stderr, "Cell %s disconnected node: %s\n", tp->name, ob->name);
+	/* Don't report on ports marked "port_match_error", which is just confusing. */
+	if (strcmp(ob->name, "port_match_error")) {
+           Fprintf(stderr, "Cell %s(%d) disconnected node: %s\n", tp->name, tp->file, ob->name);
+	}
       }
     }
   }
@@ -1033,7 +1035,7 @@ void Query(void)
       break;
     case 'v':
       promptstring("Write Verilog: circuit name: ", repstr);
-      VerilogModule(repstr, filenum, "");
+      VerilogTop(repstr, filenum, "");
       break;
     case 'E':
       promptstring("Write ESACAP: circuit name: ", repstr);

base/spice.c

@@ -26,6 +26,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #endif
 
 #include <stdlib.h>  /* for calloc(), free(), getenv() */
+#include <ctype.h>  /* for toupper(), isascii() */
 #ifndef IBMPC
 #include <sys/types.h>	/* for getpwnam() tilde expansion */
 #include <pwd.h>
@@ -40,6 +41,8 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include "objlist.h"
 #include "netfile.h"
 #include "print.h"
+#include "query.h"
+#include "objlist.h"
 
 // Global storage for parameters from .PARAM
 struct hashdict spiceparams;
@@ -937,7 +940,7 @@ skip_ends:
 	 goto baddevice;
       }
 
-      snprintf(instname, 255, "%s%s", model, inst);
+      snprintf(instname, 255, "%s:%s", model, inst);
       Cell(instname, model, collector, base, emitter);
       pobj = LinkProperties(model, kvlist);
       ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
@@ -1010,7 +1013,7 @@ skip_ends:
 	 goto baddevice;
       }
 
-      snprintf(instname, 255, "%s%s", model, inst);
+      snprintf(instname, 255, "%s:%s", model, inst);
       Cell(instname, model, drain, gate, source, bulk);
       pobj = LinkProperties(model, kvlist);
       ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
@@ -1101,7 +1104,7 @@ skip_ends:
 	   usemodel = 1;
 	}
 
-	snprintf(instname, 255, "%s%s", model, inst);
+	snprintf(instname, 255, "%s:%s", model, inst);
 	if (usemodel)
            Cell(instname, model, ctop, cbot);
 	else
@@ -1194,7 +1197,7 @@ skip_ends:
 	else
 	   strcpy(model, "r");		/* Use default resistor model */
 
-	snprintf(instname, 255, "%s%s", model, inst);
+	snprintf(instname, 255, "%s:%s", model, inst);
 	if (usemodel)
 	   Cell(instname, model, rtop, rbot);
 	else
@@ -1252,7 +1255,7 @@ skip_ends:
 	 Fprintf(stderr, "Device \"%s\" has wrong number of ports for a diode.\n");
 	 goto baddevice;
       }
-      snprintf(instname, 255, "%s%s", model, inst);
+      snprintf(instname, 255, "%s:%s", model, inst);
       Cell(instname, model, anode, cathode);
       pobj = LinkProperties(model, kvlist);
       ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
@@ -1331,7 +1334,7 @@ skip_ends:
 	else
 	   strcpy(model, "t");		/* Use default xline model */
 
-	snprintf(instname, 255, "%s%s", model, inst);
+	snprintf(instname, 255, "%s:%s", model, inst);
 
 	if (usemodel)
 	   Cell(instname, model, node1, node2, node3, node4);
@@ -1414,7 +1417,7 @@ skip_ends:
       else
 	 strcpy(model, "l");		/* Use default inductor model */
 
-      snprintf(instname, 255, "%s%s", model, inst);
+      snprintf(instname, 255, "%s:%s", model, inst);
       if (usemodel)
 	 Cell(instname, model, end_a, end_b);
       else
@@ -1726,7 +1729,7 @@ skip_ends:
       /* names.								  */
 
       if (strncmp(instancename, scan->name, strlen(scan->name))) {
-         snprintf(subcktname, 99, "%s%s", scan->name, instancename);
+         snprintf(subcktname, 99, "%s:%s", scan->name, instancename);
          strcpy(instancename, subcktname);
       }
       else {

base/tech.h

@@ -0,0 +1,8 @@
+#ifndef _TECH_H
+#define _TECH_H
+
+extern int ActelLibPresent(void);
+extern void ActelLib(void);
+extern void VerilogTop(char *name, int fnum, char *filename);
+
+#endif /* _TECH_H */

base/verilog.c

@@ -52,10 +52,10 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #endif
 
 #include "netgen.h"
-#include "hash.h"
 #include "objlist.h"
 #include "netfile.h"
 #include "print.h"
+#include "hash.h"
 
 // See netfile.c for explanation of delimiters.  'X'
 // separates single-character delimiters from two-character delimiters.
@@ -63,6 +63,10 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #define VLOG_PIN_NAME_DELIMITERS "X///**/(**)X()"
 #define VLOG_PIN_CHECK_DELIMITERS "X///**/(**)X,;(){}"
 
+// Used by portelement structure "flags" record.
+#define PORT_NOT_FOUND	0
+#define PORT_FOUND	1
+
 // Global storage for verilog parameters
 struct hashdict verilogparams;
 // Global storage for verilog definitions
@@ -1404,6 +1408,7 @@ skip_endmodule:
 	char *name;	// Name of port in subcell
 	char *net;	// Name of net connecting to port in the parent
 	int   width;	// Width of port, if port is a bus
+	char  flags;	// Used for marking if port was added into netlist
 	struct portelement *next;
       };
 
@@ -1530,6 +1535,7 @@ nextinst:
 	       new_port = (struct portelement *)CALLOC(1, sizeof(struct portelement));
 	       new_port->name = strsave(nexttok + 1);
 	       new_port->width = -1;
+	       new_port->flags = PORT_NOT_FOUND;
 	       SkipTokComments(VLOG_DELIMITERS);
 	       if (!match(nexttok, "(")) {
 	           Printf("Badly formed subcircuit pin line at \"%s\"\n", nexttok);
@@ -1571,6 +1577,14 @@ nextinst:
 		     }
 		     new_port->net = wire_bundle;
 		  }
+		  else if (nexttok[0] == '~' || nexttok[0] == '!' || nexttok[0] == '-') {
+		     /* All of these imply that the signal is logically manipulated */
+		     /* in turn implying behavioral code.			    */
+		     Printf("Module '%s' is not structural verilog, "
+				    "making black-box.\n", model);
+		     SetClass(CLASS_MODULE);
+		     goto skip_endmodule;
+		  }
 		  else
 		     new_port->net = strsave(nexttok);
 
@@ -1764,54 +1778,6 @@ nextinst:
 	    scan->width = width;
 
 	    result = GetBus(scan->net, &wb);
-	    if (result == -1) {
-		/* CHECK:  THIS CODE SHOULD BE DELETED, IT IS NOT THE ISSUE */
-		/* Not bus notation, but check if signal was defined as a bus */
-		wb.start = wb.end = -1;
-		minnet = maxnet = -1;
-
-		/* Pins should be in index order start->end.  Other nodes */
-		/* should be in order start->end by node number.	  */
-
-		for (bobj = CurrentCell->cell; bobj; bobj = bobj->next) {
-		    if (bobj->type == PORT) {
-			if ((bptr = strvchr(bobj->name, '[')) != NULL) {
-			    *bptr = '\0';
-			    if (!strcmp(bobj->name, scan->net)) {
-				*bptr = '[';
-				if (wb.start == -1)
-				    sscanf(bptr + 1, "%d", &wb.start);
-				else
-				    sscanf(bptr + 1, "%d", &wb.end);
-			    }
-			}
-		    }
-		    else if (bobj->type == NODE) {
-			if ((bptr = strvchr(bobj->name, '[')) != NULL) {
-			    *bptr = '\0';
-			    if (!strcmp(bobj->name, scan->net)) {
-				if (sscanf(bptr + 1, "%d", &testidx) == 1) {
-				    if (minnet == -1) {
-					minnet = maxnet = bobj->node;
-					wb.start = wb.end = testidx;
-				    }
-				    else if (bobj->node < minnet) {
-					minnet = bobj->node;
-					wb.start = testidx;
-				    }
-				    else if (bobj->node > maxnet) {
-					maxnet = bobj->node;
-					wb.end = testidx;
-				    }
-				}
-			    }
-			    *bptr = '[';
-			}
-		    }
-		}
-		if (wb.start != -1) result = 0;
-	    }
-
 	    if (result == 0) {
 	       int match = 0;
 	       int wblen, arraylen;
@@ -1921,7 +1887,25 @@ nextinst:
 	       }
 	    }
 	    else if (portstart != portend) {
-	       Fprintf(stderr, "Error:  Single net %s is connected to bus port %s\n",
+	       /* If the name starts with "_noconnect_", then it was an
+		* auto-generated name that incorrectly assumed a single-bit
+		* wide signal because it did not have a module prototype.
+		* Rewrite the noconnect name as an array.  This just means
+		* that the verilog had an empty list "()" and the initial
+		* assumption was wrong.  If not all instances agree on the
+		* size, then this will eventually generate an error.
+		*/
+	       if (!strncmp(scan->net, "_noconnect_", 11) &&
+			(strchr(scan->net, '\[') == NULL) && (width > 1)) {
+		  char *savenet = scan->net;
+		  char *newnet = MALLOC(strlen(scan->net) + 12);
+		  sprintf(newnet, "%s[%d:0]", scan->net, scan->width - 1);
+		  FREE(savenet);
+		  scan->net = newnet;
+		  continue;	/* Re-process this entry */
+	       }
+	       else
+	          Fprintf(stderr, "Error:  Single net %s is connected to bus port %s\n",
 			scan->net, scan->name);
 	    }
 	 }
@@ -1964,6 +1948,7 @@ nextinst:
 	       obpinidx = -1;
 	       while (scan != NULL) {
 		  if (match(obpinname, scan->name)) {
+		     scan->flags |= PORT_FOUND;
 		     break;
 		  }
 		  scan = scan->next;
@@ -2056,6 +2041,89 @@ nextinst:
 	           if (LookupObject(scan->net, CurrentCell) == NULL) Node(scan->net);
 	           join(scan->net, obptr->name);
 	       }
+
+	       /* Before exiting the loop, check if all ports in the	*/
+	       /* scan list were handled.				*/
+
+	       if ((obptr->next == NULL) || (obptr->next->type <= FIRSTPIN)) {
+	          for (scan = head; scan; scan = scan->next) {
+	             if (!(scan->flags & PORT_FOUND)) {
+		        if (tp->flags & CELL_PLACEHOLDER) {
+			   char tempname[128];
+			   int maxnode;
+
+		           /* This pin was probably implicit in the first call */
+		           /* and so it needs to be added to the definition.	 */
+
+			   ReopenCellDef(modulename, filenum);
+		           Port(scan->name);
+			   ReopenCellDef((*CellStackPtr)->cellname, filenum);
+
+			   /* obptr->next now gets the new port.  Update the	*/
+			   /* port number, and copy class and instance name.	*/
+			   nobj = GetObject();
+			   sprintf(tempname, "%s%s%s", obptr->instance.name,
+						SEPARATOR, scan->name);
+			   nobj->name = strsave(tempname);
+			   nobj->model.class = strsave(obptr->model.class);
+			   nobj->instance.name = strsave(obptr->instance.name);
+			   nobj->type = obptr->type + 1;
+			   nobj->next = obptr->next;
+			   nobj->node = -1;
+			   obptr->next = nobj;
+      			   HashPtrInstall(nobj->name, nobj, &(CurrentCell->objdict));
+
+	           	   if (LookupObject(scan->net, CurrentCell) == NULL)
+			      Node(scan->net);
+	           	   join(scan->net, nobj->name);
+	             	   scan->flags |= PORT_FOUND;
+
+			   /* Now any previous instance of the same cell must	*/
+			   /* insert the same additional pin as a no-connect.	*/
+			   /* NOTE:  This should be running a callback on all	*/
+			   /* cells in the file, not just CurrentCell.		*/
+
+			   for (sobj = CurrentCell->cell; sobj && (sobj != obptr);
+					sobj = sobj->next) {
+			      if (sobj->type == FIRSTPIN) {
+				 if (match(sobj->model.class, obptr->model.class)) {
+				    while (sobj->next && (sobj->next->type > FIRSTPIN))
+				       sobj = sobj->next;
+				    /* Stop when reaching the current instance */
+				    if (sobj->type == obptr->type + 1) break;
+				    nobj = GetObject();
+				    sprintf(tempname, "%s%s%s", sobj->instance.name,
+						SEPARATOR, scan->name);
+				    nobj->name = strsave(tempname);
+				    nobj->model.class = strsave(sobj->model.class);
+				    nobj->instance.name = strsave(sobj->instance.name);
+				    nobj->type = obptr->type + 1;
+				    nobj->node = -1;
+				    nobj->next = sobj->next;
+				    sobj->next = nobj;
+      				    HashPtrInstall(nobj->name, nobj,
+							&(CurrentCell->objdict));
+
+		  	   	    sprintf(tempname, "_noconnect_%d_", localcount++);
+		  	   	    Node(tempname);
+		  	   	    join(tempname, nobj->name);
+		  	   	    Fprintf(stderr, "Note:  Implicit pin %s in instance "
+						"%s of %s in cell %s\n",
+			 			scan->name, sobj->instance.name,
+						modulename, CurrentCell->name);
+				 }
+			      }
+			   }
+		        }
+		        else {
+		           Fprintf(stderr, "Error:  Instance %s has pin %s which is "
+					"not in the %s cell definition.\n",
+					locinst, scan->name, modulename);
+		        }
+	             }
+	          }
+	       }
+
 	       obptr = obptr->next;
             } while (obptr != NULL && obptr->type > FIRSTPIN);
 	 }
@@ -2141,7 +2209,7 @@ char *ReadVerilogTop(char *fname, int *fnum, int blackbox)
   else {
      matchfunc = match;
      matchintfunc = matchfile;
-     hashfunc = hash;
+     hashfunc = hashcase;
   }
 
   InitializeHashTable(&verilogparams, OBJHASHSIZE);

base/xilinx.c

@@ -23,6 +23,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include <stdio.h>
 #include <stdarg.h>
 #include <ctype.h>
+#include <time.h>
 
 #ifdef IBMPC
 #include <stdlib.h>  /* for strtol on PC */
@@ -33,6 +34,8 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include "netfile.h"
 #include "hash.h"
 #include "print.h"
+#include "xilinx.h"
+#include "flatten.h"
 
 #define XILINXHASHSIZE 99
 static long xilinxhashbase = 0xA00;
@@ -132,10 +135,8 @@ char *xilinx_class(model)
 	}
 	return(model);
 }
-void
-Xilinx(cellname, filename)
-	char *cellname;
-	char *filename;
+
+void Xilinx(char *cellname, char *filename)
 {
 	char Path[500];
 	char FileName[500];
@@ -163,8 +164,7 @@ Xilinx(cellname, filename)
 	CloseFile(FileName);
 }
 
-xilinxCell(cell)
-	char *cell;
+int xilinxCell(char *cell)
 {
 	struct nlist *nl;
 	struct objlist *ob;
@@ -252,9 +252,7 @@ struct objlist *xilinx_gate(ob,nl)
 	return(nob);
 }
 
-xilinx_sym(nl,gob)
-	struct nlist *nl;
-	struct objlist *gob;
+void xilinx_sym(struct nlist *nl, struct objlist *gob)
 {
 	struct objlist *ob;
 	char *cp,*rindex();

base/xilinx.h

@@ -0,0 +1,10 @@
+#ifndef _XILINX_H
+#define _XILINX_H
+
+extern void xilinx_sym(struct nlist *nl, struct objlist *gob);
+extern void Xilinx(char *cellname, char *filename);
+extern int xilinxCell(char *cell);
+extern int XilinxLibPresent(void);
+extern void XilinxLib(void);
+
+#endif /* _XILINX_H */

python/Makefile

@@ -8,6 +8,8 @@ SCRIPTINSTALL = $(DESTDIR)${INSTALL_PYDIR}
 
 include ${NETGENDIR}/defs.mak
 
+CLEANS += lvs_manager.py
+
 main: lvs_manager.py
 
 tcl-main: lvs_manager.py
@@ -27,6 +29,7 @@ lvs_manager.py: lvs_manager.py.in
 $(DESTDIR)${INSTALL_PYDIR}/lvs_manager.py: lvs_manager.py
 	${RM} $@
 	${CP} lvs_manager.py $@
+	chmod a+x $@
 
 $(DESTDIR)${INSTALL_PYDIR}/treeviewsplit.py: treeviewsplit.py
 	${RM} $@

python/lvs_manager.py

@@ -343,7 +343,7 @@ class LVSManager(ttk.Frame):
             techbase = os.path.split(techname)[1]
             self.tech = os.path.splitext(techbase)[0]
             self.lvs_setup = techname
-            self.toppane.title2_frame.layout_select.config(text = self.tech)
+            self.toppane.title2_frame.tech_select.config(text = self.tech)
 
     def choose_layout(self):
         try:
@@ -358,30 +358,37 @@ class LVSManager(ttk.Frame):
 			title = "Choose a layout cell to compare.")
         if cellname != '':
             print("Selected compare cell " + cellname)
+            self.layout = cellname
             cellbase = os.path.split(cellname)[1]
-            self.layout = os.path.splitext(cellbase)[0]
-            self.toppane.title2_frame.layout_select.config(text = self.layout)
+            layoutname = os.path.splitext(cellbase)[0]
+            self.toppane.title2_frame.layout_select.config(text = layoutname)
+            fileext = os.path.splitext(cellbase)[1]
+            if fileext == '.mag':
+                self.toppane.title2_frame.layout_label.config(text = 'Layout:')
+            else:
+                self.toppane.title2_frame.layout_label.config(text = 'Layout netlist:')
 
     def choose_netlist(self):
         try:
             project_path = self.rootpath
-            initdirname = self.rootpath + '/netlist/' + self.project + '.spi'
+            initdirname = self.rootpath + '/netlist/' + self.project + '.spice'
         except:
             print('Must choose a project first.')
             return
         cellname = filedialog.askopenfilename(multiple=False,
 			initialdir = initdirname,
-			filetypes = (("Spice netlist", "*.spi"),("Verilog netlist", "*.v")),
+			filetypes = (("Spice netlist", "*.spice"),("Verilog netlist", "*.v"),("All Files","*.*")),
 			title = "Choose a netlist to compare.")
         if cellname != '':
             print("Selected compare cell " + cellname)
+            self.schematic = cellname
             cellbase = os.path.split(cellname)[1]
-            self.schematic = os.path.splitext(cellbase)[0]
-            self.toppane.title2_frame.schem_select.config(text = self.schematic)
+            schematic_name = os.path.splitext(cellbase)[0]
+            self.toppane.title2_frame.schem_select.config(text = schematic_name)
             fileext = os.path.splitext(cellbase)[1]
             if fileext == '.v':
                 self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
-            elif fileext == '.sp' or fileext == '.spi' or fileext == '.spice' or fileext == '.spc' or fileext == '.ckt':
+            elif fileext == '.sp' or fileext == '.spice' or fileext == '.spi' or fileext == '.spc' or fileext == '.ckt':
                 self.toppane.title2_frame.schem_label.config(text = 'SPICE netlist:')
             elif fileext == '.cdl':
                 self.toppane.title2_frame.schem_label.config(text = 'CDL netlist:')
@@ -433,7 +440,10 @@ class LVSManager(ttk.Frame):
                 self.logfile = None
 
             # Put new log file called 'lvs.log' in the mag/ subdirectory
-            self.logfile = open(rootpath + '/layout/lvs.log', 'w')
+            if os.path.exists(rootpath + '/layout'):
+                self.logfile = open(rootpath + '/layout/lvs.log', 'w')
+            else:
+                self.logfile = open(rootpath + '/lvs.log', 'w')
             # Print some initial information to the logfile.
             self.logprint('Starting new log file ' + datetime.datetime.now().strftime('%c'),
 				doflush=True)
@@ -444,15 +454,23 @@ class LVSManager(ttk.Frame):
             # Cell name is the same as project name initially
             self.layout = self.project
             self.schematic = self.project
-            self.toppane.title2_frame.layout_select.config(text = self.layout)
-            self.toppane.title2_frame.schem_select.config(text = self.schematic)
+            layname = os.path.splitext(os.path.split(self.layout)[1])[0]
+            self.toppane.title2_frame.layout_select.config(text = layname)
+            schemname = os.path.splitext(os.path.split(self.schematic)[1])[0]
+            self.toppane.title2_frame.schem_select.config(text = schemname)
 
             # Update schematic button
-            if os.path.isfile(rootpath + '/verilog/' + self.schematic + '.v'):
+            if os.path.splitext(self.schematic)[1] == '.v':
                 self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
             else:
                 self.toppane.title2_frame.schem_label.config(text = 'Schematic netlist:')
 
+            # Update layout button
+            if os.path.splitext(self.layout)[1] == '.mag':
+                self.toppane.title2_frame.schem_label.config(text = 'Layout:')
+            else:
+                self.toppane.title2_frame.schem_label.config(text = 'Layout netlist:')
+
             # If there is a comparison file that post-dates both netlists, load it.
             self.check_lvs()
         return True
@@ -567,8 +585,8 @@ class LVSManager(ttk.Frame):
         # load LVS results from comp.json
         project_path = self.rootpath
         project_name = self.project
-        layout_path = project_path + '/layout/' + project_name + '.spc'
-        net_path = project_path + '/netlist/' + project_name + '.spi'
+        layout_path = project_path + '/layout/' + project_name + '.spice'
+        net_path = project_path + '/netlist/' + project_name + '.spice'
         comp_path = project_path + '/layout/comp.json'
 
         if os.path.exists(layout_path) and os.path.exists(net_path) and os.path.exists(comp_path):
@@ -599,7 +617,7 @@ class LVSManager(ttk.Frame):
             mproc.stdin.write("ext2spice cthresh infinite\n")
             mproc.stdin.write("ext2spice rthresh infinite\n")
             mproc.stdin.write("ext2spice blackbox on\n")
-            mproc.stdin.write("ext2spice -o " + self.layout + ".spi\n")
+            mproc.stdin.write("ext2spice -o " + self.layout + ".spice\n")
             mproc.stdin.write("quit -noprompt\n")
             magicout = mproc.communicate()[0]
             self.printwarn(magicout)
@@ -607,8 +625,8 @@ class LVSManager(ttk.Frame):
                 print('Failure to generate new layout netlist.')
                 return False
 
-            # Move .spi netlist to project_dir/netlist/lvs/
-            shutil.move(project_path + '/layout/' + self.layout + '.spi', layout_path)
+            # Move .spice netlist to project_dir/netlist/lvs/
+            shutil.move(project_path + '/layout/' + self.layout + '.spice', layout_path)
             # Remove extraction files
             for file in os.listdir(project_path + '/layout'):
                 if os.path.splitext(file)[1] == '.ext':
@@ -625,17 +643,37 @@ class LVSManager(ttk.Frame):
 
         project_path = self.rootpath
         project_name = self.project
-        comp_path = project_path + '/layout/comp.json'
+
+        # Diagnostic:
+        print('project_name is ' + project_name)
+        print('project_path is ' + project_path)
+        print('self.layout is ' + self.layout)
+        print('self.schematic is ' + self.schematic)
+        print('self.lvs_setup is ' + self.lvs_setup)
+
         has_vlog = False
         vlog_path = project_path + '/verilog/' + project_name + '.v'
 
-        layout_path = project_path + '/netlist/lvs/' + self.layout + '.spi'
-        net_path = project_path + '/netlist/schem/' + self.schematic + '.spi'
-        layout_src = project_path + '/layout/' + self.layout + '.mag'
+        if os.path.isfile(self.layout):
+            layout_path = self.layout
+            layout_src = None
+        else:
+            layout_path = project_path + '/netlist/lvs/' + self.layout + '.spice'
+            layout_src = project_path + '/layout/' + self.layout + '.mag'
+
+        comp_dir = os.path.split(layout_path)[0]
+        comp_path = comp_dir + '/comp.json'
+
+        if os.path.isfile(self.schematic):
+            net_path = self.schematic
+        else:
+            net_path = project_path + '/netlist/schem/' + self.schematic + '.spice'
 
         # Does the setup file exist (this is optional)?
-        if self.lvs_setup != '' and not os.path.isfile('setup.tcl'):
+        if self.lvs_setup == '' and not os.path.isfile('setup.tcl'):
             print('No technology setup file selected.')
+        elif not os.path.isfile(self.lvs_setup):
+            print("Can't find technology setup file " + self.lvs_setup)
 
         # Does schematic netlist exist?
         if not os.path.isfile(vlog_path) and not os.path.isfile(net_path):
@@ -643,14 +681,16 @@ class LVSManager(ttk.Frame):
             return
 
         # Does LVS netlist subdirectory exist?
-        if not os.path.exists(project_path + '/netlist/lvs'):
-            os.makedirs(project_path + '/netlist/lvs')
+        if os.path.exists(project_path + '/netlist'):
+            if not os.path.exists(project_path + '/netlist/lvs'):
+                os.makedirs(project_path + '/netlist/lvs')
 
         # Does layout netlist exist and is it current?
-        if not self.generate_layout_netlist(layout_path, layout_src, project_path):
-            return False
+        if layout_src:
+            if not self.generate_layout_netlist(layout_path, layout_src, project_path):
+                return False
 
-        # Final check
+        # Final checks
         if not os.path.isfile(layout_path):
             print('Error:  No netlist generated from magic.')
             return
@@ -662,26 +702,27 @@ class LVSManager(ttk.Frame):
             with open(layout_path) as ifile:
                 spitext = ifile.read()
 
-            # spilines = spitext.replace(',', '|')
-            # with open(layout_path, 'w') as ofile:
-            #     ofile.write(spilines)
-
         # Check the netlist to see if the cell to match is a subcircuit.  If
         # not, then assume it is the top level.
 
+        layoutcell = os.path.splitext(os.path.split(self.layout)[1])[0]
         is_subckt = False
+        subname = None
         subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
         dutlines = spitext.replace('\n+', ' ').splitlines()
         for line in dutlines:
             lmatch = subrex.match(line)
             if lmatch:
                 subname = lmatch.group(1)
-                if subname == self.layout:
+                if subname == layoutcell:
                     is_subckt = True
                     break
 
         if is_subckt:
-            layout_arg = layout_path + ' ' + self.layout
+            layout_arg = self.layout + ' ' + layoutcell
+            layout_text = '"' + layout_arg + '"'
+        elif subname:
+            layout_arg = self.layout + ' ' + subname
             layout_text = '"' + layout_arg + '"'
         else:
             layout_arg = layout_path
@@ -690,8 +731,39 @@ class LVSManager(ttk.Frame):
         if has_vlog:
             schem_arg = vlog_path + ' ' + self.schematic
         else:
-            schem_arg = net_path + ' ' + self.schematic
-        schem_text = '"' + schem_arg + '"'
+            # Final checks
+            if not os.path.isfile(net_path):
+                print('Error:  No netlist from schematic.')
+                return
+
+            with open(net_path) as ifile:
+                spitext = ifile.read()
+
+            # Check the netlist to see if the cell to match is a subcircuit.  If
+            # not, then assume it is the top level.
+
+            schemcell = os.path.splitext(os.path.split(self.schematic)[1])[0]
+            subname = None
+            is_subckt = False
+            subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
+            dutlines = spitext.replace('\n+', ' ').splitlines()
+            for line in dutlines:
+                lmatch = subrex.match(line)
+                if lmatch:
+                    subname = lmatch.group(1)
+                    if subname == schemcell:
+                        is_subckt = True
+                        break
+
+            if is_subckt:
+                schem_arg = self.schematic + ' ' + schemcell
+                schem_text = '"' + schem_arg + '"'
+            elif subname:
+                schem_arg = self.schematic + ' ' + subname
+                schem_text = '"' + schem_arg + '"'
+            else:
+                schem_arg = net_path
+                schem_text = schem_arg
 
         # Remove any previous comparison output file
         comp_out_path = os.path.splitext(comp_path)[0] + '.out'
@@ -708,7 +780,7 @@ class LVSManager(ttk.Frame):
         self.lvsproc = subprocess.Popen(['netgen', '-batch', 'lvs',
 		layout_arg, schem_arg,
 		self.lvs_setup, comp_out_path, '-json', '-blackbox'],
-		cwd=project_path + '/layout',
+		cwd=comp_dir,
 		stdout=subprocess.PIPE, stderr=subprocess.PIPE, bufsize=0)
         # This is largely unnecessary as netgen usually runs to completion very quickly.
         self.watchclock(comp_path)

python/lvs_manager.py.in

@@ -343,7 +343,7 @@ class LVSManager(ttk.Frame):
             techbase = os.path.split(techname)[1]
             self.tech = os.path.splitext(techbase)[0]
             self.lvs_setup = techname
-            self.toppane.title2_frame.layout_select.config(text = self.tech)
+            self.toppane.title2_frame.tech_select.config(text = self.tech)
 
     def choose_layout(self):
         try:
@@ -358,30 +358,37 @@ class LVSManager(ttk.Frame):
 			title = "Choose a layout cell to compare.")
         if cellname != '':
             print("Selected compare cell " + cellname)
+            self.layout = cellname
             cellbase = os.path.split(cellname)[1]
-            self.layout = os.path.splitext(cellbase)[0]
-            self.toppane.title2_frame.layout_select.config(text = self.layout)
+            layoutname = os.path.splitext(cellbase)[0]
+            self.toppane.title2_frame.layout_select.config(text = layoutname)
+            fileext = os.path.splitext(cellbase)[1]
+            if fileext == '.mag':
+                self.toppane.title2_frame.layout_label.config(text = 'Layout:')
+            else:
+                self.toppane.title2_frame.layout_label.config(text = 'Layout netlist:')
 
     def choose_netlist(self):
         try:
             project_path = self.rootpath
-            initdirname = self.rootpath + '/netlist/' + self.project + '.spi'
+            initdirname = self.rootpath + '/netlist/' + self.project + '.spice'
         except:
             print('Must choose a project first.')
             return
         cellname = filedialog.askopenfilename(multiple=False,
 			initialdir = initdirname,
-			filetypes = (("Spice netlist", "*.spi"),("Verilog netlist", "*.v")),
+			filetypes = (("Spice netlist", "*.spice"),("Verilog netlist", "*.v"),("All Files","*.*")),
 			title = "Choose a netlist to compare.")
         if cellname != '':
             print("Selected compare cell " + cellname)
+            self.schematic = cellname
             cellbase = os.path.split(cellname)[1]
-            self.schematic = os.path.splitext(cellbase)[0]
-            self.toppane.title2_frame.schem_select.config(text = self.schematic)
+            schematic_name = os.path.splitext(cellbase)[0]
+            self.toppane.title2_frame.schem_select.config(text = schematic_name)
             fileext = os.path.splitext(cellbase)[1]
             if fileext == '.v':
                 self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
-            elif fileext == '.sp' or fileext == '.spi' or fileext == '.spice' or fileext == '.spc' or fileext == '.ckt':
+            elif fileext == '.sp' or fileext == '.spice' or fileext == '.spi' or fileext == '.spc' or fileext == '.ckt':
                 self.toppane.title2_frame.schem_label.config(text = 'SPICE netlist:')
             elif fileext == '.cdl':
                 self.toppane.title2_frame.schem_label.config(text = 'CDL netlist:')
@@ -433,7 +440,10 @@ class LVSManager(ttk.Frame):
                 self.logfile = None
 
             # Put new log file called 'lvs.log' in the mag/ subdirectory
-            self.logfile = open(rootpath + '/layout/lvs.log', 'w')
+            if os.path.exists(rootpath + '/layout'):
+                self.logfile = open(rootpath + '/layout/lvs.log', 'w')
+            else:
+                self.logfile = open(rootpath + '/lvs.log', 'w')
             # Print some initial information to the logfile.
             self.logprint('Starting new log file ' + datetime.datetime.now().strftime('%c'),
 				doflush=True)
@@ -444,15 +454,23 @@ class LVSManager(ttk.Frame):
             # Cell name is the same as project name initially
             self.layout = self.project
             self.schematic = self.project
-            self.toppane.title2_frame.layout_select.config(text = self.layout)
-            self.toppane.title2_frame.schem_select.config(text = self.schematic)
+            layname = os.path.splitext(os.path.split(self.layout)[1])[0]
+            self.toppane.title2_frame.layout_select.config(text = layname)
+            schemname = os.path.splitext(os.path.split(self.schematic)[1])[0]
+            self.toppane.title2_frame.schem_select.config(text = schemname)
 
             # Update schematic button
-            if os.path.isfile(rootpath + '/verilog/' + self.schematic + '.v'):
+            if os.path.splitext(self.schematic)[1] == '.v':
                 self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
             else:
                 self.toppane.title2_frame.schem_label.config(text = 'Schematic netlist:')
 
+            # Update layout button
+            if os.path.splitext(self.layout)[1] == '.mag':
+                self.toppane.title2_frame.schem_label.config(text = 'Layout:')
+            else:
+                self.toppane.title2_frame.schem_label.config(text = 'Layout netlist:')
+
             # If there is a comparison file that post-dates both netlists, load it.
             self.check_lvs()
         return True
@@ -567,8 +585,8 @@ class LVSManager(ttk.Frame):
         # load LVS results from comp.json
         project_path = self.rootpath
         project_name = self.project
-        layout_path = project_path + '/layout/' + project_name + '.spc'
-        net_path = project_path + '/netlist/' + project_name + '.spi'
+        layout_path = project_path + '/layout/' + project_name + '.spice'
+        net_path = project_path + '/netlist/' + project_name + '.spice'
         comp_path = project_path + '/layout/comp.json'
 
         if os.path.exists(layout_path) and os.path.exists(net_path) and os.path.exists(comp_path):
@@ -599,7 +617,7 @@ class LVSManager(ttk.Frame):
             mproc.stdin.write("ext2spice cthresh infinite\n")
             mproc.stdin.write("ext2spice rthresh infinite\n")
             mproc.stdin.write("ext2spice blackbox on\n")
-            mproc.stdin.write("ext2spice -o " + self.layout + ".spi\n")
+            mproc.stdin.write("ext2spice -o " + self.layout + ".spice\n")
             mproc.stdin.write("quit -noprompt\n")
             magicout = mproc.communicate()[0]
             self.printwarn(magicout)
@@ -607,8 +625,8 @@ class LVSManager(ttk.Frame):
                 print('Failure to generate new layout netlist.')
                 return False
 
-            # Move .spi netlist to project_dir/netlist/lvs/
-            shutil.move(project_path + '/layout/' + self.layout + '.spi', layout_path)
+            # Move .spice netlist to project_dir/netlist/lvs/
+            shutil.move(project_path + '/layout/' + self.layout + '.spice', layout_path)
             # Remove extraction files
             for file in os.listdir(project_path + '/layout'):
                 if os.path.splitext(file)[1] == '.ext':
@@ -625,17 +643,37 @@ class LVSManager(ttk.Frame):
 
         project_path = self.rootpath
         project_name = self.project
-        comp_path = project_path + '/layout/comp.json'
+
+        # Diagnostic:
+        print('project_name is ' + project_name)
+        print('project_path is ' + project_path)
+        print('self.layout is ' + self.layout)
+        print('self.schematic is ' + self.schematic)
+        print('self.lvs_setup is ' + self.lvs_setup)
+
         has_vlog = False
         vlog_path = project_path + '/verilog/' + project_name + '.v'
 
-        layout_path = project_path + '/netlist/lvs/' + self.layout + '.spi'
-        net_path = project_path + '/netlist/schem/' + self.schematic + '.spi'
-        layout_src = project_path + '/layout/' + self.layout + '.mag'
+        if os.path.isfile(self.layout):
+            layout_path = self.layout
+            layout_src = None
+        else:
+            layout_path = project_path + '/netlist/lvs/' + self.layout + '.spice'
+            layout_src = project_path + '/layout/' + self.layout + '.mag'
+
+        comp_dir = os.path.split(layout_path)[0]
+        comp_path = comp_dir + '/comp.json'
+
+        if os.path.isfile(self.schematic):
+            net_path = self.schematic
+        else:
+            net_path = project_path + '/netlist/schem/' + self.schematic + '.spice'
 
         # Does the setup file exist (this is optional)?
-        if self.lvs_setup != '' and not os.path.isfile('setup.tcl'):
+        if self.lvs_setup == '' and not os.path.isfile('setup.tcl'):
             print('No technology setup file selected.')
+        elif not os.path.isfile(self.lvs_setup):
+            print("Can't find technology setup file " + self.lvs_setup)
 
         # Does schematic netlist exist?
         if not os.path.isfile(vlog_path) and not os.path.isfile(net_path):
@@ -643,14 +681,16 @@ class LVSManager(ttk.Frame):
             return
 
         # Does LVS netlist subdirectory exist?
-        if not os.path.exists(project_path + '/netlist/lvs'):
-            os.makedirs(project_path + '/netlist/lvs')
+        if os.path.exists(project_path + '/netlist'):
+            if not os.path.exists(project_path + '/netlist/lvs'):
+                os.makedirs(project_path + '/netlist/lvs')
 
         # Does layout netlist exist and is it current?
-        if not self.generate_layout_netlist(layout_path, layout_src, project_path):
-            return False
+        if layout_src:
+            if not self.generate_layout_netlist(layout_path, layout_src, project_path):
+                return False
 
-        # Final check
+        # Final checks
         if not os.path.isfile(layout_path):
             print('Error:  No netlist generated from magic.')
             return
@@ -662,26 +702,27 @@ class LVSManager(ttk.Frame):
             with open(layout_path) as ifile:
                 spitext = ifile.read()
 
-            # spilines = spitext.replace(',', '|')
-            # with open(layout_path, 'w') as ofile:
-            #     ofile.write(spilines)
-
         # Check the netlist to see if the cell to match is a subcircuit.  If
         # not, then assume it is the top level.
 
+        layoutcell = os.path.splitext(os.path.split(self.layout)[1])[0]
         is_subckt = False
+        subname = None
         subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
         dutlines = spitext.replace('\n+', ' ').splitlines()
         for line in dutlines:
             lmatch = subrex.match(line)
             if lmatch:
                 subname = lmatch.group(1)
-                if subname == self.layout:
+                if subname == layoutcell:
                     is_subckt = True
                     break
 
         if is_subckt:
-            layout_arg = layout_path + ' ' + self.layout
+            layout_arg = self.layout + ' ' + layoutcell
+            layout_text = '"' + layout_arg + '"'
+        elif subname:
+            layout_arg = self.layout + ' ' + subname
             layout_text = '"' + layout_arg + '"'
         else:
             layout_arg = layout_path
@@ -690,8 +731,39 @@ class LVSManager(ttk.Frame):
         if has_vlog:
             schem_arg = vlog_path + ' ' + self.schematic
         else:
-            schem_arg = net_path + ' ' + self.schematic
-        schem_text = '"' + schem_arg + '"'
+            # Final checks
+            if not os.path.isfile(net_path):
+                print('Error:  No netlist from schematic.')
+                return
+
+            with open(net_path) as ifile:
+                spitext = ifile.read()
+
+            # Check the netlist to see if the cell to match is a subcircuit.  If
+            # not, then assume it is the top level.
+
+            schemcell = os.path.splitext(os.path.split(self.schematic)[1])[0]
+            subname = None
+            is_subckt = False
+            subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
+            dutlines = spitext.replace('\n+', ' ').splitlines()
+            for line in dutlines:
+                lmatch = subrex.match(line)
+                if lmatch:
+                    subname = lmatch.group(1)
+                    if subname == schemcell:
+                        is_subckt = True
+                        break
+
+            if is_subckt:
+                schem_arg = self.schematic + ' ' + schemcell
+                schem_text = '"' + schem_arg + '"'
+            elif subname:
+                schem_arg = self.schematic + ' ' + subname
+                schem_text = '"' + schem_arg + '"'
+            else:
+                schem_arg = net_path
+                schem_text = schem_arg
 
         # Remove any previous comparison output file
         comp_out_path = os.path.splitext(comp_path)[0] + '.out'
@@ -708,7 +780,7 @@ class LVSManager(ttk.Frame):
         self.lvsproc = subprocess.Popen(['netgen', '-batch', 'lvs',
 		layout_arg, schem_arg,
 		self.lvs_setup, comp_out_path, '-json', '-blackbox'],
-		cwd=project_path + '/layout',
+		cwd=comp_dir,
 		stdout=subprocess.PIPE, stderr=subprocess.PIPE, bufsize=0)
         # This is largely unnecessary as netgen usually runs to completion very quickly.
         self.watchclock(comp_path)

tcltk/netgen.tcl.in

@@ -532,7 +532,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
    }
    set properr {}
    set matcherr {}
-   set pinsgood 0
+   set pinsgood -1
    while {$endval != {}} {
       if {$dolist == 1} {
          netgen::run -list converge
@@ -562,12 +562,13 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
             if {[netgen::print queue] != {}} {
 	       if {([lsearch $noflat [lindex $endval 0]] == -1) &&
 			([lsearch $noflat [lindex $endval 1]] == -1)} {
-	           netgen::log put "  Flattening non-matched subcircuits $endval"
+	           netgen::log put "  Flattening non-matched subcircuits $endval\n"
 	           netgen::flatten class "[lindex $endval 0] $fnum1"
 	           netgen::flatten class "[lindex $endval 1] $fnum2"
 	       } else {
-	           netgen::log put "  Continuing with black-boxed subcircuits $endval"
-		   lappend matcherr [lindex $endval 0]
+	           netgen::log put "  Continuing with black-boxed subcircuits $endval\n"
+		   lappend matcherr [lindex $endval 0]"($fnum1)"
+		   lappend matcherr [lindex $endval 1]"($fnum2)"
 	           # Match pins
                    netgen::log echo off
 	           if {$dolist == 1} {
@@ -586,7 +587,6 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
 	       }
 	    }
 	 } else {
-	    # Match pins
             netgen::log echo off
 	    if {$dolist == 1} {
 		set result [equate -list pins "$fnum1 [lindex $endval 0]" \
@@ -599,23 +599,26 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
 		equate classes "$fnum1 [lindex $endval 0]" \
 			 "$fnum2 [lindex $endval 1]"
 	    }
-	    set pinsgood $result
+	    # If $uresult == -1 then these are black-box entries and
+	    # $pinsgood should not be set to the resulting value.
+	    if {$uresult > 0} {
+	        set pinsgood $result
+	    }
             netgen::log echo on
 	 }
 	 if {$uresult == 2} {lappend properr [lindex $endval 0]}
       } else {
 	 # Flatten the non-matching subcircuit (but not the top-level cells)
          if {[netgen::print queue] != {}} {
-	    if {([lsearch $noflat [lindex $endval 1]] == -1) &&
+	    if {([lsearch $noflat [lindex $endval 0]] == -1) &&
 		    ([lsearch $noflat [lindex $endval 1]] == -1)} {
-	       netgen::log put "  Flattening non-matched subcircuits $endval"
+	       netgen::log put "  Flattening non-matched subcircuits $endval\n"
 	       netgen::flatten class "[lindex $endval 0] $fnum1"
 	       netgen::flatten class "[lindex $endval 1] $fnum2"
 	    } else {
-	       netgen::log put "  Continuing with black-boxed subcircuits $endval"
-	       lappend matcherr [lindex $endval 0]
-	       netgen::log put "  Continuing with black-boxed subcircuits $endval"
-	       lappend matcherr [lindex $endval 0]
+	       netgen::log put "  Continuing with black-boxed subcircuits $endval\n"
+	       lappend matcherr [lindex $endval 0]"($fnum1)"
+	       lappend matcherr [lindex $endval 0]"($fnum2)"
 	       # Match pins
                netgen::log echo off
 	       if {$dolist == 1} {
@@ -647,15 +650,16 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
    puts stdout "Result: " nonewline
    netgen::log echo on
    if {$pinsgood == 0} {
-      netgen::log put "The top level cell failed pin matching.\n"
+      # NOTE:  Need to disambiguate these two cases. . .
+      netgen::log put "Cells failed matching, or top level cell failed pin matching.\n"
    } else {
       verify only
    }
    if {$properr != {}} {
-      netgen::log put "The following cells had property errors: $properr\n"
+      netgen::log put "The following cells had property errors:\n " [regsub -all { } $properr "\n "] "\n"
    }
    if {$matcherr != {}} {
-      netgen::log put "The following subcells failed to match: $matcherr\n"
+      netgen::log put "The following subcells failed to match:\n " [regsub -all { } $matcherr "\n "] "\n"
    }
    if {$dolog} {
       netgen::log end

tcltk/tclnetgen.c

@@ -32,6 +32,9 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include "print.h"
 #include "query.h"	/* for ElementNodes() */
 #include "hash.h"
+#include "xilinx.h"
+#include "tech.h"
+#include "flatten.h"
 
 #ifndef TRUE
 #define TRUE 1
@@ -976,7 +979,7 @@ _netgen_writenet(ClientData clientData,
          SpiceCell(repstr, filenum, "");
          break;
       case VERILOG_IDX:
-         VerilogModule(repstr, filenum, "");
+         VerilogTop(repstr, filenum, "");
          break;
       case WOMBAT_IDX:
          Wombat(repstr,NULL);
@@ -2066,6 +2069,7 @@ _netcmp_format(ClientData clientData,
 	Tcl_WrongNumArgs(interp, 1, objv, "[col1_width [col2_width]]");
 	return TCL_ERROR;
     }
+    return TCL_OK;
 }
 
 /*------------------------------------------------------*/
@@ -2091,8 +2095,9 @@ _netcmp_compare(ClientData clientData,
    int dohierarchy = FALSE;
    int assignonly = FALSE;
    int argstart = 1, qresult, llen, result;
+   int hascontents1, hascontents2;
    struct Correspond *nextcomp;
-   struct nlist *tp;
+   struct nlist *tp1 = NULL, *tp2 = NULL;
    Tcl_Obj *flist = NULL;
 
    if (objc > 1) {
@@ -2135,24 +2140,24 @@ _netcmp_compare(ClientData clientData,
       }
       else if ((objc - argstart) == 2) {
 
-	 result = CommonParseCell(interp, objv[argstart], &tp, &fnum1);
+	 result = CommonParseCell(interp, objv[argstart], &tp1, &fnum1);
          if (result != TCL_OK) return TCL_ERROR;
 	 else if (fnum1 == -1) {
 	    Tcl_SetResult(interp, "Cannot use wildcard with compare command.\n",
 			NULL);
 	    return TCL_ERROR;
 	 }
-         name1 = tp->name;
+         name1 = tp1->name;
 	 argstart++;
 
-	 result = CommonParseCell(interp, objv[argstart], &tp, &fnum2);
+	 result = CommonParseCell(interp, objv[argstart], &tp2, &fnum2);
          if (result != TCL_OK) return TCL_ERROR;
 	 else if (fnum2 == -1) {
 	    Tcl_SetResult(interp, "Cannot use wildcard with compare command.\n",
 			NULL);
 	    return TCL_ERROR;
 	 }
-         name2 = tp->name;
+         name2 = tp2->name;
 
          if (dohierarchy) {
 	    RemoveCompareQueue();
@@ -2191,11 +2196,34 @@ _netcmp_compare(ClientData clientData,
       ConvertGlobals(name2, fnum2);
    }
 
-   CreateTwoLists(name1, fnum1, name2, fnum2, dolist);
-   while (PrematchLists(name1, fnum1, name2, fnum2) > 0) {
-      Fprintf(stdout, "Making another compare attempt.\n");
-      CreateTwoLists(name1, fnum1, name2, fnum2, dolist);
+   tp1 = LookupCellFile(name1, fnum1);
+   tp2 = LookupCellFile(name2, fnum2);
+
+   hascontents1 = HasContents(tp1);
+   hascontents2 = HasContents(tp2);
+
+   if (hascontents1 && !hascontents2 && (tp2->flags & CELL_PLACEHOLDER)) {
+       Fprintf(stdout, "Circuit 2 cell %s is a black box; will not flatten "
+                        "Circuit 1\n", name2);
    }
+   else if (hascontents2 && !hascontents1 && (tp1->flags & CELL_PLACEHOLDER)) {
+       Fprintf(stdout, "Circuit 1 cell %s is a black box; will not flatten "
+                        "Circuit 2\n", name1);
+   }
+   else if (hascontents1 || hascontents2) {
+       FlattenUnmatched(tp1, name1, 1, 0);
+       FlattenUnmatched(tp2, name2, 1, 0);
+       DescribeContents(name1, fnum1, name2, fnum2);
+
+       while (PrematchLists(name1, fnum1, name2, fnum2) > 0) {
+          Fprintf(stdout, "Making another compare attempt.\n");
+          Printf("Flattened mismatched instances and attempting compare again.\n");
+          FlattenUnmatched(tp1, name1, 1, 0);
+          FlattenUnmatched(tp2, name2, 1, 0);
+          DescribeContents(name1, fnum1, name2, fnum2);
+       }
+   }
+   CreateTwoLists(name1, fnum1, name2, fnum2, dolist);
 
    // Return the names of the two cells being compared, if doing "compare
    // hierarchical".  If "-list" was specified, then append the output
@@ -2428,6 +2456,8 @@ _netcmp_run(ClientData clientData,
 	 else {
 	    enable_interrupt();
 	    while (!Iterate() && !InterruptPending);
+	    ExhaustiveSubdivision = 1;
+	    while (!Iterate() && !InterruptPending);
 	    if (dolist) {
 	       result = _netcmp_verify(clientData, interp, 2, objv - 1);
 	    }
@@ -2446,6 +2476,8 @@ _netcmp_run(ClientData clientData,
 	 else {
 	    enable_interrupt();
 	    while (!Iterate() && !InterruptPending);
+	    ExhaustiveSubdivision = 1;
+	    while (!Iterate() && !InterruptPending);
 	    automorphisms = VerifyMatching();
 	    if (automorphisms == -1)
 	       Fprintf(stdout, "Netlists do not match.\n");
@@ -3023,11 +3055,11 @@ _netcmp_equate(ClientData clientData,
 			(tp2->flags & CELL_PLACEHOLDER)) {
 		if (tp1->flags & CELL_PLACEHOLDER) {
 		    Fprintf(stdout, "Warning: Equate pins:  cell %s "
-			"has no definition, treated as a black box.\n", name1);
+			"is a placeholder, treated as a black box.\n", name1);
 		}
 		if (tp2->flags & CELL_PLACEHOLDER) {
 		    Fprintf(stdout, "Warning: Equate pins:  cell %s "
-			"has no definition, treated as a black box.\n", name2);
+			"is a placeholder, treated as a black box.\n", name2);
 		}
 		// If a cell in either circuit is marked as a black box, then
 		// the cells in both circuits should be marked as a black box.