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netgen
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Merge branch 'master' into netgen-1.5

This commit is contained in:
Tim Edwards 2021-10-30 03:00:02 -04:00
parent 6b8c6d1718 e4a15f12fb
commit 737b2a73bf
5 changed files with 16 additions and 12 deletions
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2
VERSION
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@ -1 +1 @@
1.5.207
1.5.208

5
base/netcmp.c
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@ -3125,7 +3125,7 @@ int FirstElementPass(struct Element *E, int noflat, int dolist)
ostr = CALLOC(right_col_end + 2, sizeof(char));
if (Debug == 0) {
Fprintf(stdout, "\nSubcircuit summary:\n");
Fprintf(stdout, "Subcircuit summary:\n");
*(ostr + left_col_end) = '|';
*(ostr + right_col_end) = '\n';
*(ostr + right_col_end + 1) = '\0';
@ -3736,8 +3736,9 @@ void CreateTwoLists(char *name1, int file1, char *name2, int file2, int dolist)
ResetState();
Fprintf(stdout, "\n"); // blank line before new circuit diagnostics in log file
/* print preliminary statistics */
Printf("Contents of circuit 1: ");
Printf("\nContents of circuit 1: ");
DescribeInstance(name1, file1);
Printf("Contents of circuit 2: ");
DescribeInstance(name2, file2);

5
base/netgen.c
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@ -3441,7 +3441,7 @@ int CombineParallel(char *model, int file)
}
HashKill(&devdict);
if (dcnt > 0) {
Fprintf(stdout, "Class %s: Merged %d devices.\n", model, dcnt);
Fprintf(stdout, "Class %s(%d): Merged %d parallel devices.\n", model, file, dcnt);
}
FREE(nodecount);
return dcnt;
@ -3738,6 +3738,9 @@ int CombineSeries(char *model, int file)
}
}
FREE(instlist);
if (scnt > 0) {
Fprintf(stdout, "Class %s(%d): Merged %d series devices.\n", model, file, scnt);
}
return scnt;
}

4
base/query.c
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@ -807,9 +807,9 @@ void DescribeInstance(char *name, int file)
if (!(tp->flags & CELL_PLACEHOLDER) && (tp->class != CLASS_MODULE))
{
if (disconnectednodes == 0) Fprintf(stderr, "\n");
//if (disconnectednodes == 0) Fprintf(stderr, "\n");
disconnectednodes++;
Fprintf(stderr, "Cell %s disconnected node: %s\n", tp->name, ob->name);
Fprintf(stderr, "Cell %s(%d) disconnected node: %s\n", tp->name, tp->file, ob->name);
}
}
}

12
tcltk/netgen.tcl.in
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@ -567,7 +567,8 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
netgen::flatten class "[lindex $endval 1] $fnum2"
} else {
netgen::log put " Continuing with black-boxed subcircuits $endval\n"
lappend matcherr [lindex $endval 0]
lappend matcherr [lindex $endval 0]"($fnum1)"
lappend matcherr [lindex $endval 1]"($fnum2)"
# Match pins
netgen::log echo off
if {$dolist == 1} {
@ -616,9 +617,8 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
netgen::flatten class "[lindex $endval 1] $fnum2"
} else {
netgen::log put " Continuing with black-boxed subcircuits $endval\n"
lappend matcherr [lindex $endval 0]"(1)"
netgen::log put " Continuing with black-boxed subcircuits $endval\n"
lappend matcherr [lindex $endval 0]"(2)"
lappend matcherr [lindex $endval 0]"($fnum1)"
lappend matcherr [lindex $endval 0]"($fnum2)"
# Match pins
netgen::log echo off
if {$dolist == 1} {
@ -656,10 +656,10 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
verify only
}
if {$properr != {}} {
netgen::log put "The following cells had property errors: $properr\n"
netgen::log put "The following cells had property errors:\n " [regsub -all { } $properr "\n "] "\n"
}
if {$matcherr != {}} {
netgen::log put "The following subcells failed to match: $matcherr\n"
netgen::log put "The following subcells failed to match:\n " [regsub -all { } $matcherr "\n "] "\n"
}
if {$dolog} {
netgen::log end