Merge branch 'master' into netgen-1.5

VERSION

@@ -1 +1 @@
-1.5.142
+1.5.143

base/netcmp.c

@@ -4436,12 +4436,13 @@ int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run, int series,
 		  if (vl == NULL) {
 		     if (kl->type != vlist[p][j]->type)
 			PromoteProperty(kl, vl2);
+		     vl = &dfltvl;
 		  }
 		  else {
 		     if (kl->type != vlist[p][i]->type)
 			PromoteProperty(kl, vl);
+		     vl2 = &dfltvl;
 		  }
-		  vl = &dfltvl;
 		  dfltvl.type = kl->type;
 		  switch (kl->type) {
 		     case PROP_STRING:

base/spice.c

@@ -1983,11 +1983,15 @@ void IncludeSpice(char *fname, int parent, struct cellstack **CellStackPtr,
 	if (strchr(fname, '.') == NULL) {
            SetExtension(name, fname, SPICE_EXTENSION);
            filenum = OpenParseFile(name, parent);
-	}
-        if (filenum < 0) {
-           Fprintf(stderr,"Error in SPICE file include: No file %s\n",name);
-           return;
+	   if (filenum < 0) {
+             Fprintf(stderr, "Error in SPICE file include: No file %s\n", name);
+             return;
+	   }
         }    
+        else {
+          Fprintf(stderr, "Error in SPICE file include: No file %s\n", fname);
+          return;
+	}
      }
   }
   ReadSpiceFile(fname, parent, CellStackPtr, blackbox);

base/verilog.c

@@ -2043,11 +2043,15 @@ void IncludeVerilog(char *fname, int parent, struct cellstack **CellStackPtr,
 	if (strchr(fname, '.') == NULL) {
            SetExtension(name, fname, VERILOG_EXTENSION);
            filenum = OpenParseFile(name, parent);
+	   if (filenum < 0) {
+	      fprintf(stderr,"Error in Verilog file include: No file %s\n", name);
+	      return;
+	   }
         }
-	if (filenum < 0) {
+	else {
 	   fprintf(stderr,"Error in Verilog file include: No file %s\n", fname);
 	   return;
-        }    
+        }
      }
   }
   ReadVerilogFile(fname, parent, CellStackPtr, blackbox);

tcltk/tclnetgen.c

@@ -2974,6 +2974,10 @@ _netcmp_equate(ClientData clientData,
 		    Fprintf(stdout, "Warning: Equate pins:  cell %s "
 			"has no definition, treated as a black box.\n", name2);
 		}
+		// If a cell in either circuit is marked as a black box, then
+		// the cells in both circuits should be marked as a black box.
+		tp1->flags |= CELL_PLACEHOLDER;
+		tp2->flags |= CELL_PLACEHOLDER;
 	    }
 	    else {
 		Fprintf(stdout, "Equate pins:  cell %s and/or %s "