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netgen
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Merge branch 'master' into netgen-1.5

This commit is contained in:
Tim Edwards 2020-08-04 03:00:31 -04:00
parent 69c9d85be7 82be18ec4b
commit ed5276d67b
2 changed files with 18 additions and 5 deletions
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2
VERSION
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@ -1 +1 @@
1.5.153
1.5.154

21
base/verilog.c
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@ -1225,7 +1225,12 @@ skip_endmodule:
lhs = LookupObject(nodename, CurrentCell);
*aptr = '[';
}
else strcpy(noderoot, nexttok);
else {
strcpy(noderoot, nexttok);
/* Set LHS to the start of the vector */
sprintf(nodename, "%s[%d]", nexttok, wb.start);
lhs = LookupObject(nodename, CurrentCell);
}
}
else {
lhs = LookupObject(nexttok, CurrentCell);
@ -1290,13 +1295,21 @@ skip_endmodule:
if (rhs != NULL) {
Printf("Improper assignment; left-hand side cannot "
"be parsed.\n");
Printf("Right-hand side is \"%s\".\n", rhs->name);
if (j != -1)
Printf("Right-hand side is \"%s\".\n", assignroot);
else
Printf("Right-hand side is \"%s\".\n", rhs->name);
Printf("Improper expression is \"%s\".\n", nexttok);
break;
}
if (lhs != NULL) {
Printf("Improper assignment; right-hand side cannot "
"be parsed.\n");
Printf("Left-hand side is \"%s\".\n", lhs->name);
if (i != -1)
Printf("Left-hand side is \"%s\".\n", noderoot);
else
Printf("Left-hand side is \"%s\".\n", lhs->name);
Printf("Improper expression is \"%s\".\n", nexttok);
/* Not parsable, probably behavioral verilog? */
Printf("Module '%s' is not structural verilog, "
"making black-box.\n", model);
@ -1854,7 +1867,7 @@ nextinst:
if (is_bundle &&
((i == -1) ||
((wbb.start > wbb.end) && (i < wbb.end)) ||
((wbb.start < wbb.end) && (i > wbb.end)))) {
((wbb.start <= wbb.end) && (i > wbb.end)))) {
if (bptr) *bptr = '[';
netname = cptr + 1;