Fischer Moseley
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a67adc31d2
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uart: initial commit of updated COBS decoder
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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e82f0ab6e8
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meta: autoformat with updated ruff config
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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d63ce8305b
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uart: add more cases to random COBS encoder tests
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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349de40cd2
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uart: tidy COBS encoder tests
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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d8fbf71146
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uart: fix COBS encoder bug where 254th byte is zero
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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0c0f6121b3
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uart: handle case of 255 byte-long groups in COBS encoder
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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6631ddde6a
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uart: rewrite COBS encoder to allow backpressure
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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b1fc256f26
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uart: use wiring.Component for internal bus
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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0c77b9e49a
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uart: remove unused bridge testbenches
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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1714521026
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uart: fix tests for receiver and transmitter modules
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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e4f6f29b05
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uart: update top-level wiring in UARTInterface
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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43c22aa0e5
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uart: use wiring.Component instead of plain Elaborateable
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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db81d8cbf0
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meta: replace Signal(1) with Signal()
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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498ab321f3
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uart: add skeleton of new UART RTL, add COBS from fischermoseley/cobs
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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61e7d2e961
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ethernet: remove obsolete tests, fix naming
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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cdc611f88d
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ethernet: bugfix in read transmit logic
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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030011c1cb
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ethernet: use new bridge in EthernetInterface
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2026-03-17 11:23:01 -06:00 |
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Fischer Moseley
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1e5a247cf4
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meta: set ruff max line length to 100 characters
This should hopefully make the Amaranth source more readable, since indentation and the `m.d.sync +=` prefix take a bit of line space.
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2026-02-25 13:18:23 -07:00 |
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Fischer Moseley
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9611c0b554
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uart: fix #36, explicitly handle scientific notation in YAML config
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2025-04-06 18:28:29 -06:00 |
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Fischer Moseley
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f91f7c5fbb
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meta: add pre-commit, commit changes it makes
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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5759da568d
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tests: remove redundant test_toolchains test
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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9937269c19
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ethernet: add individual methods for each flavor of MII
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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ccecc16726
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ethernet: fix path to divider.sv
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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da21a3a414
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ethernet: load divider.sv via symlink
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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363bef8d87
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ethernet: add HWITL ethernet test
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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2761507803
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tests: add ethernet_io_core to build_examples test
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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cfbf372862
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uart: remove flaky nexys4ddr baudrate mismatch test case
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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d450221ed8
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tests: fix test_config_export
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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9d2ec45689
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uart: add stall_interval parameter and tests
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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cf62dd07bb
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logic_analyzer: default to immediate instead of single-shot, add intelligence to to_config()
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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2c124200da
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docs: autogenerate Python API docs, update IO core docs
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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1e7d4e92e7
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tests: fix bug where base_addr was not passed but not used
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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daedb91ff2
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meta: sort imports with ruff
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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b1caec9c57
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meta: switch from black to ruff
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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ecfbdaa86b
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cli: remove JSON loader, add test for instantiation generation
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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b31a655d58
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tests: include building examples in test suite
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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3ba93efd2f
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meta: expose Amaranth API via __all__
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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0d15abe4d1
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ethernet: update __init__ away from config dict
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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0bdfd9a5f7
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tests: fix mem_core_hw
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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165c6e46ca
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tests: fix logic_analyzer_sim
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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a01b6981e2
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tests: refactor to use Amaranth-native API
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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b20d7c7822
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logic analyzer: move __init__ away from config dict
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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743f434652
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meta: add boilerplate for Amaranth-native API
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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b87f8cbc48
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meta: move to lib.io and lib.mem, enable bidirectional mem tests on xilinx
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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753a3f9427
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meta: finish moving simulations to new async API
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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8fd943257c
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sim: update testbenches to async API
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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13bc196a34
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rename Nexys A7 to Nexys 4 DDR
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2024-05-12 10:35:18 -07:00 |
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Fischer Moseley
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bd452d94a4
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put test outputs in build/
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2024-03-06 16:40:54 -08:00 |
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Fischer Moseley
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71ec1174d1
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add parameterized HW tests for all memory core modes
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2024-03-06 14:53:27 -08:00 |
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Fischer Moseley
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d1a772784a
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add environment.sh for tool paths and serial ports
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2024-03-06 11:26:31 -08:00 |