Fischer Moseley
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7ed4a9e6b8
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polish uart testbenches
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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56b2442df7
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move uart code for verification to test/
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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d580419a5b
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remove lut_mem, clean up examples
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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112bd43963
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remove mention of wdata/rdata
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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ac23e8a599
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make functional sim run again
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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d95ca04dd5
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move macro functions to tasks, update to
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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6e9ca36559
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add test case for back to back messages
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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0c942fcb59
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finish cleaning up bridge_rx_tb
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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25b2ff0dd0
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add first round of tweaks to bridge_rx_tb
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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38f7ee86fa
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add uart_rx and refactor uart_tx and bridge_tx
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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df2dbf4ec6
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update makefile to reflect new paths
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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15aa5f469f
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add ethernet_tx_tb
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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2c461ed08d
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add working ethernet_tx testbench
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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9c5ea31d14
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enforce consistent naming of lut_mem module
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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b3d402c1f5
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refactor python/hdl structure
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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7cd8a2cfa5
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tidy up mac stack
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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c507f795f1
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add ethernet_tx/rx, semi-working in hardware
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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357b7eed94
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refactor logic analyzer a little, add ps2_decoder example, and implement trigger_loc
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2023-04-18 01:06:39 -04:00 |
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Fischer Moseley
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07624d83ee
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move back to iverilog 13 compatability
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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925fd915be
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update simulation syntax for iverilog 11 compat
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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1aa067b435
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update logic_analyzer_tb to use only generated HDL
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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a2ad90a66a
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modify sim and generator, seems to work in simulation
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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bdca8e01e7
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add boilerplate for new modules - just gotta rewrite the fsm
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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153ae7e3df
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video sprite example working! kinda frankensteined tho
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2023-04-13 17:02:55 -04:00 |
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Fischer Moseley
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5ceefc8da9
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this bram core has taken my soul
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2023-04-12 18:15:50 -04:00 |
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Fischer Moseley
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ba6100ce30
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import tutorial from yesterday, add mostly working bram core
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2023-04-12 11:47:50 -04:00 |
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Fischer Moseley
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3731305f63
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keep tidying bram core
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2023-04-10 18:03:02 -04:00 |
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Fischer Moseley
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db76ce3579
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reasonably tidy BRAM core - might be dependent on icarus 13
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2023-04-10 17:51:43 -04:00 |
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Fischer Moseley
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4837b2787a
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add (half) working BRAM core example
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2023-04-10 17:02:48 -04:00 |
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Fischer Moseley
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12f498dc9a
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add cursed BRAM core implementation
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2023-04-10 14:38:29 -04:00 |
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Fischer Moseley
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1710da6f87
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update makefile to represent new functional sim locations
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2023-04-09 22:33:58 -04:00 |
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Fischer Moseley
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353be7551e
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remove all narly verilog from python! 🤠
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2023-04-08 16:23:02 -04:00 |
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Fischer Moseley
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c604614428
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autogenerate logic_analyzer and sample_mem
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2023-04-03 23:15:09 -04:00 |
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Fischer Moseley
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0a4a1519c4
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clean up inferred BRAM, trim whitespace
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2023-04-03 21:20:58 -04:00 |
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Fischer Moseley
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8f08dffc70
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consolidate logic analyzer testbench
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2023-04-03 12:20:24 -04:00 |
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Fischer Moseley
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df4d243b9a
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refactor test structure
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2023-04-02 20:33:50 -04:00 |