Fischer Moseley
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b9a7e75355
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examples: fix #37, use proper indexing in Amaranth examples
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2025-04-06 20:15:08 -06:00 |
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Fischer Moseley
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9611c0b554
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uart: fix #36, explicitly handle scientific notation in YAML config
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2025-04-06 18:28:29 -06:00 |
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Fischer Moseley
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f91f7c5fbb
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meta: add pre-commit, commit changes it makes
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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9937269c19
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ethernet: add individual methods for each flavor of MII
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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a80bd399e7
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examples: determine divider.sv path at runtime
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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da21a3a414
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ethernet: load divider.sv via symlink
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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363bef8d87
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ethernet: add HWITL ethernet test
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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1a8292fb37
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ethernet: inject Ethernet module definition during elaboration
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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c65c8f1351
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ethernet: add initial (working!) amaranth-native design
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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9ac3181502
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examples: fix typos
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2024-11-07 09:50:55 -07:00 |
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Fischer Moseley
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1c1c514a39
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logic_analyzer: only set triggers if extra info provided in config
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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2c124200da
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docs: autogenerate Python API docs, update IO core docs
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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9f2dffb069
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examples: make verilog/amaranth versions of uart_logic_analyzer match
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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daedb91ff2
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meta: sort imports with ruff
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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b31a655d58
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tests: include building examples in test suite
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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8f45546b5a
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manta: fix code generation from config file, update tests
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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3ba93efd2f
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meta: expose Amaranth API via __all__
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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b20d7c7822
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logic analyzer: move __init__ away from config dict
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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743f434652
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meta: add boilerplate for Amaranth-native API
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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13bc196a34
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rename Nexys A7 to Nexys 4 DDR
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2024-05-12 10:35:18 -07:00 |
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Fischer Moseley
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978937e4bc
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modify example design naming convention
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2024-05-12 10:25:00 -07:00 |
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Fischer Moseley
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4ae061ffdc
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add missing .gitignore
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2024-03-07 09:21:40 -08:00 |
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Fischer Moseley
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04cfa41190
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add logic analyzer/io core ethernet example
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2024-03-07 09:18:30 -08:00 |
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Fischer Moseley
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60066ccdca
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add examples for the Nexys4DDR, bump version to 1.0.0
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2024-03-06 23:07:20 -08:00 |
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Fischer Moseley
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05b9b450e8
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add logic analyzer icestick example
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2024-03-06 22:05:24 -08:00 |
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Fischer Moseley
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21afbad7c4
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add icestick IO core example
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2024-03-06 21:47:03 -08:00 |
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Fischer Moseley
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bc616fd3bf
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inital source, imported from splat
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2023-12-28 14:22:29 -08:00 |
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Fischer Moseley
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c38c0f561a
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add automated test to read from output probe
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2023-09-04 23:03:49 -04:00 |
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Fischer Moseley
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b4fb79bc8e
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add write/readback tests, seems to pass
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2023-09-04 23:03:49 -04:00 |
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Fischer Moseley
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060583d8fc
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add working io_core autogeneration
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2023-09-04 23:03:49 -04:00 |
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Fischer Moseley
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78a7cce83a
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add logic_analyzer_uart example
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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44a8c57dc5
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swap to zipcpu uart_rx
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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3af6f6ff0c
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add block_mem_uart example
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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f5ef2bbb49
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remove more API calls that don't exist anymore
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2023-09-02 11:39:16 -04:00 |
Fischer Moseley
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4b9d941bc5
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fix API call that doesn't exist anymore, thanks Joe :)
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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c37a6e5e90
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move icestick build steps to makefile
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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0044ae5884
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merge nexys makefile targets
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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7e707e1fc1
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manually specify vivado path in makefile
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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d580419a5b
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remove lut_mem, clean up examples
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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8b9abd1b0b
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update examples, which appear to build :cowboy:
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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0840786914
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enforce consistent folder naming
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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112bd43963
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remove mention of wdata/rdata
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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adf355c633
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make examples build
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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f5caca613a
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simplify uart/ether APIs, improve lazy loading
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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ab58af0bfc
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add video_sprite_ether example
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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15aa5f469f
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add ethernet_tx_tb
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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9c5ea31d14
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enforce consistent naming of lut_mem module
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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54b97fd120
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add working ethernet verilog autogeneration woot woot :)
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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b3d402c1f5
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refactor python/hdl structure
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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7f9012b542
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tidy examples
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2023-04-28 14:57:36 -04:00 |