85229a6cdc
Add unsigned bit based power to continuous assignments.
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This patch adds the power operator for unsigned bit based values
in a continuous assignment. It also refactors the power code for
normal expressions and continuous assignments.
2008-02-06 14:38:16 -08:00
e82293c981
Add unsigned bit based power support to normal expressions.
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This patch adds bit based power support to normal expressions.
It also pushes the constant unsigned bit based calculation to
the runtime until the bit based method can be copied to the
compiler. Continuous assignments also need to use this type
of calculation.
2008-02-05 15:33:51 -08:00
d9ac146b8f
Spelling fixes
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only comments and documentation
some punctuation and capitalization for good measure
Changelogs are purposefully untouched
2008-01-29 20:24:24 -08:00
abfccb65e9
User defined functions take real arguments
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Allow user defined functions to take real value arguments and return
real value results in net contexts. Use the data type of the nets
attached to the ports to define the data types of the arguments and
return value.
2008-01-28 18:57:55 -08:00
c899a6a52e
Add %load/avp0 opcode and fix %load/vp0.
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This patch adds a new opcode %load/avp0 that is used to load a
word from an array and add a value to it. %load/vp0 was
changed/fixed to do the summation at the result width not the
vector width. This allows small vectors to index large arrays with
an offset. A few errors in the opcodes.txt file were also fixed.
2008-01-13 19:47:49 -08:00
8f519531f3
Optimize load-add with load/add instruction
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Where and expression is an immediate value added to a signal value,
it is possible to optimize them to a single instruction that combines
the load with an add at the same time.
2007-12-04 19:15:15 -08:00
7e59186f1e
Fixes for wide division/modulus.
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Wide division/modulus (more bits than unsigned long) gave incorrect
results when both the divisor and dividend where the same. They also
did not produce an error message when dividing by zero.
2007-11-05 20:24:33 -08:00
bef55d4426
Nets initialize with z value.
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At time zero, nets (not variables) need to be initialized with z
instead of x.
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-28 16:56:01 -07:00
ae82eccdc4
handle constant inf values.
2007-06-12 02:36:58 +00:00
611d2c81b3
Spelling fixes from Larry
2007-03-22 16:08:14 +00:00
fc9a90c9e0
Add support for edge sensitive spec paths.
2007-03-02 06:13:22 +00:00
d958a4a5af
Handle relink of continuous assignment.
2007-02-05 01:08:10 +00:00
91d84e7dc7
Major rework of array handling. Memories are replaced with the
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more general concept of arrays. The NetMemory and NetEMemory
classes are removed from the ivl core program, and the IVL_LPM_RAM
lpm type is removed from the ivl_target API.
2007-01-16 05:44:14 +00:00
316422d93b
Handle vpiRealVal reads of signals, and real anyedge events.
2006-12-09 19:06:53 +00:00
898b0e0365
Support release of a for/linked reg.
2006-08-04 04:37:37 +00:00
80f30be9d0
Add support for system functions in continuous assignments.
2006-06-18 04:15:50 +00:00
6f46d12e07
Add support for logic parameters.
2006-03-08 05:29:42 +00:00
2b8fd28a95
Force instruction that can be indexed.
2005-11-26 17:16:05 +00:00
35951510c5
Put vec8 and vec4 nets into seperate net classes.
2005-11-25 17:55:26 +00:00
bebcc05aab
Handle very wide % and / operations using expanded vector2 support.
2005-11-10 13:27:16 +00:00
ee22550047
Lazy processing of vvp_fun_part functor.
2005-09-20 00:51:53 +00:00
be73be8c98
Spelling patches from Larry.
2005-09-19 21:45:35 +00:00
bc489a7761
Bring threads into the vvp_vector4_t structure.
2005-08-27 02:34:42 +00:00
a8d49921ee
gcc4 compile errors.
2005-07-14 23:34:18 +00:00
3ac79c294a
Implement real valued signals and arith nodes.
2005-07-06 04:29:25 +00:00
de1dd2f2b3
Make bit masks of vector4_t 64bit aware.
2005-06-26 01:57:22 +00:00
6c8e1f7834
inline the vvp_send_vec4_pv function.
2005-06-24 02:16:42 +00:00
b58705b829
Inline more simple stuff, and more vector4_t by const reference for performance.
2005-06-22 18:30:12 +00:00
7091915b73
Reduce vvp_vector4 copies by using const references.
2005-06-22 00:04:48 +00:00
5513974b78
Optimize vvp_scalar_t handling, and fun_buf Z handling.
2005-06-21 22:48:23 +00:00
ad78af2f91
Inline some commonly called vvp_vector4_t methods.
2005-06-20 01:28:14 +00:00
1b30bac9f3
Optimize the LOAD_VEC implementation.
2005-06-19 18:42:00 +00:00
466ab5c2c7
Resolv do not propogate inputs that do not change.
2005-06-15 00:47:15 +00:00
21c7abf090
Accomodate fussy compilers.
2005-06-14 00:42:06 +00:00
80cac983c6
More unified vec4 to hex string functions.
2005-06-13 00:54:04 +00:00
668781788b
Support resistive mos devices.
2005-06-12 15:13:37 +00:00
a59f3b1fa6
Implement nmos and pmos devices.
2005-06-12 00:44:49 +00:00
42433f4df9
Add support for notif0/1 gates.
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Make delay nodes support inertial delay.
Add the %force/link instruction.
2005-06-02 16:02:11 +00:00
b6fd4f610b
Add a sign-extension node.
2005-05-24 01:43:27 +00:00
ed78c5b677
Force part base out of bounds if index is invalid.
2005-05-09 00:36:58 +00:00
7dd0d255a6
Add support for variable part select.
2005-05-08 23:40:14 +00:00
f6da64e2ec
ostream insert for vvp_vector4_t objects.
2005-05-07 03:14:50 +00:00
e9bf021f6c
vvp_fun_signal eliminates duplicate propagations.
2005-04-25 04:42:17 +00:00
a3f696cd06
Add vvp driver functor for logic outputs,
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Add ostream output operators for debugging.
2005-04-13 06:34:20 +00:00
fe91ebe77c
Default behavior for recv_vec8 methods.
2005-04-09 05:30:38 +00:00
573e07225d
Rework the vvp_delay_t class.
2005-04-03 05:45:51 +00:00
b7ef2fcb0a
Reimplement combinational UDPs.
2005-04-01 06:02:45 +00:00
53da6e9a33
Add support for LPM_UFUNC user defined functions.
2005-03-18 02:56:03 +00:00
313502f360
Implement VPI access to signal strengths,
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Fix resolution of ambiguous drive pairs,
Fix spelling of scalar.
2005-03-12 04:27:42 +00:00
c5e7e2ec0a
Signals may receive part vectors from %set/x0
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instructions. Re-implement the %set/x0 to do
just that. Remove the useless %set/x0/x instruction.
2005-02-14 01:50:23 +00:00
ff067bb959
tri0 and tri1 resolvers must replace HiZ with 0/1 after resolution.
2005-02-13 05:26:30 +00:00
355ead0002
Add debug dumps for vectors, and fix vvp_scaler_t make from BIT4_X values.
2005-02-12 06:13:22 +00:00
ca1bbc79a3
Add .repeat functor and BIFIF functors.
2005-02-07 22:42:42 +00:00
b48abb2148
Add wide .arith/mult, and vvp_vector2_t vectors.
2005-02-04 05:13:02 +00:00
018014368b
Add support for reduction logic gates.
2005-02-03 04:55:13 +00:00
84b3e8e2dc
Get .arith/sub working.
2005-01-30 05:06:49 +00:00
d51503ffd8
move AND to buitin instead of table.
2005-01-29 17:52:06 +00:00
a121e703f3
Add vector4 implementation of .arith/mult.
2005-01-28 05:34:25 +00:00
6a23f16860
.cmp/x supports signed magnitude compare.
2005-01-22 17:36:15 +00:00
1c3668ea7f
Reimplement comparators as vvp_vector4_t nodes.
2005-01-16 04:19:08 +00:00
9735b0e8b3
Add the .part/pv node and related functionality.
2005-01-09 20:11:15 +00:00
d5c33420ab
vvp_fun_signal propagates vvp_vector8_t vectors when appropriate.
2005-01-01 02:12:34 +00:00
34a14b983b
Implement .resolv functors, and stub signals recv_vec8 method.
2004-12-31 06:00:06 +00:00
1674d692b7
Add the part concatenation node (.concat).
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Add a vvp_event_anyedge class to handle the special
case of .event statements of edge type. This also
frees the posedge/negedge types to handle all 4 inputs.
Implement table functor recv_vec4 method to receive
and process vectors.
2004-12-29 23:45:13 +00:00
36f36bd2ac
Add basic force/release capabilities.
2004-12-15 17:16:08 +00:00
65e9b6be12
Rework of internals to carry vectors through nexus instead
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of single bits. Make the ivl, tgt-vvp and vvp initial changes
down this path.
2004-12-11 02:31:25 +00:00
Cary R
Larry Doolittle
Stephen Williams
steve