ee34ccec70
Update lz4 files from GTKWave
2014-11-29 07:36:44 -08:00
ac2e8dd6cd
Report that packed arrays can not currently be elaborated in all cases
2014-11-24 19:11:08 -08:00
cd992b4d5a
Add file/line information for parray data type.
2014-11-24 18:37:40 -08:00
754899c99e
Make asynchronous case statement synthesis more robust.
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Added various error/warning messages for behaviour not supported
in synthesis. Also give correct behaviour when multiple case item
expressions evaluate to the same constant value.
2014-11-09 20:20:03 +00:00
4e94b81a4b
On a 32 bit system you can print a 32 bit value as a long (verinum)
2014-11-05 14:43:58 -08:00
6948c27c2d
Enumerations are compatible if their type definitions match.
2014-11-04 15:05:49 -08:00
2e9c4cde55
More refined check for enumeration width and constant width
2014-11-04 12:10:38 -08:00
2e8c4e3dbc
Basic patch from github #44
2014-11-04 11:39:01 -08:00
cc9fcfd13d
Only a literal constant size has to match the enumeration width.
2014-11-03 19:46:10 -08:00
4660e0bf2f
Another tweak to the enumeration elaboration code
2014-11-02 20:26:36 -08:00
1e7509a021
Update enumeration elaboration checks
2014-11-02 11:45:19 -08:00
c2e53f0d63
Fix for br963 - vvp qpop instructions need to call thr_check_addr.
2014-11-02 15:36:52 +00:00
f171161822
Fix for br962 - pop from dynamic array is not padded to correct width.
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When the expression width is greater than the dynamic array width,
we need to generate code to pad the popped value to the correct
width.
2014-11-02 15:26:15 +00:00
0237297e93
Added pruning of case statement expressions.
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When unsized literals are used in case item expressions, it is likely
that the calculated expression width will be larger than necessary to
unambiguously select the correct case item (particularly when using
"strict" expression elaboration). This patch adds an optimisation
step that prunes the expressions to the minimum necessary width.
2014-11-02 13:02:57 +00:00
e38b5d9fb7
Eliminate unnecessary rerun of test_width in case statement elaboration.
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Also fix a typo in a comment.
2014-11-02 13:02:57 +00:00
9a471bd81c
Don't crash if there are problems elaborating an enumeration.
2014-10-31 20:08:05 -07:00
632e15a55c
Catch enumerations with the same name.
2014-10-31 20:06:28 -07:00
d4313dad75
Merge branch 'master' of github.com:steveicarus/iverilog
2014-10-31 18:09:29 -07:00
c25538d750
Pass the integer type for enumerations to the IVL target stage
2014-10-31 18:09:19 -07:00
871d447ff7
Reinstate error recovery for range expressions.
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If an error is found whilst elaborating a range expression in a signal
declaration, create a dummy range and continue elaboration. This stops
the compiler reporting an error every time that signal is referenced.
2014-10-31 21:42:23 +00:00
b286b76134
Fix null pointer dereference in pform debug output.
2014-10-31 18:40:51 +00:00
4f62a0d1f2
Check enum trimmed bits for values with undefined bits
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If an enumeration constant has undefined bits then we need to verify that
the bits that are trimmed match the MSB of the remaining bits.
2014-10-30 19:54:38 -07:00
e7df9774aa
When comparing that an enumeration is in range cast the value to 2-state
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When checking that an enumeration value is in range we need to cast it to
a 2-state value so that when we compare it we get a true or false value
instead of an undefined value. Undefined bits in the comparison return
undefined which is not logically false.
2014-10-30 18:23:47 -07:00
08afbde08d
Update cppcheck suppression file for tgt-vlog.
2014-10-30 18:23:39 -07:00
7ab0824adf
Fix for br961 - function return type elaborated in wrong scope.
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The return type of a function should be elaborated in the context of
the enclosing scope, not in the context of the function itself.
2014-10-30 21:09:17 +00:00
7fad4779c5
Add error recovery when elaboration of a type range fails.
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If elaboration of the msb or lsb expression in the range of a vector
type specification failed (due to an error in the Verilog code being
compiled), an assertion failure was being triggered when the compiler
attempted to evaluate the expressions. Bypassing the evaluation (and
using a default value) should allow us to recover from the error.
2014-10-30 20:42:12 +00:00
3e9c14060f
lexor handles arbitrary length defines in the precompiled_defiles file.
2014-10-25 09:48:11 -07:00
006aef93d0
Fix a reference to an undefined element.
2014-10-23 16:56:13 -07:00
a63ca15735
Add support for putting a single delay from the VPI
2014-10-18 18:27:39 -07:00
d139142c29
Merge pull request #47 from orsonmmz/concat
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Expression concatenation in VHDL
2014-10-18 15:13:50 -07:00
af85d44d9f
Add support for putting three and six delays from the VPI
2014-10-17 20:06:01 -07:00
c5e0507941
Fix the modpath edge and vpi_put_delay() code
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The code to get the correct modpath delay for a given edge had the X and Z
entries swapped.
When putting a delay from the VPI the 2 delay to twelve delay mapping was
incorrect and the to/from X delays were also not being calculated correctly.
2014-10-17 19:42:55 -07:00
c55a013162
vhdlpp: Support for integer() function.
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Note: I could not find any info about the integer() function, but it is
used in the VHDL standard packages (e.g. math_real, see:
http://www.csee.umbc.edu/portal/help/VHDL/packages/mathpack.vhd )
Real numbers are rounded, this is compatible with ModelSim behavior.
2014-10-17 14:53:59 +02:00
dfbca0b186
vhdlpp: Emit use_types in Architecture.
2014-10-17 14:13:06 +02:00
4a779f43bd
vhdlpp: Fix error message for 'right attribute.
2014-10-17 14:13:06 +02:00
97df6183a9
vhdlpp: Emit '-' std_logic value as 'x'.
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Note: It is not a direct ("don't care" vs "unknown"), but I could not
find anything that suits better.
2014-10-17 14:13:06 +02:00
95faed8e9d
vhdlpp: Added basic support for concatenated expressions.
2014-10-15 10:51:21 +02:00
76aab15798
vhdlpp: Minor code cleaning.
2014-10-15 10:51:21 +02:00
e896f0c8e6
Remove some compile warnings in the vhdlpp code
2014-10-14 09:03:42 -07:00
f36bebf0e1
Remove some compile warnings.
2014-10-13 16:31:53 -07:00
3fd622e4eb
vlog95: Add support for emitting global tasks and functions
2014-10-13 09:51:55 -07:00
da4200c5bd
Update lz4 files to the latest from GTKWave
2014-10-13 09:44:57 -07:00
712f394224
Elaborate classes in packages.
2014-10-10 18:53:53 -07:00
d6685f40a1
Merge pull request #46 from orsonmmz/range
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VHDL attributes: 'range, 'reverse_range, 'left & 'right
2014-10-10 17:23:59 -07:00
9ff9cbf4aa
vhdlpp: Smarter determining the direction in for loops.
2014-10-10 18:39:14 +02:00
a992f3ce7c
vhdlpp: Evaluation for 'left and 'right attributes.
2014-10-10 18:35:17 +02:00
1a4edcac48
vvp: Accepts continuous assignment for 2-state nets.
2014-10-10 16:16:46 +02:00
8cac72192f
vhdlpp: Fix array typedefs in packages.
2014-10-09 10:37:33 +02:00
7f6100be2a
vhdlpp: Emit VHDL 'integer' as SystemVerilog 'int'.
2014-10-09 10:29:14 +02:00
4b60d2737e
vhdlpp: Skip signed & unsigned in types dump in packages.
2014-10-09 10:28:35 +02:00
Cary R
Martin Whitaker
Stephen Williams
Maciej Suminski