ff067bb959
tri0 and tri1 resolvers must replace HiZ with 0/1 after resolution.
2005-02-13 05:26:30 +00:00
355ead0002
Add debug dumps for vectors, and fix vvp_scaler_t make from BIT4_X values.
2005-02-12 06:13:22 +00:00
ca1bbc79a3
Add .repeat functor and BIFIF functors.
2005-02-07 22:42:42 +00:00
b48abb2148
Add wide .arith/mult, and vvp_vector2_t vectors.
2005-02-04 05:13:02 +00:00
018014368b
Add support for reduction logic gates.
2005-02-03 04:55:13 +00:00
84b3e8e2dc
Get .arith/sub working.
2005-01-30 05:06:49 +00:00
d51503ffd8
move AND to buitin instead of table.
2005-01-29 17:52:06 +00:00
a121e703f3
Add vector4 implementation of .arith/mult.
2005-01-28 05:34:25 +00:00
6a23f16860
.cmp/x supports signed magnitude compare.
2005-01-22 17:36:15 +00:00
1c3668ea7f
Reimplement comparators as vvp_vector4_t nodes.
2005-01-16 04:19:08 +00:00
9735b0e8b3
Add the .part/pv node and related functionality.
2005-01-09 20:11:15 +00:00
d5c33420ab
vvp_fun_signal propagates vvp_vector8_t vectors when appropriate.
2005-01-01 02:12:34 +00:00
34a14b983b
Implement .resolv functors, and stub signals recv_vec8 method.
2004-12-31 06:00:06 +00:00
1674d692b7
Add the part concatenation node (.concat).
...
Add a vvp_event_anyedge class to handle the special
case of .event statements of edge type. This also
frees the posedge/negedge types to handle all 4 inputs.
Implement table functor recv_vec4 method to receive
and process vectors.
2004-12-29 23:45:13 +00:00
36f36bd2ac
Add basic force/release capabilities.
2004-12-15 17:16:08 +00:00
65e9b6be12
Rework of internals to carry vectors through nexus instead
...
of single bits. Make the ivl, tgt-vvp and vvp initial changes
down this path.
2004-12-11 02:31:25 +00:00
steve