Commit Graph

251 Commits

Author SHA1 Message Date
Stephen Williams 7f7decde03 Basic structure for emitting packages. 2013-06-12 14:09:07 -07:00
Stephen Williams d9fea802da Function declarations in packages
This is still basic. Definitions are still not done.
2013-06-12 14:09:07 -07:00
Stephen Williams 11682fc7eb Harmless cleanup of comments / initialization warnings. 2013-04-18 18:18:40 -07:00
Cary R d2928d500d Remove a few more compile error messages from RHEL5 2013-04-17 17:46:05 -07:00
Cary R 15379f1750 Remove some compile warnings 2013-04-17 17:13:22 -07:00
Stephen Williams bad8ed39c1 Parse VHDL subprogram bodies and return statements. 2012-11-03 09:54:07 -07:00
Stephen Williams 5651e6e001 Improve error handling. 2012-11-02 19:30:12 -07:00
Stephen Williams c14134aa2e Handle genvar variables in expressions.
In generate for blocks, there is a genvar that can be used in
expressions within the generate block. Generate this genvar in
the generated output, matched to the generate scope.
2012-09-07 15:14:48 -07:00
Stephen Williams 85e000ed0c Handle prefix expressions that include array index expressions. 2012-09-03 16:00:10 -07:00
Stephen Williams 7fad717a1e Redesign selected_name rule to better handle complex prefixes
Prefixes of hierarchical names are complex and cannot be handled
by simple strings, to the rules must be reworked.
2012-09-03 16:00:10 -07:00
Arun Persaud f5aafc32f9 updated FSF-address 2012-08-29 10:12:10 -07:00
Cary R 4313fbbf1f Fix space errors in various files 2012-08-16 11:13:32 -07:00
Cary R 1749d10966 Fix some clang/bison compile warnings. 2012-08-06 15:49:11 -07:00
Larry Doolittle befff82655 Spelling fixes
Comments and debug messages.
2012-07-27 18:25:32 -07:00
Stephen Williams 621c09105c Sort the typedef emits so that types are emitted in the order used.
It is common for typedefs of complex types to use further typedefs.
Emit the type definitions depth first so that the types that are used
are defined first. This reduces the need for pre-declaration of types.
2012-05-22 17:31:27 -07:00
Stephen Williams 369a0b9eca VHDL named types work in more places. 2012-05-22 17:31:27 -07:00
Stephen Williams 4748f0cb5e Handle incomplete type declarations
Use these in the package library to allow for arbitrary mixing
of type declaration and use. This makes writing libraries much
easier.
2012-05-22 17:31:27 -07:00
Stephen Williams 039e6014fe Rework VType::emit_def methods / use packed arrays to implement arrays.
VHDL arrays are more like SV packed arrays, so use packed arrays
to implement them.
2012-05-22 17:31:26 -07:00
Stephen Williams 63b7fe059d Reword concat to handle aggregate arguments.
When concatenation expressions have aggregate arguments, we need to
get the type of the result down to the aggregate expressions so that
it can know how to interpret the elements.
2012-05-22 17:31:26 -07:00
Stephen Williams 67af96fee7 Module output ports use data_type_or_implicit
This cleans up the parsing of module output ports, allows for more
complex types on the ports, and fixes some bugs.
2012-05-22 17:31:26 -07:00
Stephen Williams 7e202bb5ca Fix emit of struct ports/declarations. 2012-05-22 17:31:26 -07:00
Stephen Williams 71d2401221 Handle VHDL records.
Elaborate records and emit them as packed SV records. Also handle
record members so handle name prefixes.

While we are at it, handle some cases of array aggregate expressions.
2012-05-22 17:31:26 -07:00
Stephen Williams ae06863db1 Elaborate prefix names which may be structure variables. 2012-05-22 17:31:26 -07:00
Stephen Williams a5458828cd Some vhdl parser error handling. 2012-05-22 17:31:26 -07:00
Stephen Williams 021d944a30 Probe type of ExpName with a record prefix. 2012-05-22 17:31:25 -07:00
Stephen Williams 7eb89c5548 Parse name prefix syntax for record member reference.
When signals/variables are records, they are often referenced by
their members, using a prefix.name syntax. Parse that syntax and
generate "sorry" messages in elaboration.
2012-05-22 17:31:25 -07:00
Stephen Williams 5e7f61ea42 VHDL process sensitivities go to the end of each iteration 2012-05-22 17:31:25 -07:00
Stephen Williams 9b816f6478 Add support for nested when/else expressions. 2012-05-22 17:31:25 -07:00
Stephen Williams 1249b5dd32 Initial support for if_generate syntax. 2012-05-22 17:31:25 -07:00
Stephen Williams 0775e36a67 Properly elaborate argument types for binary relation expressions.
The argument types of binary relation expressions are decoupled
from the return type for the expression itself.
2012-05-22 17:31:25 -07:00
Stephen Williams ed3da959f3 Support types in packages.
Types declared in packages should be written into the package library.
2012-05-22 17:31:25 -07:00
Stephen Williams 79435924f2 Move some VType::show methods to ::write_to_stream methods. 2012-05-22 17:31:25 -07:00
Stephen Williams 9ed56a6354 Parse record types, and some new aggregate types. 2012-05-22 17:31:25 -07:00
Larry Doolittle 84f14dbc81 Spelling fixes to vhdlpp tree
Mostly comments as usual, but one error message is changed.
2012-05-17 16:42:03 -07:00
Cary R 9c99bce054 Update lex/yacc builds to be consistent and to support parallel builds
Not all the lex/yacc (flex/bison) targets were using a consistent syntax.
This patch fixes that and explicitly serializes the *.c/*.cc and *.h build.
Not doing this was causing problem when using make -j. The issue appears to
be that if two targets are specified for a rule (e.g. file.cc file.h: file.y)
make does not realize they are both built by the same call so the rule is
executed twice. Once for the .cc target and once for the .h target. This is
not a problem for a serial build. To work around this only use the .c/.cc
file in the main target and then make the .h file depend on the .c/.cc file
as a sub-target.
2012-01-04 18:21:40 -08:00
Cary R aedbda5a75 Identifiers need to be deleted with delete[]
This patch fixes a mismatch in the delete style.
2011-12-18 16:45:08 -08:00
Cary R ed13de131d Use mkdir() instead of _mkdir() for MinGW
MinGW-w64 requires the use of mkdir() and MinGW-w32 appears to support
both so use mkdir() to allow compilation to work with both versions.
2011-12-18 11:43:35 -08:00
Cary R 8df745a281 Remove SV include file and vhdlpp with make uninstall 2011-12-14 18:39:27 -08:00
Cary R cc5efa45ba Fix two bugs and use the more efficient !empty() vs size() > 0
These two bugs were found with a recent cppcheck addition. It also
changes one occurrence of size() > 0 for the more efficient ! empty().
2011-11-22 19:44:55 -08:00
Cary R bcb963a235 Fix Cygwin compile problem (replace abs() call with ?:
This patch fixes a compile problem in Cygwin where there are two
definitions for abs() that do not match so the C++ code doesn't know
which one to call. To avoid the whole mess replace the call to abs()
with the appropriate ?: construct.
2011-11-17 14:30:33 -08:00
Stephen Williams 5e4c0c9783 Merge branch 'master' into work9 2011-11-06 10:27:40 -08:00
Stephen Williams 8e0beff3ab Handle arrays of vectors in VHDL types.
This incidentally adds binding of generic to generic instantation.
2011-11-06 09:01:02 -08:00
Stephen Williams c1be255844 Fix dump display of array ranges. 2011-11-05 17:22:30 -07:00
Stephen Williams cc508d1626 Support write_to_stream for arithmetic expressions. 2011-11-05 15:55:41 -07:00
Stephen Williams 2063c5ee9d Support VHDL user defined array types. 2011-11-05 15:55:17 -07:00
Martin Whitaker 58d182bdf3 Compiler fixes for MinGW.
In MinGW, when parameters are passed to vhdlpp by ivlpp, single quotes
are treated as ordinary characters. Use double quotes instead, as is
done in the driver.

Also, MinGW does not have a standard mkdir() function, so we need to
convert calls to mkdir() into calls to _mkdir().
2011-11-03 19:11:28 -07:00
Stephen Williams 98d928f6e0 Add support for VHDL for-generate 2011-10-30 17:10:19 -07:00
Stephen Williams 5724f71339 Elaborate expressions for entity generics. 2011-10-29 17:07:03 -07:00
Stephen Williams 15da45f7cb VHDL initialization expressions for signals. 2011-10-29 17:06:40 -07:00
Stephen Williams 37ef14b1c8 Implement VHDL conf_std_logic_vector() as SystemVerilog size cast. 2011-10-29 14:47:39 -07:00
Stephen Williams 4f98a6d181 Rewire VHDL addition expression parsing.
The VHDL LRM addition expression rules are ... different.
2011-10-23 17:31:58 -07:00
Stephen Williams 2be682f8a5 Support VHDL component instantiations with generics as Verilog parameters. 2011-10-23 17:08:48 -07:00
Stephen Williams eeeadea3ac Fix recently broken write of vhdl packages to work space. 2011-10-16 12:18:34 -07:00
Stephen Williams a109df04bb Proper expression type for vhdl relation expressions. 2011-10-16 11:02:07 -07:00
Stephen Williams 93e5a72d84 Get parameter output syntax right for vhdlpp. 2011-10-16 11:01:32 -07:00
Stephen Williams d9acfe57b1 Put off array bound evaluation / describe entity generics as parameters
Entity generics are easily implemented as module parameters, so make
it so. Give the parameters their default values from the generic declaration.

Array bounds may use values that cannot be evaluated right away, so
put off their evaluation.
2011-10-15 17:41:48 -07:00
Stephen Williams a6f63b8a54 Parse generic clause in entity headers
The generic clause can create named generics in entities. This patch
gets the parser support for them working, even though they cannot
yet evaluate.
2011-10-15 09:49:24 -07:00
Cary R 209a78a439 Remove a more cppcheck warnings in vhdlpp.
This patch removes a few more cppcheck warnings in the vhdlpp directory.
2011-10-14 18:40:39 -07:00
Cary R 8f17e79b7e Remove a few cppcheck warnings.
This patch removes a few cppcheck warnings.
2011-10-14 18:40:24 -07:00
Stephen Williams 6268db6e68 Handle simple type declarations. 2011-10-09 15:25:35 -07:00
Stephen Williams 30cfcbe2dc Rework elaborate/emit of types.
This rework is needed to reasonably handle new types, like enums.
2011-10-02 10:56:00 -07:00
Stephen Williams 271aaf6376 Parse enumeration type declarations. 2011-10-01 17:04:04 -07:00
Stephen Williams 8003382b3e Elaborate and emit case statements. 2011-10-01 11:45:28 -07:00
Martin Whitaker c59d27e19f Remove more clang warnings.
clang warns that the yyinput function generated by flex is never used.
2011-09-25 10:14:16 -07:00
Cary R eab5bacf9f Remove clang/clang++ warnings.
This patch makes the code consistently use struct/class in the C++ files,
it removes a couple shadow warnings and where a class pointer is passed to
the C routines, it defines the pointer as a class for C++ and as struct for
C and it removes a namespace std duplication.
2011-09-25 10:14:04 -07:00
Stephen Williams 52019b0e55 Merge branch 'master' into work8 2011-09-18 19:48:50 -07:00
Stephen Williams 88cce86c63 Emit code for the to_unsigned() bulit-in function. 2011-09-18 19:31:28 -07:00
Stephen Williams 873a447b5c Evaluate VHDL <name>'length attribute at compile time. 2011-09-18 17:45:06 -07:00
Stephen Williams 677a22d353 Generate code for vhdl for loops. 2011-09-18 15:51:31 -07:00
Stephen Williams f0e61a1db7 Basic vhdl elaboration for unary not operator. 2011-09-18 15:13:30 -07:00
Stephen Williams 4d445dc269 Fix parse of unnamed processes. 2011-09-18 09:37:11 -07:00
Stephen Williams 1d02f89a09 Handle vhdh array aggregate expressions.
Support the more general case of explicit element expressions
defined at various index positions, mixed with "others" records.
2011-09-11 17:08:22 -07:00
Stephen Williams 3497e2e663 Distinguish bit selects of entity ports from function calls.
Besides variables and signals, a name with a bit select may
be an entity port. Distinguish these from function calls.
2011-09-11 15:28:58 -07:00
Cary R ca6af1c20d Fix some space issues. 2011-09-11 11:41:38 -07:00
Stephen Williams 563d73e7d9 Index/part select of VHDL l-values changes expression type
The changed expression type impacts how code is generated
for the r-value expression.
2011-09-03 17:57:37 -07:00
Stephen Williams 6d28c989ce Handle the basics of aggregate expressions
This takes care of the parser support, and a shell of the
elaboration. Handle some special cases all the way through.
2011-09-03 17:11:55 -07:00
Stephen Williams 4464c5849b Handle a few built-in functions internally.
The "unsigned" and "std_logic_vector" functions are internal
functions and VHDL and can be handled internally in the code
generator.
2011-08-28 15:30:45 -07:00
Stephen Williams 7556a37859 Parse function calls, and detect type case expressions.
Type cast expressions and some function calls are syntactically
identical to array element select, so we can only tell the difference
by looking up the name of the identifier being selected. If it is a
type name, then create an ExpCast instead of an ExpName object.

Also, parse and emit vector part selects.
2011-08-21 16:52:18 -07:00
Stephen Williams e6a9b5532a Report some missed emit error count. 2011-08-21 16:40:06 -07:00
Stephen Williams a46c66130b Emit VHDL symbols as escaped identifiers 2011-08-20 12:11:49 -07:00
Stephen Williams 78788d17fe Translate VHDL string literals to bit vectors 2011-08-20 11:11:47 -07:00
Stephen Williams 13c17a2485 Fix broken creation of ExpString. 2011-08-17 20:53:49 -07:00
Stephen Williams f5220c54f1 Handle variables in process statements
Parse variables declared in the declaration section of process
statements, and support variable assignment statements.
2011-08-17 20:19:15 -07:00
Stephen Williams 3e3b83da30 Add some detail on how libraries work. 2011-08-05 12:11:54 -07:00
Stephen Williams f2629d53a2 Add VHDL support for named libraries
Named libraries are similar to the work library, but they are not
written to implicitly, or imported implicitly. They are only brought
in by a "library" clause, the the packages within the library are
brought in by a "use" clause.
2011-07-30 15:04:07 -07:00
Cary R 72769146ee Remove all the user code compilation warnings
Remove all the compilation warnings that are from user changeable code.
There are still some warnings related to the flex generated lexor code.
2011-07-30 09:37:14 -07:00
Cary R de356b03c8 Fix most of the cppcheck warnings in the vhdlpp directory.
Mostly using size() vs empty() in the STL and a missing initialization.
2011-07-30 09:35:12 -07:00
Cary R 836e61e878 Fix spacing issues in the code.
Remove space at the end of line and space before tab since they serve
no purpose.
2011-07-30 09:33:28 -07:00
Pawel Szostek 547ea61be8 Delete dynamically allocated objects in vhdlpp 2011-07-28 15:03:28 -07:00
Stephen Williams fcecfc065c Handle bit types in package library stream. 2011-07-24 16:16:01 -07:00
Stephen Williams 521005caf6 Add +vhdl-work+ control to the config file.
Presumably, the user will want the ability to explicitly set the
working library location, so create a +vhdl-work+ plusarg setting
for exactly that purpose.
2011-07-24 15:24:32 -07:00
Stephen Williams 9ee938f0b4 Replace package in work library when I get a new one. 2011-07-24 11:06:59 -07:00
Stephen Williams 116d9f5f54 Merge branch 'master' into work7 2011-07-24 11:06:22 -07:00
Pawel Szostek 981425fcce Add semantics check in component instantiation
There have been applied rules for port and signal
association in component instatiation statements
described in the VHDL standard.
2011-07-24 10:14:41 -07:00
Pawel Szostek e19089e838 Use multimap in VHDL Component Instantiations
Port map aspects were held in std::maps. Because
of that, in case of multiple assignments to the same
port, some assignments were lost and in effect vhdlpp
produced correct verilog code from a buggy VHDL.

Std::map was replaced by std::multimap. Thanks to it
we can gather this multiple assignments and detect them
in the elaboration phase.
2011-07-24 10:08:14 -07:00
Pawel Szostek 50f7e1b69e Add parser cleanup to vhdlpp
This commit adds removal of global objects in
the execution of vhdlpp. This includes deleting
design entities and the global parse scope.
2011-07-24 10:03:03 -07:00
Pawel Szostek eb98ed9ce2 Add additional deletion in VHDL classes' destructors
Delete dynamically allocated objects in ScopeBase,
Architecture, ComponentInstatiation, Entity and Package.
2011-07-24 09:58:57 -07:00
Pawel Szostek a8fae6bbf7 Use stl algorithms and templates in ScopeBase destructor
This patch applies a more sophisticated method for
cleaning containers in VHDL ScopeBase class.
2011-07-24 09:57:20 -07:00
Pawel Szostek a5ca9ea8be Use separate containers for current and previous scopes
This patch introduces in ScopeBase separate containers
for declarations coming from the current scope and from
the previous scopes.
Until now, in one scope, all objects were kept in an stl map.
When a scope was created inside other scopes, a shallow
copy of the map was made. This solution was nice for
name shadowing (in new scopes, when a name was
encountered, the old objects were overridden by a new
one), but didn't allow for distinguishing where the objects
were allocated. As a result, it is impossible to know who
the owner is and who should delete them.

In this commit ScopeBase gets two containers: for old
and new objects. If a ScopeBase is made from another
ScopeBase object, all objects from the copied object
go to an old_XXX container, where XXX depends on the
type of the copied objects. When a ScopeBase object
is deleted, the objects from new_XXX are deleted and
the ones from old_XXX are not touched.

This patch adds some complexity to the internals
of ScopeBase, but leaves its interface unchanged.
2011-07-24 09:53:06 -07:00
Pawel Szostek 3764216a88 Use stl stack for for carrying scopes
This is rather a cosmetic change. The patch changes
the container used for stack of scopes from std::list
to std::stack. It suits this particular application
a bit better.
2011-07-24 09:50:31 -07:00