This implementation works by detecting assignments
to constant properties in elaboration. Allow initializer
assignments to assign to the constant, error all other
assignments, and otherwise treat the constant like any
other property.
Class constructors are the "new" method in a class description.
Elaborate the constructor as an ordinary method, but the only
way to access this method is to implicitly call it. The elaborator
will take the constructor call and generate a naked "new" expression
and implicit constructor method call with the object itself as the
return value.
Rework lexical support for PACKAGE_IDENTIFIER so that the lexor
can help with package scoped identifiers.
Pform package types and package functions up to elaboration.
This patch adds support for bool/bit vector types on the LHS of
a parameter declaration and ensures implicit casts in parameter
declarations are performed where necessary.
A package can have parameters, but it does not have specparams or
keep the order the parameters are defined. This patch skips these
items if the scope is not a Module.
This was temporarily implemented to just copy definitions to the
local scope, but the better method is to create a PEIdent that has
the package attached to it.
The parser does not distinguish between module and UDP instances, so
a UDP delay is handled by the rules used for parsing module parameter
overrides. Although these rules had been relaxed to accept the case of
a simple decimal value (e.g. #10), they did not allow a simple real
value (e.g. #0.1).
Implement through the ivl core to the ivl_target.h API.
Also draft implementation of creating and storing arrays
in the vvp runtime and code generator.
In vvp, create the .var/str variable for representing strings, and
handle strings in the $display system task.
Add to vvp threads the concept of a stack of strings. This is going to
be how complex objects are to me handled in the future: forth-like
operation stacks. Also add the first two instructions to minimally get
strings to work.
In the parser, handle the variable declaration and make it available
to the ivl_target.h code generator. The vvp code generator can use this
information to generate the code for new vvp support.
The parser had been changed to support null statements in sequential
and parallel blocks (a feature introduced in SystemVerilog), but was
not supported in elaboration, leading to a compiler crash. This patch
fixes this by discarding the null statements during parsing.
Making the scope type NESTED_MODULE was just plain wrong, because
it didn't really encapsulate the meaning of program blocks OR
nested modules. So instead create nested_module() and program_block()
flags and use those to test scope constraints.
An important advantage of program blocks is its ability to nest
within a module. This winds up also allowing modules to nest, which
is legal but presumably less used feature.
This patch extends the compiler to support all specparam declarations
allowed by the 1364-2005 standard. For compatibility with other
simulators, it allows specparam values to be used in any constant
expression, but outputs a warning message and disables run-time
annotation of a specparam if it is used in an expression that must
be evaluated at compile time.
This is a cleanup in preparation for better support of range lists.
(cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68)
Conflicts:
PTask.h
elab_scope.cc
elab_sig.cc
parse.y
pform.cc
pform.h
pform_types.h
Signed-off-by: Stephen Williams <steve@icarus.com>
The SystemVerilog unbased literals (e.g. '0, '1, etc.) are expected to be
used standalone and cannot take a size. This patch modifies the parsing
code to give a good error message when this is done.
Class methods belong in a class scope, not the containing module.
So create a lexical scope that carries tasks and functions and
create a PClass to represent classes.
Tasks call arguments may be dropped in favor of default values.
Allow for that in the syntax. This requires a little handling
of the non-SystemVerilog case during elaboration.
Class names can be declared early, before definitions, so that the
name can be used as a type name. This thus allows class definitions
to be separate from the declaration. This creates some complexity in
the parser, since the lexor knows about the class names.
This adds the vector_type_t and real_type_t types to handle
vector and real types in tf_port items. This cleans up a lot
of the parsing for these items.
During parse/pform processing, convert increment statements to
the equivalent compressed assignment statement. This is less weird
for elaboration processing and better expresses what is going on.
This gets me to the point where the parser stashes a defined type,
and the lexical analyzer uses the type names to differentiate
IDENTIFIER and TYPE_IDENTIFIER.
Parse typedefs with structs and enums, but give a sorry message,
because they are not yet supported. Rearrange some of the parse
rules for variables in order to increase comonality with the
typedef rules.
The standard allows a parameter (or localparam) declaration of the
form "parameter signed my_param = ...". The parser currently rejects
this. A small adjustment is also required in the parameter evaluation
code to correctly apply the type.
This patch adds wreal support when in Verilog-AMS mode. It doesn't add
everything that is shown in the Verilog-A standard.
It adds the following:
Declaring a wreal net.
Declaring a wreal net with an initialization.
Declaring a wreal input/output using ANSI syntax.
Declaring a wreal input/output using the old style.
Declaring wreal inout ports are also allowed and parsed, but the
compiler does not know how to handle this. There are other deviations
from what is shown in the Verilog-A standard, but this should get most
of the syntax people actually use.
It is legal for a named block to contain variable definitions and
no statements. This patch fixes this for both style of blocks. It
also organizes the block parsing code to be a bit more clear, adds
an error case for fork/join and changes on check for size() > 0 for
the more efficient ! empty().
This patch fixes a few more bugs in the enumeration code.
It add support for saving the file and line information to make
diagnostic messages better.
It updates some of the compiler warning messages to use the file
and line information.
It passes if the enumeration type is signed all the way to the
code generators.
It fixes the parser to correctly have the range after the signed
designation for the vector types.
It adds a warning that vvp does not currently support a negative
two state enumeration value.
Add a new IVL_PR_FINAL process type.
Add a flag to NetScope in_final_ which is set when elaborating the
statement of a final procedure.
Add checks during statement elaboration for invalid statements in a
final procedure, similar to checks for statements in functions.
Do a final check to make sure no final blocks have delays.
In the vvp runtime, use "$final" as the flag for the thread created by
the final procedure. During compilation, instead of adding such a
thread to the sched_list, add it to a new schedule_final_list that
mirrors the schedule_init_list, but is run at the end of simulation.
This patch adds support for increment/decrement operators as an
expression. The operations on real and vector slices have been
disabled for now.
These operators can be used as in independent statements. However, the
corresponding support is not added in parser.
Changes since V2:
- Additional error checking in elaboration to deny operation on vector
slices and real (suggested by Martin)
Changes since V1:
- Use 'i' and 'I' for increment (suggested by Cary)
- Evaluate sub-expression once (suggested by Cary and Stev)
- Add necessary checks during elaboration to ensure that the
expression is valid (suggested Stev)
- Proper width handling with vectors (suggested by Martin)
Signed-off-by: Prasad Joshi <prasad@canopusconsultancy.com>
This patch adds code to check for a negative or undefined value used in
an enumeration sequence name, it verifies that the count in an enumeration
sequence name is not zero and allows more decimal constant values in the
enumeration sequence name..
SystemVerilog extended the assignments operator support to C-like
assignment operators and special bitwise assignment operators.
For example:
a += 1;
a -= 1;
The list of these operators can be found in SV LRM (1800-2009)
section 11.4.1.
NOTE: I fixed a few parts of this. In particular, the PEBShift
class is used for shift operators.
Acked-and-Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
pow(int, int) is ambiguous since it could use the double version from
the math library or the verinum version. This patch makes it obvious that
we want to use the double version.
SystemVerilog has support for time literals. The time literal for
example #10ns, adds a delay of 10ns no matter the time unit currently
in effect. For more details please refer to
http://iverilog.wikia.com/wiki/Projects#SystemVerilog_Style_Time_Literals
Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
A bit/logic output type in a module initially is defaulted to as a
variable. Depending on how they are used in the module, the type
changes accordingly.
For example
module test(output logic l);
assign l = '0;
endmodule
The variable 'l' would be promoted to a Net data type, when the
'assign' statement is encountered.
Acked-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
The module declaration should allow initialization of the bit and
logic data types.
For example:
$ cat clkgen.sv
module clkgen(output logic clk = 0, output bit p = 1);
initial begin
#200;
$display("p = %b", p);
$finish;
end
initial forever #10 clk = ~clk;
endmodule
$ iverilog -g 2009 clkgen.sv
$ ./a.out
p = 1
Suggested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
SystemVerilog allows passing the 'bit' and 'logic' arguments to a
function. The patch adds support for parsing these function
definitions. The 'bit' data type is treated as boolean, whereas 'logic'
data type remains as logic.
Acked-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
The patch allows parsing of function definitions which do not have
explicit data type or range. The default return data type is assumed
to be reg unsigned and the default range is 0.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Verilog allows returning variables of 'reg' type. The icarus verilog
implicitly assumes the default returned type of the function as
'reg unsigned'. The patch allows to explicitly specify the 'reg' return
type.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Verilog allows user to define variables of primitive types. The patch
adds support for defining variables of type 'logic'. The data type
'logic' is the only primitive data type which supports defining ranges.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Verilog allows user to define variables of primitive types. The patch
adds support for defining variables of type 'bit'. The data type 'bit'
is the only primitive data type which supports defining ranges.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
If there are attributes attached to a module port declaration them
pform_bind_attribute() which is called from pform_module_define_port()
will delete the attribute list. They do not need to be deleted locally.
IEEE 1800-2005/9 says "each fixed-size dimension shall be represented by
an address range, such as [1:1024], or a single positive number to
specify the size of a fixed-size unpacked array, as in C. In other
words, [size] becomes the same as [0:size-1]."
This patch implements that translation in the parser. It issues a
warning when doing so when the generation flag is less than 2005-sv.
Stephen Williams
Cary R
Martin Whitaker
Arun Persaud
Martin Whitaker
Larry Doolittle
Jared Casper
Prasad Joshi
Prasad Joshi