Commit Graph

37 Commits

Author SHA1 Message Date
Larry Doolittle e9fda22ad9 Spelling fixes
Mostly then/than confusion.  All comments or README files,
except for one user-visible change in a tgt-vlog95 error message.
2011-03-14 16:28:36 -07:00
Cary R 1993bf6f69 Remove malloc.h support and for C++ files use <c...> include files.
The functions (malloc, free, etc.) that used to be provided in
malloc.h are now provided in cstdlib for C++ files and stdlib.h for
C files. Since we require a C99 compliant compiler it makes sense
that malloc.h is no longer needed.

This patch also modifies all the C++ files to use the <c...>
version of the standard C header files (e.g. <cstdlib> vs
<stdlib.h>). Some of the files used the C++ version and others did
not. There are still a few other header changes that could be done,
but this takes care of much of it.
2010-06-01 08:56:30 -07:00
steve e4ae832153 Clean up spurious trailing white space. 2004-10-04 01:10:51 +00:00
steve 0fd5a79760 Cleanup of warnings. 2004-02-15 18:03:30 +00:00
steve 534a656be8 devices need show_cmp_gt 2003-11-12 03:20:14 +00:00
steve e561819179 Add synthesis support for synchronous reset. 2003-08-15 02:23:52 +00:00
steve 7734ba99fc Generate MUXF5 based 4-input N-wide muxes. 2003-07-04 00:10:09 +00:00
steve eb605694eb More xilinx common code. 2003-07-02 03:02:15 +00:00
steve b810556d3f Remember to set INIT on wide-or trailing luts. 2003-07-02 02:58:18 +00:00
steve 5314ec373b lut3 for 3input wide or. 2003-06-30 19:21:21 +00:00
steve 03089bdbf3 Add support for wide OR/NOR gates. 2003-06-28 04:18:47 +00:00
steve 253f3bc660 Add Xilinx support for A/B MUX devices. 2003-06-26 03:57:05 +00:00
steve 0e797dc7bc Virtex and Virtex2 share much code. 2003-06-25 02:55:57 +00:00
steve f7162eb538 Spelling fixes. 2003-06-25 01:49:06 +00:00
steve 79248d0592 Add ivl_synthesis_cell support for virtex2. 2003-06-24 03:55:00 +00:00
steve 9ceaaa5faf ivl_lpm_name is obsolete. 2003-02-26 01:24:35 +00:00
steve 751e4e4c79 Fix instanceRef spelling. 2002-11-24 02:26:14 +00:00
steve 9a3c9507ed Handle wide AND/NOR devices with Virtex carry logic. 2002-11-22 05:46:06 +00:00
steve d71d52bfe9 Implement bufif1 as BUFT 2002-11-22 01:45:40 +00:00
steve fe6756eb07 Fix bottom bit of ADD/SUB device. 2002-11-01 02:36:34 +00:00
steve 1298656c22 Fix up left shift to pass compile,
fix up ADD/SUB to generate missing pieces,
 Add the asynch set/reset to DFF devices.
2002-10-30 03:58:45 +00:00
steve ae27165ffe Add Virtex code generators for left shift,
subtraction, and GE comparators.
2002-10-28 02:05:56 +00:00
steve 9f1ce170e6 Generate code for 8:1 muxes msing F5 and F6 muxes. 2002-09-15 21:52:19 +00:00
steve 327c8826f4 Generate Virtex code for 4:1 mux slices. 2002-09-14 05:19:19 +00:00
steve 52bf4e613f conditional ident string using autoconfig. 2002-08-12 01:34:58 +00:00
steve aca1dcf848 Add missing Log and Ident strings. 2002-08-11 23:47:04 +00:00
steve 36d36d99f3 Generate BUF devices for bufz logic. 2001-10-11 00:12:28 +00:00
steve 606eb2b3cd Support the cellref attribute. 2001-09-16 22:26:47 +00:00
steve cefbb635c1 Suppor the PAD attribute on signals. 2001-09-16 01:48:16 +00:00
steve b2b8b89cd8 Make configure detect malloc.h 2001-09-15 18:27:04 +00:00
steve 92760f2c5f Support != in virtex code generator. 2001-09-15 05:06:04 +00:00
steve 9fda809fa6 Add XOR and XNOR gates. 2001-09-14 04:17:20 +00:00
steve 5976e7078c Xilinx uses GROUND and VCC as pin names for the
GND and VCC devices.

 Connect the top end of the EQ chain to the MUXCY
 instead of to the LUT. The MUXCY has the real output.
2001-09-12 04:35:25 +00:00
steve da9a84ed84 Use carry mux to implement wide identity compare,
Place property item in correct place in LUT cell list.
2001-09-11 05:52:31 +00:00
steve 167f94bdbf Add 4 wide identity compare. 2001-09-10 03:48:34 +00:00
steve 4507351d48 Virtex support for mux devices and adders
with carry chains. Also, make Virtex specific
 implementations of primitive logic.
2001-09-09 22:23:28 +00:00
steve acde444439 Separate the virtex and generic-edif code generators. 2001-09-06 04:28:39 +00:00