55747bf79d
Refactor signdness changing code into a single function
...
This is the code that generated calls to signed/unsigned in
the VHDL output.
2008-07-08 13:07:11 +01:00
1cd7689d03
Fix casting with signed/unsigned expressions
...
Previously the code generator tried to infer the VHDL types. Now it
takes a much more dumb approach and forces the VHDL type to be
the same as the ivl type (derived from ivl_expr_signed and
ivl_expr_width) in the expression tree. This works much better :-)
2008-07-08 12:58:50 +01:00
bd5cc96956
Correct vector sizes for bit select
2008-07-08 00:20:31 +01:00
4777966b4c
Bit select bug fixes
2008-07-07 21:19:59 +01:00
47db80315c
Add sign extension LPM
2008-07-07 19:27:52 +01:00
3987e0753d
Fix case where booleans are compared against vectors
2008-07-07 16:31:27 +01:00
4db5b9d7ed
Add unary OR/NOR
...
These are currently implemented with reference to an external
Reduce_OR function
2008-07-07 15:23:57 +01:00
bdf5ee7ab7
Concat LPM
2008-07-07 14:48:57 +01:00
ebaa4c7d5d
Implement assignment to part select properly
...
Previously the base of the lval was ignored, this ensures
the correct assignment is generated.
2008-07-07 11:00:27 +01:00
c33600bcc3
Add concatenation operator
2008-07-06 18:21:34 +01:00
5aeff6d47d
Merge blocking and non-blocking assignment code
2008-07-04 20:07:38 +01:00
a298b03735
Add bitwise OR
2008-07-04 12:05:49 +01:00
96d32b29c9
Translate logical expressions correctly.
...
For logical AND/OR in VHDL both operands must be of the
same type (Boolean)
2008-07-04 11:23:32 +01:00
c54b36c902
Add logical AND operator
2008-07-04 11:10:20 +01:00
6e8474f584
Fix bug where func had to be declared before use
2008-06-30 17:58:15 +01:00
d997397c38
Generate function calls with parameters
2008-06-25 21:49:22 +01:00
44aa8a6b91
Associate signals with scopes rather than entities
2008-06-25 18:12:57 +01:00
a3df37b851
Initial code to generate function calls
...
Also catch a few null-pointer issues
2008-06-25 17:29:09 +01:00
e77bb0157e
Remove redundant methods from vhdl_arch
2008-06-24 19:39:05 +01:00
4188fbecee
Add XOR operator and catch default case branch
2008-06-24 10:55:45 +01:00
88dc9b6b63
Remove debugging information from the output
2008-06-23 15:02:26 +01:00
449cd0a76e
Correctly generate signed/unsigned types
2008-06-23 14:28:27 +01:00
e5ef0d97bd
Fix signed/unsigned resizing
2008-06-23 13:04:28 +01:00
9911939576
Simplify casting code
2008-06-23 12:21:10 +01:00
c9ace14c40
Shift operators working correctly
2008-06-23 12:14:12 +01:00
c70fb4ba08
Simple implementation of IVL_EX_SELECT
2008-06-21 16:17:44 +01:00
7cba9f3cb2
Shift left/right
2008-06-21 15:19:33 +01:00
d6acb8d059
Less than / greater than
2008-06-21 15:16:22 +01:00
58f2f5007d
Bitwise AND
2008-06-21 15:05:48 +01:00
0caf4fd9d0
Add case statement
2008-06-21 15:03:36 +01:00
6622b5fe3a
Compare logic values for === and !==
2008-06-19 16:08:33 +01:00
fb31a88c51
Blocking assignment nearly working
2008-06-18 13:30:19 +01:00
ce72eb4eb4
Fix Valgrind warnings
2008-06-16 14:26:38 +01:00
7cde5f247e
Add translation for not-equals operator
2008-06-16 12:47:41 +01:00
849e7cb4d5
Add equality operator
2008-06-16 12:20:28 +01:00
8a9486eb49
Eliminate useless Resize() call
2008-06-14 18:11:10 +01:00
2fb57805ea
Use signed rather than std_logic_vector
...
Arithmetic operators now working correctly
2008-06-14 18:03:25 +01:00
919c1d695c
Adding binary +
2008-06-14 17:09:31 +01:00
005df31a0d
Use renamed signal in expressions, if there is one
2008-06-13 12:39:18 +01:00
645ee2003f
Translation for unary not
2008-06-12 10:56:28 +01:00
46991aa65c
Generate process bodies in the right place
2008-06-12 10:47:52 +01:00
110a1b2ac7
Replace type classes with enumeration
2008-06-08 12:48:56 +01:00
fbf85398da
Support converting bit strings to std_logic
2008-06-07 16:19:10 +01:00
cdb180e1d4
Associate a type with each VHDL expression node
2008-06-07 13:23:21 +01:00
305f448d05
Generate code for signal references
2008-06-07 11:24:09 +01:00
6e448da90d
Emit Write() calls for parameters of $display
2008-06-04 15:19:44 +01:00
9f035108e1
Stub code for translating expressions
2008-06-04 14:59:04 +01:00
Nick Gasson