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OpenRAM
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1549 Commits

Author SHA1 Message Date
mrg f542613d78 Correct wordline_driver enable to en, not en_bar. 2019-07-05 10:31:05 -07:00
mrg bfe4213fce Port address added to entire SRAM. 2019-07-05 09:44:42 -07:00
mrg 4c6556f1bc Add port address module 2019-07-05 09:04:48 -07:00
mrg c0f9cdbc12 Create port address module 2019-07-05 09:03:52 -07:00
mrg dd62269e0b Some cleanup 2019-07-05 08:18:58 -07:00
mrg 3176ae9d50 Fix pnand2 height in bank select. Unsure how it passed before. 2019-07-03 15:12:22 -07:00
Matt Guthaus f914ab0ece Re-enable replica tests 2019-07-03 14:57:47 -07:00
Matt Guthaus 0cb86b8ba2 Exclude new precharge in graph build 2019-07-03 14:46:20 -07:00
mrg 8b0b2e2817 Merge branch 'dev' into rbl_revamp 2019-07-03 14:05:28 -07:00
mrg 70c83f20b6 Fixes to pass unit tests. 
Skip replica tests until freepdk45 cells are made.
Revert to previous control and row addr dff placement.
 2019-07-03 13:37:56 -07:00
mrg bc4a3ee2b7 New port_data module works in SCMOS 2019-07-03 13:17:12 -07:00
mrg 244604fb0d Data port module working by itself. 2019-07-02 15:35:53 -07:00
mrg 2abe859df1 Fix shared bank offset. 2019-07-01 16:29:59 -07:00
Hunter Nichols 3f5b60856a Fixed key error with analytical delay of write ports. 2019-06-28 13:49:04 -07:00
Hunter Nichols ce7e320505 Undid change to add bitcell as input to array mod. 2019-06-25 18:26:13 -07:00
Hunter Nichols 4e08e2da87 Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
Hunter Nichols 4f3340e973 Cleaned up graph additions to characterizer. 2019-06-25 16:37:35 -07:00
Hunter Nichols 33c17ac41c Moved manual delay chain declarations from tech files to options. 2019-06-25 15:45:02 -07:00
Hunter Nichols 04ce3d5f45 Split control logic into different tests to avoid factory errors. 2019-06-25 14:55:28 -07:00
jsowash 3bd69d2759 Added functionality to express polygons in LEF files. 2019-06-25 09:20:00 -07:00
Matt d22d7de195 Reapply jsowash update without spice model file 2019-06-24 08:59:58 -07:00
mrg 4523a7b9f6 Replica bitcell array working 2019-06-19 16:03:21 -07:00
Hunter Nichols 2b07db33c8 Added bitcell as input to array, but there are DRC errors now. 2019-06-17 15:31:16 -07:00
mrg 5c4df2410e Fix dummy row LVS issue 2019-06-14 15:06:04 -07:00
mrg d35f180609 Add dummy row 2019-06-14 15:05:14 -07:00
mrg 3c3456596a Add replica row with dummy cells. 2019-06-14 14:38:55 -07:00
mrg b67f06a65a Add replica column for inclusion in replica bitcell array 2019-06-14 12:15:16 -07:00
mrg d8baa5384d Remove useless comments. Add missing copyright. 2019-06-14 10:13:13 -07:00
Matt Guthaus 6e044b776f Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
mrg 8418aea95a Revert height to width 2019-06-03 15:36:14 -07:00
mrg 58f51b72f1 Merge fixes 2019-06-03 15:31:49 -07:00
mrg 7b8c2cac30 Starting single layer power router. 2019-06-03 15:28:55 -07:00
mrg bd4d965e37 Begin single layer supply router 2019-06-03 15:27:37 -07:00
mrg 4612c9c182 Move power pins before no route option 2019-06-03 15:27:37 -07:00
mrg fc12ea24e9 Add boundary to every module and pgate for visual debug. 2019-06-03 15:27:37 -07:00
mrg 1268a7927b Pbitcell updates. 
Fix module offset error.
Add boundary for debugging.
Line wrap code.
 2019-06-03 15:27:37 -07:00
Matt Guthaus 7cca6b4f69 Add back scn3me_subm support 
Add back scn3me_subm tech files
Update cells to be DRC clean with rule 5.5.b
Allow magic for FreePDK45 but not debugged.
Revert to older Magic tech file for SCN3ME_SUBM
 2019-06-03 15:27:37 -07:00
mrg 301f032619 Remove +1 to induce error. 2019-05-31 10:55:17 -07:00
mrg d789f93743 Add debug runner during individual tests. 2019-05-31 10:51:42 -07:00
mrg bf86969972 Create sram subdirectory. 2019-05-31 08:56:24 -07:00
Hunter Nichols 36214792eb Removed some debug measurements that were causing failures. 2019-05-28 17:04:27 -07:00
Hunter Nichols ad229b1504 Altered indexing of objects in SRAM factory to remove duplications of items using OPTS names. Added smarter bitline name checking. 2019-05-28 16:55:09 -07:00
mrg 72f4a223c3 Move power pins before no route option 2019-05-27 16:38:47 -07:00
mrg c2cc901300 Add boundary to every module and pgate for visual debug. 2019-05-27 16:32:38 -07:00
mrg e738353b5c Pbitcell updates. 
Fix module offset error.
Add boundary for debugging.
Line wrap code.
 2019-05-27 16:19:29 -07:00
Hunter Nichols e2d1f7ab0a Added smarter name checking for the characterizer. 2019-05-27 13:08:59 -07:00
mrg 26146b6838 Fix SCN3ME_SUBM stuff. 
Update cells to be DRC clean with rule 5.5.b
Allow magic for FreePDK45 but not debugged.
Revert to older Magic tech file for SCN3ME_SUBM
 2019-05-26 22:28:16 -07:00
Hunter Nichols d08181455c Added multiport bitcell support for storage node checks 2019-05-20 22:50:03 -07:00
Hunter Nichols 099bc4e258 Added bitcell check to storage nodes. 2019-05-20 18:35:52 -07:00