mrg bd4d965e37 Begin single layer supply router

2019-06-03 15:27:37 -07:00

..

base

Begin single layer supply router

2019-06-03 15:27:37 -07:00

bitcells

Add boundary to every module and pgate for visual debug.

2019-06-03 15:27:37 -07:00

characterizer

Update copyright to correct years.

2019-05-06 06:50:15 -07:00

datasheet

Update copyright to correct years.

2019-05-06 06:50:15 -07:00

drc

Begin single layer supply router

2019-06-03 15:27:37 -07:00

example_configs

Add giant example for front-end mode

2019-04-01 15:49:01 -07:00

gdsMill

Remove non-rectangular error and just skip them.

2019-01-30 10:25:01 -08:00

modules

Add boundary to every module and pgate for visual debug.

2019-06-03 15:27:37 -07:00

pgates

Add boundary to every module and pgate for visual debug.

2019-06-03 15:27:37 -07:00

router

Begin single layer supply router

2019-06-03 15:27:37 -07:00

sram

Begin single layer supply router

2019-06-03 15:27:37 -07:00

tests

Add back scn3me_subm support

2019-06-03 15:27:37 -07:00

verify

Add back scn3me_subm support

2019-06-03 15:27:37 -07:00

debug.py

Update copyright to correct years.

2019-05-06 06:50:15 -07:00

gen_stimulus.py

Update copyright to correct years.

2019-05-06 06:50:15 -07:00

globals.py

Update copyright to correct years.

2019-05-06 06:50:15 -07:00

Makefile

Clean up Makefile for unit tests

2018-12-05 12:58:10 -08:00

openram.py

Update copyright to correct years.

2019-05-06 06:50:15 -07:00

options.py

Update copyright to correct years.

2019-05-06 06:50:15 -07:00

run_profile.sh

Convert pin map to a set for faster membership.

2019-04-01 15:45:44 -07:00

sram_factory.py

Update copyright to correct years.

2019-05-06 06:50:15 -07:00

view_profile.py

Update copyright to correct years.

2019-05-06 06:50:15 -07:00