Fix dummy row LVS issue

compiler/bitcells/dummy_bitcell.py

@@ -0,0 +1,48 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import design
+import debug
+import utils
+from tech import GDS,layer,parameter,drc
+import logical_effort
+
+class dummy_bitcell(design.design):
+    """
+    A single bit cell (6T, 8T, etc.)  This module implements the
+    single memory cell used in the design. It is a hand-made cell, so
+    the layout and netlist should be available in the technology
+    library.
+    """
+
+    pin_names = ["bl", "br", "wl", "vdd", "gnd"]
+    (width,height) = utils.get_libcell_size("dummy_cell_6t", GDS["unit"], layer["boundary"])
+    pin_map = utils.get_libcell_pins(pin_names, "dummy_cell_6t", GDS["unit"])
+
+    def __init__(self, name=""):
+        # Ignore the name argument
+        design.design.__init__(self, "dummy_cell_6t")
+        debug.info(2, "Create dummy bitcell")
+
+        self.width = dummy_bitcell.width
+        self.height = dummy_bitcell.height
+        self.pin_map = dummy_bitcell.pin_map
+
+    def analytical_power(self, corner, load):
+        """Bitcell power in nW. Only characterizes leakage."""
+        from tech import spice
+        leakage = spice["bitcell_leakage"]
+        dynamic = 0 #temporary
+        total_power = self.return_power(dynamic, leakage)
+        return total_power
+
+    def get_wl_cin(self):
+        """Return the relative capacitance of the access transistor gates"""
+        #This is a handmade cell so the value must be entered in the tech.py file or estimated.
+        #Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width.
+        access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
+        return 2*access_tx_cin