Fixed key error with analytical delay of write ports.

2026-09-03 08:27:11 +02:00 · 2019-06-28 13:49:04 -07:00
parent ce7e320505
commit 3f5b60856a
1 changed files with 1 additions and 0 deletions
@@ -529,6 +529,7 @@ class sram_base(design, verilog, lef):
            elif port in self.readwrite_ports:
                control_logic = self.control_logic_rw
            else:
+                delays[port] = self.return_delay(0,0) #Write ports do not have a lib defined delay, marked as 0 
                continue
            clk_to_wlen_delays = control_logic.analytical_delay(corner, slew, load)
            wlen_to_dout_delays = self.bank.analytical_delay(corner,slew,load,port) #port should probably be specified...