 mrg
|
eef97ff215
|
Reabstracting bit and word line names.
|
2020-08-06 11:17:49 -07:00 |
|
|
mrg
|
037de96989
|
Merge branch 'dev' into wlbuffer
|
2020-08-05 10:37:29 -07:00 |
|
|
mrg
|
528cb07635
|
Merge branch 'dev' into wlbuffer
|
2020-08-05 10:01:43 -07:00 |
|
 Bob Vanhoof
|
9b8ef5ef57
|
fix: generated pex file was not passed correctly to lib characterizer
|
2020-08-03 10:16:12 +02:00 |
|
|
Bob Vanhoof
|
487bb6c6e9
|
Merge branch 'dev' of github:VLSIDA/OpenRAM into CalibrePexFilesUpdate
|
2020-08-03 09:32:27 +02:00 |
|
|
Bob Vanhoof
|
dc55ededc1
|
fix regession tests after calibre fix
|
2020-07-31 12:51:34 +02:00 |
|
|
mrg
|
487027a9f2
|
Fix pex file names
|
2020-07-30 11:35:13 -07:00 |
|
|
mrg
|
8fa0065aaf
|
Undo PR 82 changes -- broke unit test.
|
2020-07-30 11:09:19 -07:00 |
|
|
mrg
|
a663d903c5
|
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
|
2020-07-30 08:44:25 -07:00 |
|
|
Matt Guthaus
|
68387ec525
|
Merge pull request #84 from bvhoof/CalibrePexFilesUpdate
calibrepex: file copy fix
|
2020-07-30 08:40:35 -07:00 |
|
 Hunter Nichols
|
c6f2edc20d
|
Changed warning message for multiport analytical characterization.
|
2020-07-29 19:50:06 -07:00 |
|
|
mrg
|
64d61f4d56
|
Merge remote-tracking branch 'private/dev' into dev
|
2020-07-29 12:16:41 -07:00 |
|
|
mrg
|
f23d2e36a7
|
Don't obstruct control logic signals with dffs when no column mux.
|
2020-07-29 10:31:18 -07:00 |
|
|
mrg
|
8a2fa90cd5
|
Merge remote-tracking branch 'private/dev' into dev
|
2020-07-29 10:11:26 -07:00 |
|
|
mrg
|
2fa561f98f
|
Local bitcell array edits. Skip test by default.
|
2020-07-29 10:08:13 -07:00 |
|
|
Hunter Nichols
|
b4dafac489
|
Fixed issue with sen measurement not being added
|
2020-07-27 23:55:03 -07:00 |
|
|
mrg
|
c260297366
|
Allow replica_bitcell_array without the replica columns for local wordlines.
|
2020-07-27 16:22:21 -07:00 |
|
|
Hunter Nichols
|
9ea3616260
|
Changed multiport characterization warning to better fit
|
2020-07-27 15:47:02 -07:00 |
|
|
Hunter Nichols
|
c65178f86c
|
Fixed issue with sen delay measure getting mixed with voltage checks
|
2020-07-27 15:43:50 -07:00 |
|
|
mrg
|
69cab42676
|
Add pbuf_dec gate
|
2020-07-27 13:59:55 -07:00 |
|
|
mrg
|
26b01e37c6
|
Fix pbuf test info
|
2020-07-27 13:59:35 -07:00 |
|
|
mrg
|
2991534d3f
|
Drafting local bitline stuff.
|
2020-07-23 17:15:39 -07:00 |
|
|
mrg
|
e1967dc548
|
Draft local and global arrays. Ensure rows before cols in usage.
|
2020-07-23 14:43:14 -07:00 |
|
|
mrg
|
317662d4aa
|
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
|
2020-07-23 14:17:52 -07:00 |
|
|
mrg
|
b7c43ae674
|
Fix 1w/1r example
|
2020-07-23 14:17:13 -07:00 |
|
|
mrg
|
58846a4a25
|
Limit wordline driver size. Place row addr dff near predecoders.
|
2020-07-20 17:57:38 -07:00 |
|
|
mrg
|
0ed81aa923
|
Removed extraneous shift from added mirroring
|
2020-07-20 14:11:52 -07:00 |
|
|
mrg
|
82bbacdfb5
|
Add data bus gap to dynamically computed channel width
|
2020-07-20 13:43:57 -07:00 |
|
|
mrg
|
a36e89e103
|
Replace data flops depending on channel width
|
2020-07-20 13:26:05 -07:00 |
|
|
mrg
|
2ccf3aea3b
|
Set channel route height and width (of routes, not pins)
|
2020-07-20 13:25:47 -07:00 |
|
|
mrg
|
f87b427f76
|
Add parent to channel route for dumpign debug gds.
|
2020-07-20 12:03:25 -07:00 |
|
|
mrg
|
f35848e4f8
|
Route col flops separately. Flip port 1 col flop for easier routing.
|
2020-07-20 12:02:59 -07:00 |
|
|
mrg
|
7385decbff
|
Add channel route cyclic VCG debugging.
|
2020-07-20 12:02:30 -07:00 |
|
|
mrg
|
80070dff41
|
Move write_driver din left to avoid control signal in spare columns.
|
2020-07-16 14:47:14 -07:00 |
|
|
mrg
|
9d5d632d1a
|
Pins may be below the channel.
|
2020-07-16 14:23:48 -07:00 |
|
|
mrg
|
ba3d32fa0c
|
Starting to implement minimizing channel router (not done)
|
2020-07-16 13:21:44 -07:00 |
|
|
mrg
|
919e6a5027
|
Merge remote-tracking branch 'private/dev' into dev
|
2020-07-15 19:47:44 -07:00 |
|
|
mrg
|
c7bc01c3a9
|
Clean up binning. Fix mults to 1 for certain gates.
|
2020-07-15 17:15:42 -07:00 |
|
|
Bob Vanhoof
|
ee3da91232
|
calibrepex: file copy fix
|
2020-07-15 11:50:21 +02:00 |
|
|
mrg
|
bb8157b3b7
|
Exit on DRC not run, check for LVSDRC before running in sram_base.
|
2020-07-14 08:38:49 -07:00 |
|
|
mrg
|
ed9d32c7bc
|
OpenRAM 1.1.6
v1.1.6
|
2020-07-13 16:26:25 -07:00 |
|
|
mrg
|
b4f5dc4c6e
|
OpenRAM 1.1.6
|
2020-07-13 16:25:55 -07:00 |
|
|
mrg
|
e502ee02be
|
Place before computing height of col mux.
|
2020-07-13 15:51:46 -07:00 |
|
|
mrg
|
2b7d89d2c1
|
Fix netlist_only in sky130
|
2020-07-13 14:59:31 -07:00 |
|
|
mrg
|
e49236f8fc
|
Default drc and lvs errors is skipped.
|
2020-07-13 14:08:00 -07:00 |
|
|
mrg
|
716798baae
|
Convert all DRC and LVS routines to set member variables for drc_errors and lvs_errors.
|
2020-07-13 13:01:00 -07:00 |
|
|
mrg
|
2011974e01
|
Make drc and lvs errors a member variable. Run only once.
|
2020-07-13 12:49:24 -07:00 |
|
|
mrg
|
a3195c0827
|
Add words_per_row and others in config file.
|
2020-07-13 12:37:56 -07:00 |
|
|
mrg
|
f49448d0a7
|
Merge remote-tracking branch 'private/dev' into dev
|
2020-07-09 11:58:04 -07:00 |
|
|
mrg
|
a989ea63a0
|
Move magic/netgen files to tech dir
|
2020-07-09 11:33:14 -07:00 |
|