 mrg
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e043aaffb3
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Don't print DRC/LVS/PEX run stats in regress.py
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2021-02-03 15:17:28 -08:00 |
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mrg
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19e99d1c7b
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Enable parallel regression testing.
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2021-02-03 14:19:11 -08:00 |
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 Hunter Nichols
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df8d59f32e
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Merge branch 'dev' into automated_analytical_model
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2021-02-01 01:49:45 -08:00 |
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mrg
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bc8fd4a882
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Merge branch 'supply_router' into dev
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2021-01-25 11:01:48 -08:00 |
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Matt Guthaus
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30fc81a1f0
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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mrg
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db142bcd5a
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Rename pins to original names
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2021-01-21 15:22:54 -08:00 |
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Hunter Nichols
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cd84cf1973
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Merged and addressed conflict in delay.py
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2021-01-06 01:37:16 -08:00 |
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Hunter Nichols
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48baf3ab4e
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Updated test to use new analytical class
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2021-01-06 01:34:44 -08:00 |
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mrg
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9ef4cf14c5
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Check for drc/lvs aux scripts in test 30
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2020-12-23 07:25:24 -08:00 |
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mrg
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e59333a232
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Change options to use route perimeter pins and supply as tree by default.
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2020-12-23 07:25:07 -08:00 |
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mrg
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ae1c889235
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Updates to IO signal router.
Route signals to perimeter using maze router.
Move IO pins without perimeter pins to M3 using add_io_pin (like add_power_pin).
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2020-12-22 09:39:58 -08:00 |
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mrg
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348001b1c8
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Supply tree uses signal grid. PEP8 cleanup.
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2020-12-21 13:51:50 -08:00 |
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mrg
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3a3ecb27d2
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Merge branch 'dev' into supply_router
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2020-12-17 15:53:31 -08:00 |
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Hunter Nichols
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56c4c89720
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Adjusted error margin for period in analytical model and added check in model test.
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2020-12-17 01:34:53 -08:00 |
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mrg
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d5ed45dadf
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Make default router tree router
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2020-12-16 16:42:19 -08:00 |
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mrg
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fd118c62e5
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Default zom is None not negative.
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2020-12-15 13:27:36 -08:00 |
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Hunter Nichols
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942675051a
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Added test for linear regression model.
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2020-12-14 14:37:53 -08:00 |
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mrg
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87493e1e30
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Disable pex tests.
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2020-12-11 11:47:10 -08:00 |
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mrg
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38bf12771b
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Make DRC/LVS scripts use relative paths
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2020-12-11 10:06:00 -08:00 |
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mrg
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9717794400
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Remove extra debug statement
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2020-12-08 11:59:14 -08:00 |
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mrg
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0008de3e59
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Change test 14 to odd sizes for use in sky130.
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2020-12-08 10:32:23 -08:00 |
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mrg
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e134e07522
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-11-20 16:57:14 -08:00 |
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mrg
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f729e9fca7
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Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions.
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2020-11-20 16:56:07 -08:00 |
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Hunter Nichols
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35e1a523cc
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Changed named on delay chain sizing variable. Automatic sizing default is False.
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2020-11-17 14:29:01 -08:00 |
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mrg
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7512aa6e70
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Skip test 50 which is too slow
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2020-11-16 08:59:25 -08:00 |
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mrg
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2f994b8c0a
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Change custom cells to use set_ports setter
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2020-11-14 07:15:27 -08:00 |
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mrg
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63941a10e1
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Add None as sp_file parameter to local_drc_check
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2020-11-12 10:01:38 -08:00 |
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mrg
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03dad01e4c
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Use readspice to define ports from sp netlist in Magic extract.
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2020-11-10 17:06:24 -08:00 |
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mrg
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31ae56ff39
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Simplify to a single DRC/LVS library test.
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2020-11-10 16:45:00 -08:00 |
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mrg
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2c203530ad
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Merge branch 'drclvs' into dev
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2020-11-09 14:36:36 -08:00 |
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mrg
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0ba2feee53
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Fix errors in new run_sim calls and corners
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2020-11-09 13:59:46 -08:00 |
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mrg
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532492d5ae
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Output functional stimulus to output directory.
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2020-11-09 12:00:25 -08:00 |
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mrg
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31d21e169f
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Skip LEF test as correct output keeps changing.
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2020-11-09 11:14:55 -08:00 |
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mrg
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66633a843b
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Add PDK layer names to tech file
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2020-11-09 09:10:43 -08:00 |
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mrg
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2da9c307db
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Disable 4x16 decoder test for now
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2020-11-06 13:50:04 -08:00 |
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mrg
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147649e142
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Why was single port decoder test a dual port?
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2020-11-06 12:21:30 -08:00 |
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mrg
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2c76a2680f
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Adjust openram options.
Remove option -d (dontpurge) and replace with keeptemp
Add option -d (debug) to drop into pdb.
Add option -k (--keeptemp) to keep temp files
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2020-11-05 13:12:26 -08:00 |
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mrg
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fb0b285652
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-11-04 10:40:20 -08:00 |
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mrg
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6e12d4d46c
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Skip tri gate array test
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2020-11-04 06:57:51 -08:00 |
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mrg
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29ac541b28
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Refactor dynamic cell name to utilize base class
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2020-11-03 13:18:46 -08:00 |
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mrg
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87419bd640
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Fix bitcell and pbitcell with different cell names
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2020-11-03 11:30:40 -08:00 |
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mrg
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cb3e9517bb
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Use cell_properties to override cell names
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2020-11-03 07:06:01 -08:00 |
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mrg
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da721a677d
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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mrg
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8c4584daa1
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Missing import fix.
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2020-11-03 06:09:42 -08:00 |
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mrg
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f9787eb878
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Use bitcell_base for all bitcells. Fix missing setup_bitcell call
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2020-11-02 17:00:15 -08:00 |
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mrg
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fa89b73ef8
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PR from mithro + other changable GDS file names
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2020-11-02 16:00:16 -08:00 |
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mrg
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cbf9c48504
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Names in skiptests changed. Reduce grid router verbosity.
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2020-10-23 09:22:59 -07:00 |
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mrg
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43d2058b3c
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Remove temp files
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2020-10-08 10:35:27 -07:00 |
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mrg
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9a0fc8047b
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Remove diff
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2020-10-08 09:53:52 -07:00 |
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mrg
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7076c376e0
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Remove log from branch
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2020-10-08 09:53:17 -07:00 |
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