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OpenRAM
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58 Commits

Author SHA1 Message Date
Matt Guthaus 14f440df73 Update golden results with new lib syntax 2020-04-22 10:40:04 -07:00
Matt Guthaus 9f54afbf2c Fix capitalization in verilog golden files 2019-08-21 14:29:57 -07:00
Matt Guthaus d0f04405a6 Convert capital names to lower case for consistency 2019-08-21 13:45:34 -07:00
Matt d22d7de195 Reapply jsowash update without spice model file 2019-06-24 08:59:58 -07:00
Hunter Nichols ddeb40c9bf Added lib test which generates multiple corner models. Only does process currently. 2019-03-04 16:27:10 -08:00
Matt Guthaus 599e5457a0 Fix all libs to have pin indices 2019-02-22 17:40:49 -08:00
Matt Guthaus 583dc4410b Revert bus bits back into pins 2019-02-22 16:22:27 -08:00
Matt Guthaus e210ef2a41 Add assert to lef and verilog unit test. Fix verilog files in golden results. 2019-01-11 16:42:50 -08:00
Matt Guthaus a7dd62b0e5 falling_edge not negative_edge 2019-01-11 15:17:27 -08:00
Matt Guthaus 49d0b9d69c Remove old scn3me golden results. Remove indices from new golden results. 2019-01-09 12:04:17 -08:00
Hunter Nichols 5c8a00ea1d Fixed pruned golden lib file from error in last commit. 2018-10-24 00:55:55 -07:00
Hunter Nichols da1b003d10 Fixed multiport lib files not generating the correct number of signals. Move setup time from DOUT to DIN in lib file. Altered golden files with these changes. 2018-10-24 00:17:08 -07:00
Hunter Nichols 016604f846 Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-24 00:16:26 -07:00
Matt Guthaus a58b1906ad Convert unit tests to scn4m_subm 
Also, fixed isdiff for python3.
 2018-09-17 11:13:46 -07:00
Hunter Nichols 8aaf1155d1 Fixed test 23_lib_sram_test. Fixed syntax in related golden lib files. 2018-09-06 22:51:34 -07:00
Hunter Nichols 0ff3b29b66 Fixed test 23_sram_prune test. Fixed syntax errors in golden lib files. 2018-09-06 22:06:23 -07:00
Hunter Nichols dd22f9acd5 Fixed issues with analytical sram test. Changed syntax errors in golden lib file. 2018-09-06 17:01:10 -07:00
Matt Guthaus d75d17bc8a Update golden results for FreePDK45 tests. 2018-07-27 14:25:52 -07:00
Matt Guthaus 5b2cb6a95e Update remaining SCMOS golden lib files. 2018-07-27 09:44:12 -07:00
Matt Guthaus 6b967c08dd Updated output messages in timing test comparisons. 
Added output to show which lines differ and what their line numbers are..
Added output to show relative difference of approximate compares.
Added output to include file names that mismatch.
 2018-07-27 09:34:44 -07:00
Matt Guthaus b14bef3bcf Initial merge of incomplete multi-port clean with new supply routing. 2018-05-11 08:18:04 -07:00
Matt Guthaus 7b5791b0e9 Change tolerance of tests to a big value. Update tests. 2018-05-09 08:29:23 -07:00
Matt Guthaus 6e9437356a Fix LEF tests with new power supplies. 2018-03-05 13:55:02 -08:00
mguthaus 04ed3792c7 Fix analytical lib tests with new power numbers. 2018-03-02 18:13:06 -08:00
mguthaus f3efb5fb50 Fixed leakage and power unit test results. 2018-02-23 15:20:52 -08:00
mguthaus fbc2d772be Fix index order of golden tests. 2018-02-21 19:37:10 -08:00
mguthaus a22badeeb5 Fix pruned results 2018-02-21 17:48:46 -08:00
mguthaus b8b2375346 Updated golden tests with new leakage aware power numbers. 2018-02-21 15:44:52 -08:00
mguthaus 5e8dff1e90 Fix unit tests with newest RBL delays. Fix tech problem with new spice models. 2018-02-16 13:54:05 -08:00
mguthaus 767990ca3b Update golden lib tests. Add new generic SCMOS models. Fix tech error with new msflop_in_cap name. 2018-02-13 15:54:50 -08:00
mguthaus f690532563 Add new corner-based lib files to unit tests. 2018-02-11 16:35:10 -08:00
mguthaus e8f658d356 Add updated non-pruned unit test results. 2018-02-07 19:35:21 -08:00
mguthaus 63ce754c72 Update unit test results 2018-02-07 18:48:22 -08:00
Matt Guthaus 1a491f3cd0 Make temp directory unique for test 30. Update LEF files after delay chain size change. 2018-02-07 15:05:21 -08:00
mguthaus c3592b3d46 Added new timing tests with ps,pd,as,ad caps included. 2018-02-06 05:26:27 -08:00
Matt Guthaus 92095e52f7 Update new LEF files for unit tests. 2018-02-05 10:27:56 -08:00
Matt Guthaus 7127895270 Update LEF files for unit tests 2018-02-02 15:51:29 -08:00
Matt Guthaus 8ef1e0af2c Replace LEF files with new changes. 2018-02-01 05:43:37 -08:00
Matt Guthaus 590f6e01d1 Fix assertion error syntax problem. Do not require hspice for functional test. Improve delay fail error message. 2018-01-31 15:38:02 -08:00
Matt Guthaus e0a6b59773 Fix LEF test mismatch in regression. 2018-01-12 08:54:31 -08:00
Matt Guthaus 1701eac1a9 Added workaround to import layouts into Magic. Select and well layers in active contacts. Fixed missing implant enclose active DRC rule in parameterized cells. 2018-01-11 10:24:44 -08:00
Matt Guthaus 4885616bec Remove metal3 in LEF library cells. 2017-12-19 13:12:39 -08:00
Matt Guthaus 97a2d620fe Fix dev tests. Split pruned test to separate golden result. 2017-12-19 11:42:11 -08:00
Matt Guthaus 9a4b2b4341 Revised LEF and Verilog generation. Does not read GDS for speed improvements. 2017-12-19 09:01:24 -08:00
Matt Guthaus abee235963 Rewrite the parameterized transistor and gate classes. 
Changes propagate through all designs.
All modules use instance and layout pins.
 2017-12-12 15:04:01 -08:00
mguthaus 5c10aebc0f Fix bug in multifinger ptx. Replace LEF file with new snapped layout. 2017-10-06 16:23:23 -07:00
Matt Guthaus 59a0394c2b Update LEF files with modified blockages. 2017-10-04 20:17:30 -07:00
Matt Guthaus e06e1691c8 Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
Matt Guthaus 857b997367 Modify LEF output to have all capital LAYER. Remove extra space before new lines. 2017-08-15 08:21:54 -07:00
Matt Guthaus d77216d6dd Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays. 2017-08-07 10:24:45 -07:00