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197 Commits

Author SHA1 Message Date
Hunter Nichols bd57a043d7 Removed reference to lamba in freepdk45 tech file. Fixed issue with transconductance equation. 2021-09-20 16:51:02 -07:00
Hunter Nichols 1236a0773a Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage. 2021-09-07 15:56:27 -07:00
Hunter Nichols de2dae4030 Changed unit capacitance from CACTI estimation to PTM estimation. 2021-08-25 15:23:12 -07:00
Hunter Nichols 12c03ddd9f Fixed issues with load capcitance units. Changed freepdk45 r and c wire values to be more in line with cacti. 2021-08-16 22:58:26 -07:00
Hunter Nichols 1b89533d7b Added unit r and c values with m2 minwidth incorporated to match CACTI params 2021-08-01 00:23:59 -07:00
Hunter Nichols 54cbef1aff Replaced cacti tech params with already existing params. Added an existence check in design_rules. 2021-07-27 14:31:22 -07:00
Hunter Nichols 10085d85ab Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files. 2021-07-21 14:59:02 -07:00
Hunter Nichols a312639ef8 Added tech params for on-resistance and load capacitances 2021-07-21 11:00:32 -07:00
Hunter Nichols ebc91814e5 Fixed various issues with imported code from CACTI, added CACTI as an option for analytical sim, added placeholder names in tech files for CACTI 2021-07-12 15:48:47 -07:00
mrg 9720e5af29 Remove default array row/col multiple 2021-06-29 11:28:19 -07:00
Hunter Nichols 294ccf602e Merged with dev, addressed conflict in port data 2021-06-21 17:23:32 -07:00
Hunter Nichols 8ee6d3be6c Added more data for regression modules. 2021-06-21 17:21:00 -07:00
Jesse Cirimelli-Low 8346ad736e add dimension contraints to other tech files 2021-06-18 14:36:15 -07:00
Hunter Nichols 4ec2e1240f Merge branch 'dev' into automated_analytical_model 2021-06-09 15:45:41 -07:00
Hunter Nichols c50ffe70b3 Added more configs for model and respective data. 2021-06-09 15:42:15 -07:00
Hunter Nichols 7a60eabdfe Add more freepdk45 data from regression model. 2021-06-09 13:31:38 -07:00
Hunter Nichols 54639bbb94 Added more data for regression models 2021-06-04 13:37:21 -07:00
Jesse Cirimelli-Low 6705f99855 merge in dev 2021-05-28 14:06:23 -07:00
Hunter Nichols a53c6c51ed Added sim data for freepdk45 and removed stale data 2021-05-26 18:40:46 -07:00
Jesse Cirimelli-Low e976c4043b Merge branch 'dev' into laptop_checkpoint 2021-04-14 15:58:06 -07:00
ota2 15e57d89ca fix end subckt typo 2021-02-27 18:28:07 -05:00
ota2 8403749fec Add Q and Qbar labels 2021-02-27 18:27:08 -05:00
jcirimel b18e2eae8d remove debug lines and merge 2021-02-09 20:53:23 -08:00
jcirimel dbe8a7f1af fix pwell pin shape bug 2021-02-09 20:51:50 -08:00
Hunter Nichols df8d59f32e Merge branch 'dev' into automated_analytical_model 2021-02-01 01:49:45 -08:00
Matt Guthaus 4b1c359089 update copyright year. 2021-01-22 11:24:53 -08:00
Hunter Nichols 59200d1048 Added updated data for scmos, removed unused files. 2021-01-13 13:09:21 -08:00
Hunter Nichols ed3d39a1b8 Added updated model data with slews and loads. Changed linear regressions to account for additional models. 2021-01-13 13:04:34 -08:00
Hunter Nichols 32ad436153 Added freepdk45 data for linear regression 2020-12-22 15:19:31 -08:00
mrg 8021430122 Fix pbitcell erros 2020-11-13 15:55:55 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
mrg a2f29e5edd Fix missing nand4_leakage #97 2020-11-12 09:48:08 -08:00
mrg 66633a843b Add PDK layer names to tech file 2020-11-09 09:10:43 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg 611a4155b9 Add initial custom layer properties. 2020-10-27 15:11:04 -07:00
mrg ef310970bf Use new Google PDK lib 2020-10-12 15:46:11 -07:00
jcirimel 35eac54c0d update freepdk bitcell for pex 2020-08-17 17:47:43 -07:00
jcirimel 19f4e30989 change Qbar to Q_bar in freepdk45 bitcells 2020-08-04 15:21:54 -07:00
mrg 80070dff41 Move write_driver din left to avoid control signal in spare columns. 2020-07-16 14:47:14 -07:00
mrg 20324ab3c4 Revert write driver pin spacing 2020-06-28 14:55:58 -07:00
mrg e774314add Separate write driver pins by M3 pitch 2020-06-28 14:14:48 -07:00
mrg a7ee17eb2d Move output of sense amp to side like other techs 2020-06-26 15:29:27 -07:00
mrg cddb16dabc Separate active and poly contact to gate rule 2020-06-24 09:17:39 -07:00
mrg 157926960b Flip freepdk45 flop, dff_buf route layer change 2020-06-09 13:48:16 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
Jesse Cirimelli-Low aedbc5f968 merge custom cell and module properties 2020-02-12 04:09:40 +00:00
Jesse Cirimelli-Low 18573c0e42 add module properties to other technologies 2020-02-05 22:25:35 +00:00
mrg 79391b84da Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
Matt Guthaus 3147b99ce0 Merge remote-tracking branch 'bkoppelmann/bit-sym' into dev 2020-01-29 11:24:09 -08:00