mirror of https://github.com/VLSIDA/OpenRAM.git
change Qbar to Q_bar in freepdk45 bitcells
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@ -5,11 +5,11 @@ MM0 Qbar Q gnd gnd NMOS_VTG W=205.00n L=50n
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MM4 Qbar Q vdd vdd PMOS_VTG W=90n L=50n
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* Inverer 2
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MM1 Q Qbar gnd gnd NMOS_VTG W=205.00n L=50n
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MM5 Q Qbar vdd vdd PMOS_VTG W=90n L=50n
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MM1 Q Q_bar gnd gnd NMOS_VTG W=205.00n L=50n
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MM5 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n
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* Access transistors
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MM3 bl wl Q gnd NMOS_VTG W=135.00n L=50n
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MM2 br wl Qbar gnd NMOS_VTG W=135.00n L=50n
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MM2 br wl Q_bar gnd NMOS_VTG W=135.00n L=50n
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.ENDS cell_6t
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@ -1,15 +1,15 @@
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.SUBCKT dummy_cell_6t bl br wl vdd gnd
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* Inverter 1
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MM0 Qbar Q gnd gnd NMOS_VTG W=205.00n L=50n
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MM4 Qbar Q vdd vdd PMOS_VTG W=90n L=50n
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MM0 Q_bar Q gnd gnd NMOS_VTG W=205.00n L=50n
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MM4 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n
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* Inverer 2
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MM1 Q Qbar gnd gnd NMOS_VTG W=205.00n L=50n
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MM5 Q Qbar vdd vdd PMOS_VTG W=90n L=50n
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MM1 Q Q_bar gnd gnd NMOS_VTG W=205.00n L=50n
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MM5 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n
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* Access transistors
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MM3 bl_noconn wl Q gnd NMOS_VTG W=135.00n L=50n
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MM2 br_noconn wl Qbar gnd NMOS_VTG W=135.00n L=50n
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MM2 br_noconn wl Q_bar gnd NMOS_VTG W=135.00n L=50n
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.ENDS cell_6t
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