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OpenRAM
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3,559 Commits 4 Branches 63 Tags 78 MiB
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3112 Commits

Author SHA1 Message Date
mrg bb1ac1a38e Fix incorrect bus indexing of spare_wen. Convert internal signals to not use braces. 2021-06-21 15:23:08 -07:00
mrg f3f19aeeeb Remove print statement 2021-06-21 15:16:36 -07:00
mrg 1ce5823df8 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2021-06-21 13:14:23 -07:00
mrg d53bc98ff5 Exit with error when spice models not found. Use ngspice if no simulator defined. 2021-06-21 13:14:08 -07:00
mrg af31027504 Fix error in 1 spare column Verilog 2021-06-21 13:13:53 -07:00
Jesse Cirimelli-Low 56dc83de47 fix typo 2021-06-18 18:10:12 -07:00
Jesse Cirimelli-Low 2dbe928c09 fix typo 2021-06-18 18:08:57 -07:00
Jesse Cirimelli-Low 4688988434 only check dimensions on single port 2021-06-18 17:46:39 -07:00
Jesse Cirimelli-Low 0008df0204 catch where strap size is zero 2021-06-18 15:24:24 -07:00
Jesse Cirimelli-Low 2eb98083d0 Merge branch 'dev' into laptop_checkpoint 2021-06-18 14:21:39 -07:00
Jesse Cirimelli-Low 8ceece2af6 check for valid dimensions instead of recalcuating 2021-06-18 14:21:02 -07:00
mrg 693a81fa8d Fix spare_wen IO pin names 2021-06-18 10:44:35 -07:00
mrg 1299989332 Fix single spare_wen naming 2021-06-18 08:43:21 -07:00
mrg 67877175b2 Fix error in no spare column verilog 2021-06-18 08:41:26 -07:00
mrg 81d20ec2aa Add spare cols to behavioral Verilog model 2021-06-18 07:23:41 -07:00
Jesse Cirimelli-Low 7b7c72706a merge in dev 2021-06-17 09:49:32 -07:00
Jesse Cirimelli-Low d9afe89770 remove print statement 2021-06-17 03:23:46 -07:00
Jesse Cirimelli-Low 1ce6b4d41a fix freepdk45 2021-06-17 03:21:01 -07:00
mrg afe0902547 Enable small short func tests 2021-06-16 19:13:50 -07:00
mrg b7f1c8e8fc Fix name for detecting single port 2021-06-16 19:07:56 -07:00
mrg c7c319c11f Use extra bitcell version tag only for single port in sky130 2021-06-16 19:06:12 -07:00
mrg d119a0e7ff Use sky130 bitcell in simulation for BLs 2021-06-16 18:45:53 -07:00
mrg 1e486cd344 Use local spacing rule 2021-06-16 18:41:39 -07:00
Hunter Nichols 16e658726e When determining bitline names, added a technology check for sky130. 2021-06-16 17:04:02 -07:00
Jesse Cirimelli-Low e775f7a355 fixed indent 2021-06-16 12:36:00 -07:00
Jesse Cirimelli-Low 2b9df2ff1f uncomment function sim and datasheet generation 2021-06-16 11:23:27 -07:00
mrg 6ac082ce23 Only replace simulator if it is defined. 2021-06-16 10:44:13 -07:00
mrg 1adada9e27 Merge branch 'dev' into xyce 2021-06-16 09:52:17 -07:00
Jesse Cirimelli-Low 25bc178132 extend input rail 2021-06-14 15:13:17 -07:00
mrg 159d0ed603 Fix s_en spacing problem. 2021-06-13 15:08:05 -07:00
mrg 53107a8322 Add ring test 2021-06-13 15:03:41 -07:00
mrg d6a72aed37 Add 2x1 perimter pins to satisfy minimum area rule. 2021-06-13 15:00:46 -07:00
mrg 2e23fffadd Fix comment 2021-06-13 14:18:55 -07:00
Jesse Cirimelli-Low 73cc6b3891 uncomment 4x16 decoder 2021-06-11 18:20:36 -07:00
Jesse Cirimelli-Low bee9b07516 fix decoder routing 2021-06-11 18:19:07 -07:00
Jesse Cirimelli-Low 2e72da0e53 rotate input to rail contacts for drc 2021-06-10 14:01:28 -07:00
Jesse Cirimelli-Low 247a388ab5 Merge branch 'dev' into laptop_checkpoint 2021-06-09 18:25:45 -07:00
Jesse Cirimelli-Low 10f561648f remove hierarchical decoder vertial m1 above pins 2021-06-09 18:24:21 -07:00
mrg 8964abc2b7 Change simulator based on one in use. 2021-06-09 16:02:32 -07:00
mrg a1cb20878d Swap LH/HL hold times in sky130. 2021-06-08 11:14:27 -07:00
mrg 27c6a13923 Back out drc listall count for detecting errors 2021-06-04 15:51:50 -07:00
mrg cf61096936 Merge branch 'laptop_checkpoint' into dev 2021-06-04 15:22:37 -07:00
mrg 6643759345 Add back drc listall with correct output. 2021-06-04 11:06:39 -07:00
mrg 53791d79c8 spacing must be two extensions (one for each cell) 2021-06-04 08:56:06 -07:00
mrg cc4c6e909b Check if s_en exists before using it 2021-06-04 07:48:26 -07:00
mrg 4107c983e2 Make sure channel route is below s_en 2021-06-04 07:14:49 -07:00
mrg 537fd6eff9 Use None instead of empty string for tool names. 2021-06-01 16:41:14 -07:00
mrg 1ded978256 Change nwell from gnd to vdd. dnwell space added. 2021-06-01 15:10:55 -07:00
Jesse Cirimelli-Low 24b45ca2d4 use flat magic files instead of gds flatten subcell 2021-05-29 16:54:36 -07:00
Jesse Cirimelli-Low 131ca42512 merge in dev 2021-05-29 16:11:21 -07:00