mirror of https://github.com/VLSIDA/OpenRAM.git
Check if s_en exists before using it
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@ -446,8 +446,12 @@ class sram_1bank(sram_base):
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layer_stack = self.m3_stack
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if port == 0:
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# This is relative to the bank at 0,0 or the s_en which is routed on M3 also
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s_en_bot = self.control_logic_insts[port].get_pin("s_en").by()
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y_offset = min(0, s_en_bot) - self.data_bus_size[port] + 2 * self.m3_pitch
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if "s_en" in self.control_logic_insts[port].mod.pin_map:
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y_bottom = min(0, self.control_logic_insts[port].get_pin("s_en").by())
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else:
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y_bottom = 0
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y_offset = y_bottom - self.data_bus_size[port] + 2 * self.m3_pitch
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offset = vector(self.control_logic_insts[port].rx() + self.dff.width,
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y_offset)
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@ -464,8 +468,11 @@ class sram_1bank(sram_base):
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else:
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self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap
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else:
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s_en_top = self.control_logic_insts[port].get_pin("s_en").uy()
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y_offset = max(self.bank.height, s_en_top) + self.m3_pitch
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if "s_en" in self.control_logic_insts[port].mod.pin_map:
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y_top = max(self.bank.height, self.control_logic_insts[port].get_pin("s_en").uy())
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else:
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y_top = self.bank.height
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y_offset = y_top + self.m3_pitch
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offset = vector(0,
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y_offset)
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cr = channel_route(netlist=route_map,
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