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OpenRAM
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Change nwell from gnd to vdd. dnwell space added.

This commit is contained in:
mrg 2021-06-01 15:10:55 -07:00
parent e944a5ec02
commit 1ded978256
2 changed files with 7 additions and 7 deletions
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10
compiler/base/hierarchy_layout.py
View File

@ -1409,7 +1409,7 @@ class layout():
[ll, ur] = bbox
# Possibly inflate the bbox
nwell_offset = vector(self.nwell_width, self.nwell_width)
nwell_offset = vector(2 * self.nwell_width, 2 * self.nwell_width)
ll -= nwell_offset.scale(inflate, inflate)
ur += nwell_offset.scale(inflate, inflate)
@ -1448,7 +1448,7 @@ class layout():
to_layer="m1",
offset=loc)
else:
self.add_power_pin(name="gnd",
self.add_power_pin(name="vdd",
loc=loc,
start_layer="li")
count += 1
@ -1468,7 +1468,7 @@ class layout():
to_layer="m1",
offset=loc)
else:
self.add_power_pin(name="gnd",
self.add_power_pin(name="vdd",
loc=loc,
start_layer="li")
count += 1
@ -1488,7 +1488,7 @@ class layout():
to_layer="m2",
offset=loc)
else:
self.add_power_pin(name="gnd",
self.add_power_pin(name="vdd",
loc=loc,
start_layer="li")
count += 1
@ -1508,7 +1508,7 @@ class layout():
to_layer="m2",
offset=loc)
else:
self.add_power_pin(name="gnd",
self.add_power_pin(name="vdd",
loc=loc,
start_layer="li")
count += 1

4
compiler/router/router.py
View File

@ -881,7 +881,7 @@ class router(router_tech):
"""
pg = pin_group(name, [], self)
# Offset two spaces inside and one between the rings
if name == "vdd":
if name == "gnd":
offset = width + 2 * space
else:
offset = space
@ -911,7 +911,7 @@ class router(router_tech):
pg = pin_group(name, [], self)
# Offset two spaces inside and one between the rings
# Units are in routing grids
if name == "vdd":
if name == "gnd":
offset = width + 2 * space
else:
offset = space