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OpenRAM
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413 Commits

Author SHA1 Message Date
Matt Guthaus bab92fcf38 Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works. 2018-03-23 08:13:20 -07:00
Matt Guthaus 1f81b24e96 Single bank passing DRC and LVS again. 
Unfold hierarchical decoder to improve routability.
 2018-03-23 08:13:10 -07:00
Matt Guthaus b867e163a6 Move label pins to center like layout pins. 
Rework of control logic with vertical poly. Passes DRC/LVS.
Single bank passing DRC.
 2018-03-23 08:12:59 -07:00
Matt Guthaus 8ca9ba4244 Recreate delay chain and RBL to have vertical poly only. 2018-03-23 08:12:47 -07:00
Matt Guthaus ed8eaed54f Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array. 2018-03-23 08:12:47 -07:00
Matt Guthaus c020d74f26 Add dff_buf and dff_array modules. 2018-03-23 08:11:51 -07:00
Matt Guthaus a2514878c1 Simplify dff array names of 1-dimension. Add ports on metal2. 2018-03-05 16:22:35 -08:00
Matt Guthaus 1eda3aa131 Add back offset all coordinates in sram.py. 2018-03-05 14:22:24 -08:00
Matt Guthaus ba82222475 Add bank_select module option 2018-03-05 14:06:12 -08:00
Matt Guthaus 54f245cb9f Fix capitalization of pins in dff_array 2018-03-05 14:04:34 -08:00
Matt Guthaus 6e9437356a Fix LEF tests with new power supplies. 2018-03-05 13:55:02 -08:00
Matt Guthaus 4205a6a700 Connect bank supply rings in sram.py. 2018-03-05 13:49:22 -08:00
Matt Guthaus 0c203c1c7e RBL width is max of delay chain or bitcell load. 2018-03-05 10:23:13 -08:00
Matt Guthaus 98fb1173df Move bank select logic to a self contained module. 2018-03-05 10:22:51 -08:00
Matt Guthaus 0f721a3d40 Add vdd and gnd rails around bank structure. 2018-03-04 17:53:22 -08:00
Matt Guthaus 8d9b79dfd8 Add dff_buf for buffered flop arrays. 2018-03-04 16:13:10 -08:00
mguthaus 04ed3792c7 Fix analytical lib tests with new power numbers. 2018-03-02 18:13:06 -08:00
Matt Guthaus 242a1a68e0 Fix duplicate instance gds output bug that only showed up in Magic extraction. Every time we saved a GDS, additional instances were put in the GDS file. Most extraction tools ignored this, but Magic actually extracted duplicates. 2018-03-02 18:05:46 -08:00
Matt Guthaus 2b130de198 Rewrite run_lvs.sh script to utilize setup.tcl file. 2018-03-02 18:03:55 -08:00
Matt Guthaus 7293eb33bc Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-03-02 10:30:16 -08:00
Hunter Nichols d0dcd9f34b Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
Hunter Nichols 93ad99b9e1 Changed variable names in analytical power function to be more clear. 2018-02-28 12:32:54 -08:00
Hunter Nichols 6a3f0843ff Fixed accidental changes made to analytical delay. 2018-02-28 12:18:41 -08:00
Hunter Nichols e6d6680da1 Fixed conflict in delay.py 2018-02-27 13:02:22 -08:00
Matt Guthaus 2b839d34a3 Get rid of netgen error of undefined dlatch. Fix sp_read to find correct subckt name and pins. 2018-02-27 08:59:46 -08:00
Hunter Nichols d0e6dc9ce7 First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
Matt Guthaus 35137d1c67 Add extra comments in stimulus output. 2018-02-26 14:39:06 -08:00
Matt Guthaus a732405836 Add utility script gen_stimulus.py to help create simulations for debugging. 2018-02-26 08:54:35 -08:00
mguthaus 7a14cf16e0 Change priority of debug info for DRC/LVS. 2018-02-25 11:14:31 -08:00
mguthaus 322f354878 Convert period to float to avoid type mismatch. 2018-02-25 11:13:43 -08:00
mguthaus f3efb5fb50 Fixed leakage and power unit test results. 2018-02-23 15:20:52 -08:00
Matt Guthaus d88ff01792 Change default operating conditions to OC 2018-02-23 13:38:55 -08:00
Matt Guthaus 29aa6002e6 Make period into p instead of remove it. Changes file names... 2018-02-23 12:50:02 -08:00
Matt Guthaus 9d1f31467e Move internal power to clock pin. Differentiate leakge power when CSb is high. 2018-02-23 12:21:32 -08:00
Matt Guthaus 107752b1fb Fix num words in example. 2018-02-23 12:17:43 -08:00
Matt Guthaus e3e7a31c6b Fix syntax error in functional test. 2018-02-23 07:47:01 -08:00
Hunter Nichols 62ad30e741 Added initial version of analytical power esitmation. Loops through instances but power estimate is not accurate. 2018-02-22 19:35:54 -08:00
Matt Guthaus 23f06bfa9a Reduce number of parameters in function calls for delay.py. 2018-02-22 11:14:58 -08:00
Hunter Nichols beb7dad9bc Added corner paramters to power functions. This commit does not compile (sorry) 2018-02-22 00:15:55 -08:00
Hunter Nichols d4a0f48d4f Added power calculations for inverter. Still testing. 2018-02-21 19:51:21 -08:00
mguthaus fbc2d772be Fix index order of golden tests. 2018-02-21 19:37:10 -08:00
Matt Guthaus b31f3c18af Change BSIM3 models to version 3.3.0. Add comment about multithreading selection. 2018-02-21 17:50:12 -08:00
mguthaus a22badeeb5 Fix pruned results 2018-02-21 17:48:46 -08:00
Matt Guthaus cf5f1e94b9 Update hspice results 2018-02-21 16:12:20 -08:00
Matt Guthaus 4e414b6c15 Fix unintended unmerge of changes. Bad bad. 2018-02-21 16:03:49 -08:00
Matt Guthaus a44346110b Fix merge of results. 2018-02-21 15:47:07 -08:00
Matt Guthaus fcacd46866 UPdate tests with new delay and slew names and leakage power. 2018-02-21 15:45:49 -08:00
mguthaus b8b2375346 Updated golden tests with new leakage aware power numbers. 2018-02-21 15:44:52 -08:00
Matt Guthaus 4b9ea66a42 Change names of variables to indicate transistions for clarity. 2018-02-21 15:13:46 -08:00
Matt Guthaus 71831e7737 Get delays only for successful run. 2018-02-21 14:05:39 -08:00