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OpenRAM
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544 Commits

Author SHA1 Message Date
Matt Guthaus a6c2e77bcf Move precharge and column mux cells to pgate directory. 
Move gnd to M3 in column mux.
Create column mux cell unit test.
 2018-04-06 17:15:14 -07:00
Matt Guthaus 91e342e4c9 Move precharge vdd pin to left edge. 2018-04-04 15:03:29 -07:00
Matt Guthaus a772217172 Route precharge_array vdd in M3 2018-04-04 13:49:55 -07:00
Matt Guthaus f9916f9f43 Route precharge vdd to M3 2018-04-04 13:34:56 -07:00
Matt Guthaus a35fc1f339 Add contact to cell6t and replica. 2018-04-04 13:18:12 -07:00
Matt Guthaus 4c4cfb2a3c Add local dir for output. Will remove later. 2018-04-04 09:55:32 -07:00
Matt Guthaus a0bf5345f8 Mostly working for 1 bank. 2018-03-23 08:14:26 -07:00
Matt Guthaus 97c08bce95 Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control. 
Shift s_en buffers even with other cells.
 2018-03-23 08:14:09 -07:00
Matt Guthaus 696433b1ec Add bank_sel to bank_select module as input. 
Remove reference to control in sram.
Add dff_buf_array to options.
Added inverted DFF
Add variable height pinvbuf
 2018-03-23 08:13:39 -07:00
Matt Guthaus 5bf915a232 Detect via size for power ring. 2018-03-23 08:13:28 -07:00
Matt Guthaus ed2fa10caa Use LSB for column mux. 
Detect via size for power ring.
 2018-03-23 08:13:20 -07:00
Matt Guthaus bab92fcf38 Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works. 2018-03-23 08:13:20 -07:00
Matt Guthaus 1f81b24e96 Single bank passing DRC and LVS again. 
Unfold hierarchical decoder to improve routability.
 2018-03-23 08:13:10 -07:00
Matt Guthaus b867e163a6 Move label pins to center like layout pins. 
Rework of control logic with vertical poly. Passes DRC/LVS.
Single bank passing DRC.
 2018-03-23 08:12:59 -07:00
Matt Guthaus 8ca9ba4244 Recreate delay chain and RBL to have vertical poly only. 2018-03-23 08:12:47 -07:00
Matt Guthaus ed8eaed54f Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array. 2018-03-23 08:12:47 -07:00
Matt Guthaus c020d74f26 Add dff_buf and dff_array modules. 2018-03-23 08:11:51 -07:00
Matt Guthaus a2514878c1 Simplify dff array names of 1-dimension. Add ports on metal2. 2018-03-05 16:22:35 -08:00
Matt Guthaus 1eda3aa131 Add back offset all coordinates in sram.py. 2018-03-05 14:22:24 -08:00
Matt Guthaus ba82222475 Add bank_select module option 2018-03-05 14:06:12 -08:00
Matt Guthaus 54f245cb9f Fix capitalization of pins in dff_array 2018-03-05 14:04:34 -08:00
Matt Guthaus 6e9437356a Fix LEF tests with new power supplies. 2018-03-05 13:55:02 -08:00
Matt Guthaus 4205a6a700 Connect bank supply rings in sram.py. 2018-03-05 13:49:22 -08:00
Matt Guthaus 0c203c1c7e RBL width is max of delay chain or bitcell load. 2018-03-05 10:23:13 -08:00
Matt Guthaus 98fb1173df Move bank select logic to a self contained module. 2018-03-05 10:22:51 -08:00
Matt Guthaus 0f721a3d40 Add vdd and gnd rails around bank structure. 2018-03-04 17:53:22 -08:00
Matt Guthaus 8d9b79dfd8 Add dff_buf for buffered flop arrays. 2018-03-04 16:13:10 -08:00
mguthaus 04ed3792c7 Fix analytical lib tests with new power numbers. 2018-03-02 18:13:06 -08:00
Matt Guthaus 242a1a68e0 Fix duplicate instance gds output bug that only showed up in Magic extraction. Every time we saved a GDS, additional instances were put in the GDS file. Most extraction tools ignored this, but Magic actually extracted duplicates. 2018-03-02 18:05:46 -08:00
Matt Guthaus 2b130de198 Rewrite run_lvs.sh script to utilize setup.tcl file. 2018-03-02 18:03:55 -08:00
Matt Guthaus fc441fe568 Add LICENSE and README from NCSU CDK 2018-03-02 10:42:23 -08:00
Matt Guthaus 7293eb33bc Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-03-02 10:30:16 -08:00
Matt Guthaus ae2dbb4cd5 Add display techfiles from NCSU PDKs. 2018-03-02 10:30:03 -08:00
Matt Guthaus 2f352c905f
Merge pull request #33 from hznichol/analytical_power 
Analytical power
 2018-03-02 10:27:21 -08:00
Hunter Nichols d0dcd9f34b Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
Hunter Nichols 9317eb7e8b Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into analytical_power 2018-03-01 20:52:40 -08:00
Matt Guthaus 9a6081de0e Remove KP from SCMOS models to get rid of ngspice error. 2018-03-01 11:10:04 -08:00
Hunter Nichols 93ad99b9e1 Changed variable names in analytical power function to be more clear. 2018-02-28 12:32:54 -08:00
Hunter Nichols 6a3f0843ff Fixed accidental changes made to analytical delay. 2018-02-28 12:18:41 -08:00
Hunter Nichols e6d6680da1 Fixed conflict in delay.py 2018-02-27 13:02:22 -08:00
Matt Guthaus 2b839d34a3 Get rid of netgen error of undefined dlatch. Fix sp_read to find correct subckt name and pins. 2018-02-27 08:59:46 -08:00
Matt Guthaus 01244347c1 Add git attribute file to ignore spice files in determining language. 2018-02-26 17:27:04 -08:00
Hunter Nichols d0e6dc9ce7 First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
Matt Guthaus 20dfb81359 Update contribution guidelines. 2018-02-26 15:03:03 -08:00
Matt Guthaus 35137d1c67 Add extra comments in stimulus output. 2018-02-26 14:39:06 -08:00
mguthaus 45295b5cfa Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-02-26 09:04:01 -08:00
mguthaus 0175870628 Forgot to add directories for tracking of IP files. 2018-02-26 09:03:53 -08:00
Matt Guthaus a732405836 Add utility script gen_stimulus.py to help create simulations for debugging. 2018-02-26 08:54:35 -08:00
mguthaus cc99025279 Add log files for IP memories. 2018-02-25 11:25:20 -08:00
mguthaus f7a3fb90f0 Add SCMOS IP files. 2018-02-25 11:20:50 -08:00