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Add log files for IP memories.

This commit is contained in:
mguthaus 2018-02-25 11:25:20 -08:00
parent f7a3fb90f0
commit cc99025279
24 changed files with 2844 additions and 0 deletions
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_12899_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_128b_1024w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_12899_temp/ =========|
|==============================================================================|
Output files are sram_1rw_128b_1024w_1bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 128
Words: 1024
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 16:26:13.838687 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 52 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 15917 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 17508 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 21120 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 256 x 512
[verify.calibre/run_drc]: bitcell_array Geometries: 39847938 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 89090 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 48389 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 31747 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 41475 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_256rows Geometries: 70385 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 5877 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 75270 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 22788 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 70146 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 40382617 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_128b_1024w_1bank_freepdk45 Geometries: 40410068 Checks: 167 Errors: 0
** SRAM creation: 3506.7 seconds
SP: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45.sp
** Spice writing: 0.6 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_12899_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 127 data bit
[characterizer.trim_spice/trim]: Keeping bl[511] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 10.0ns feasible_delay 3.1226964ns/0.30308602ns slew 0.034041887ns/0.077321978ns
[characterizer.delay/find_min_period]: MinPeriod Search: 5.0ns (ub: 10.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 7.5ns (ub: 10.0 lb: 5.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 6.25ns (ub: 7.5 lb: 5.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 5.625ns (ub: 6.25 lb: 5.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 5.9375ns (ub: 6.25 lb: 5.625)
[characterizer.delay/find_min_period]: MinPeriod Search: 5.78125ns (ub: 5.9375 lb: 5.625)
[characterizer.delay/analyze]: Min Period: 5.9375n with a delay of 3.1226964 / 0.30308602
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
** Characterization: 16788.8 seconds
GDS: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45.gds
** GDS: 9.0 seconds
LEF: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45.lef
** LEF: 24.4 seconds
Verilog: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45.v
** Verilog: 0.0 seconds
** End: 20330.3 seconds

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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_18643_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_128b_1024w_2bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_18643_temp/ =========|
|==============================================================================|
Output files are sram_1rw_128b_1024w_2bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 128
Words: 1024
Banks: 2
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-23 19:17:15.047539 seconds
[sram/compute_sizes]: Words per row: 2
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 52 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 15917 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 17508 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 21120 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 256 x 256
[verify.calibre/run_drc]: bitcell_array Geometries: 19924226 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 44546 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 24323 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 31747 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 41475 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_256rows Geometries: 70385 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 5290 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 75270 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 22788 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 70146 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 20381520 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msb_address
[verify.calibre/run_drc]: msb_address Geometries: 594 Checks: 167 Errors: 0
ERROR: file calibre.py: line 131: sram_1rw_128b_1024w_2bank_freepdk45 Geometries: 40824902 Checks: 167 Errors: 1
ERROR: file design.py: line 87: DRC failed for sram_1rw_128b_1024w_2bank_freepdk45

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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_5959_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_128b_1024w_4bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_5959_temp/ =========|
|==============================================================================|
Output files are sram_1rw_128b_1024w_4bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 128
Words: 1024
Banks: 4
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-23 19:35:43.956230 seconds
[sram/compute_sizes]: Words per row: 2
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 26 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 7961 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 9383 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 12956 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 128 x 256
[verify.calibre/run_drc]: bitcell_array Geometries: 9962498 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 44546 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 24323 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 31747 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 41475 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_128rows Geometries: 65237 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 4703 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 75270 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 22788 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 35074 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 10340523 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msb_address
[verify.calibre/run_drc]: msb_address Geometries: 1181 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_128b_1024w_4bank_freepdk45 Geometries: 42826713 Checks: 167 Errors: 0
** SRAM creation: 439.1 seconds
SP: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45.sp
** Spice writing: 0.2 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_5959_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 127 data bit
[characterizer.trim_spice/trim]: Keeping bl[254] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[511] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 0.19175762ns/0.17403244ns slew 0.091382364ns/0.093018754ns
[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.875ns (ub: 2.5 lb: 1.25)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.1875ns (ub: 2.5 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.03125ns (ub: 2.1875 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.953125ns (ub: 2.03125 lb: 1.875)
[characterizer.delay/analyze]: Min Period: 2.03125n with a delay of 0.19175762 / 0.17403244
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
** Characterization: 35039.9 seconds
GDS: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45.gds
** GDS: 5.3 seconds
LEF: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45.lef
** LEF: 36.1 seconds
Verilog: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45.v
** Verilog: 0.0 seconds
** End: 35521.6 seconds

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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_25677_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_32b_1024w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_25677_temp/ =========|
|==============================================================================|
Output files are sram_1rw_32b_1024w_1bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 32
Words: 1024
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 07:05:54.597754 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 52 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 15917 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 17508 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 21120 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 256 x 128
[verify.calibre/run_drc]: bitcell_array Geometries: 9962370 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 22274 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 12101 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 7939 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 10371 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_256rows Geometries: 70385 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 5877 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 18822 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 5700 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 70146 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 10249561 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_32b_1024w_1bank_freepdk45 Geometries: 10275380 Checks: 167 Errors: 0
** SRAM creation: 428.3 seconds
SP: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45.sp
** Spice writing: 0.2 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_25677_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 31 data bit
[characterizer.trim_spice/trim]: Keeping bl[127] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 1.1713644ns/0.19182711ns slew 0.03149035ns/0.058154194ns
[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.875ns (ub: 2.5 lb: 1.25)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.1875ns (ub: 2.5 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.03125ns (ub: 2.1875 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125)
[characterizer.delay/analyze]: Min Period: 2.1875n with a delay of 1.1713644 / 0.19182711
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
** Characterization: 8034.5 seconds
GDS: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45.gds
** GDS: 3.3 seconds
LEF: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45.lef
** LEF: 10.1 seconds
Verilog: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45.v
** Verilog: 0.0 seconds
** End: 8477.4 seconds

137
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_17202_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_32b_2048w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_17202_temp/ =========|
|==============================================================================|
Output files are sram_1rw_32b_2048w_1bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 32
Words: 2048
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 12:31:22.490074 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 103 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 31523 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 33446 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 37135 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 512 x 128
[verify.calibre/run_drc]: bitcell_array Geometries: 19924354 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 22274 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 12101 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 7939 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 10371 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_512rows Geometries: 242084 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 6464 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 18822 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 5700 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 140290 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 20402203 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_32b_2048w_1bank_freepdk45 Geometries: 20447018 Checks: 167 Errors: 0
** SRAM creation: 1092.7 seconds
SP: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45.sp
** Spice writing: 0.4 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_17202_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 11111111111 address
[characterizer.trim_spice/trim]: Keeping 31 data bit
[characterizer.trim_spice/trim]: Keeping bl[127] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[511] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 1.2374402ns/0.25744693ns slew 0.031680287ns/0.073574058ns
[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.875ns (ub: 2.5 lb: 1.25)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.1875ns (ub: 2.5 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.34375ns (ub: 2.5 lb: 2.1875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.265625ns (ub: 2.34375 lb: 2.1875)
[characterizer.delay/analyze]: Min Period: 2.34375n with a delay of 1.2374402 / 0.25744693
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
** Characterization: 12972.2 seconds
GDS: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45.gds
** GDS: 5.6 seconds
LEF: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45.lef
** LEF: 17.3 seconds
Verilog: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45.v
** Verilog: 0.0 seconds
** End: 14089.0 seconds

137
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_18997_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_32b_256w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_18997_temp/ =========|
|==============================================================================|
Output files are sram_1rw_32b_256w_1bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 32
Words: 256
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-23 17:53:13.665862 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 13 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 3983 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 5321 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 8875 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 64 x 128
[verify.calibre/run_drc]: bitcell_array Geometries: 2490882 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 22274 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 12101 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 7939 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 10371 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_64rows Geometries: 34473 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 4703 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 18822 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 5700 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 17538 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 2641339 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_32b_256w_1bank_freepdk45 Geometries: 2653124 Checks: 167 Errors: 0
** SRAM creation: 160.0 seconds
SP: Writing to ./sram_1rw_32b_256w_1bank_freepdk45.sp
** Spice writing: 0.1 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_32b_256w_1bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_18997_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 11111111 address
[characterizer.trim_spice/trim]: Keeping 31 data bit
[characterizer.trim_spice/trim]: Keeping bl[127] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[63] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 1.1300259ns/0.13801474ns slew 0.031264005ns/0.046135884ns
[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.875ns (ub: 2.5 lb: 1.25)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.1875ns (ub: 2.5 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.03125ns (ub: 2.1875 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125)
[characterizer.delay/analyze]: Min Period: 2.109375n with a delay of 1.1300259 / 0.13801474
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
** Characterization: 4457.6 seconds
GDS: Writing to ./sram_1rw_32b_256w_1bank_freepdk45.gds
** GDS: 1.4 seconds
LEF: Writing to ./sram_1rw_32b_256w_1bank_freepdk45.lef
** LEF: 3.6 seconds
Verilog: Writing to ./sram_1rw_32b_256w_1bank_freepdk45.v
** Verilog: 0.0 seconds
** End: 4623.9 seconds

137
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_3435_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_32b_512w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_3435_temp/ =========|
|==============================================================================|
Output files are sram_1rw_32b_512w_1bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 32
Words: 512
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 23:05:39.265001 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 26 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 7961 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 9383 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 12956 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 128 x 128
[verify.calibre/run_drc]: bitcell_array Geometries: 4981378 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 22274 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 12101 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 7939 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 10371 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_128rows Geometries: 65237 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 5290 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 18822 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 5700 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 35074 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 5189587 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_32b_512w_1bank_freepdk45 Geometries: 5206208 Checks: 167 Errors: 0
** SRAM creation: 219.2 seconds
SP: Writing to ./sram_1rw_32b_512w_1bank_freepdk45.sp
** Spice writing: 0.1 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_32b_512w_1bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_3435_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 111111111 address
[characterizer.trim_spice/trim]: Keeping 31 data bit
[characterizer.trim_spice/trim]: Keeping bl[127] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[127] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 1.1419594ns/0.15656674ns slew 0.031336377ns/0.049918723ns
[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.875ns (ub: 2.5 lb: 1.25)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.1875ns (ub: 2.5 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.03125ns (ub: 2.1875 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125)
[characterizer.delay/analyze]: Min Period: 2.1875n with a delay of 1.1419594 / 0.15656674
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
** Characterization: 5101.6 seconds
GDS: Writing to ./sram_1rw_32b_512w_1bank_freepdk45.gds
** GDS: 1.8 seconds
LEF: Writing to ./sram_1rw_32b_512w_1bank_freepdk45.lef
** LEF: 5.1 seconds
Verilog: Writing to ./sram_1rw_32b_512w_1bank_freepdk45.v
** Verilog: 0.0 seconds
** End: 5328.7 seconds

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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_31317_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_64b_1024w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_31317_temp/ =========|
|==============================================================================|
Output files are sram_1rw_64b_1024w_1bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 64
Words: 1024
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 09:27:13.909126 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 52 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 15917 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 17508 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 21120 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 256 x 256
[verify.calibre/run_drc]: bitcell_array Geometries: 19924226 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 44546 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 24197 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 15875 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 20739 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_256rows Geometries: 70385 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 5877 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 37638 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 11396 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 70146 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 20293913 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_64b_1024w_1bank_freepdk45 Geometries: 20320276 Checks: 167 Errors: 0
** SRAM creation: 1075.6 seconds
SP: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45.sp
** Spice writing: 0.3 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_31317_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 63 data bit
[characterizer.trim_spice/trim]: Keeping bl[255] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 1.850756ns/0.23319319ns slew 0.032157888ns/0.063655528ns
[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 3.75ns (ub: 5.0 lb: 2.5)
[characterizer.delay/find_min_period]: MinPeriod Search: 3.125ns (ub: 3.75 lb: 2.5)
[characterizer.delay/find_min_period]: MinPeriod Search: 3.4375ns (ub: 3.75 lb: 3.125)
[characterizer.delay/find_min_period]: MinPeriod Search: 3.59375ns (ub: 3.75 lb: 3.4375)
[characterizer.delay/analyze]: Min Period: 3.59375n with a delay of 1.850756 / 0.23319319
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
** Characterization: 9948.6 seconds
GDS: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45.gds
** GDS: 5.9 seconds
LEF: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45.lef
** LEF: 15.0 seconds
Verilog: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45.v
** Verilog: 0.0 seconds
** End: 11046.3 seconds

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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_3114_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_64b_1024w_2bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_3114_temp/ =========|
|==============================================================================|
Output files are sram_1rw_64b_1024w_2bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 64
Words: 1024
Banks: 2
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-23 19:10:19.014431 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 26 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 7961 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 9383 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 12956 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 128 x 256
[verify.calibre/run_drc]: bitcell_array Geometries: 9962498 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 44546 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 24197 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 15875 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 20739 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_128rows Geometries: 65237 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 5290 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 37638 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 11396 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 35074 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 10255431 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msb_address
[verify.calibre/run_drc]: msb_address Geometries: 594 Checks: 167 Errors: 0
ERROR: file calibre.py: line 131: sram_1rw_64b_1024w_2bank_freepdk45 Geometries: 20550242 Checks: 167 Errors: 1
ERROR: file design.py: line 87: DRC failed for sram_1rw_64b_1024w_2bank_freepdk45

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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_16936_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_8b_1024w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_16936_temp/ =========|
|==============================================================================|
Output files are sram_1rw_8b_1024w_4bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 8
Words: 1024
Banks: 4
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 22:05:07.033164 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 13 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 3983 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 5321 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 8875 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 64 x 32
[verify.calibre/run_drc]: bitcell_array Geometries: 622818 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 5570 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 3029 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 1987 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 2595 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_64rows Geometries: 34473 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 4703 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 4710 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 1428 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 17538 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 713631 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msb_address
[verify.calibre/run_drc]: msb_address Geometries: 1181 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_8b_1024w_4bank_freepdk45 Geometries: 3116996 Checks: 167 Errors: 0
** SRAM creation: 155.1 seconds
SP: Writing to ./sram_1rw_8b_1024w_4bank_freepdk45.sp
** Spice writing: 0.0 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_8b_1024w_4bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_16936_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 7 data bit
[characterizer.trim_spice/trim]: Keeping bl[31] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 40.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 80.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 160.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 320.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 640.0ns
ERROR: file delay.py: line 309: Timed out, could not find a feasible period.

138
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_17125_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_8b_256w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_17125_temp/ =========|
|==============================================================================|
Output files are sram_1rw_8b_256w_1bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 8
Words: 256
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 06:07:13.473469 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 13 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 3983 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 5321 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 8875 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 64 x 32
[verify.calibre/run_drc]: bitcell_array Geometries: 622818 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 5570 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 3029 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 1987 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 2595 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_64rows Geometries: 34473 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 4703 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 4710 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 1428 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 17538 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 711403 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_8b_256w_1bank_freepdk45 Geometries: 722780 Checks: 167 Errors: 0
** SRAM creation: 147.1 seconds
SP: Writing to ./sram_1rw_8b_256w_1bank_freepdk45.sp
** Spice writing: 0.0 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_8b_256w_1bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_17125_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 11111111 address
[characterizer.trim_spice/trim]: Keeping 7 data bit
[characterizer.trim_spice/trim]: Keeping bl[31] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[63] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 0.56986783ns/0.10418749ns slew 0.031200233ns/0.040857947ns
[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 0.625ns (ub: 1.25 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 0.9375ns (ub: 1.25 lb: 0.625)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.09375ns (ub: 1.25 lb: 0.9375)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.015625ns (ub: 1.09375 lb: 0.9375)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.0546875ns (ub: 1.09375 lb: 1.015625)
[characterizer.delay/analyze]: Min Period: 1.0546875n with a delay of 0.56986783 / 0.10418749
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
** Characterization: 3369.3 seconds
GDS: Writing to ./sram_1rw_8b_256w_1bank_freepdk45.gds
** GDS: 0.8 seconds
LEF: Writing to ./sram_1rw_8b_256w_1bank_freepdk45.lef
** LEF: 2.0 seconds
Verilog: Writing to ./sram_1rw_8b_256w_1bank_freepdk45.v
** Verilog: 0.0 seconds
** End: 3520.0 seconds

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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_21736_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_8b_512w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_21736_temp/ =========|
|==============================================================================|
Output files are sram_1rw_8b_512w_4bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 8
Words: 512
Banks: 4
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 05:27:47.667578 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 7 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 2147 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 3446 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 6991 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 32 x 32
[verify.calibre/run_drc]: bitcell_array Geometries: 311458 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 5570 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 3029 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 1987 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 2595 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_32rows Geometries: 9834 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 4116 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 4710 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 1428 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 8770 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 366234 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msb_address
[verify.calibre/run_drc]: msb_address Geometries: 1181 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_8b_512w_4bank_freepdk45 Geometries: 1621777 Checks: 167 Errors: 0
** SRAM creation: 151.4 seconds
SP: Writing to ./sram_1rw_8b_512w_4bank_freepdk45.sp
** Spice writing: 0.0 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_8b_512w_4bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_21736_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 111111111 address
[characterizer.trim_spice/trim]: Keeping 7 data bit
[characterizer.trim_spice/trim]: Keeping bl[31] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[127] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 40.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 80.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 160.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 320.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 640.0ns
ERROR: file delay.py: line 309: Timed out, could not find a feasible period.

140
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_19851_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/scn3me_subm/configs/sram_1rw_128b_1024w_1bank_scn3me_subm.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/scn3me_subm/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_19851_temp/ =========|
|==============================================================================|
Output files are sram_1rw_128b_1024w_1bank_scn3me_subm.(sp|gds|v|lib|lef)
Technology: scn3me_subm
Word size: 128
Words: 1024
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 16:42:54.839735 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 676 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 52 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 3150 Checks: 31 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 529 Checks: 31 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 4180 Checks: 31 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 6006 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 256 x 512
[verify.calibre/run_drc]: bitcell_array Geometries: 7735169 Checks: 31 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 54 Checks: 31 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 56322 Checks: 31 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 37124 Checks: 31 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 10115 Checks: 31 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 16259 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 603 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 1396 Checks: 31 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_256rows Geometries: 43581 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 2247 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 28802 Checks: 31 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 7300 Checks: 31 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 43010 Checks: 31 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 8038764 Checks: 31 Errors: 0
[verify.calibre/run_drc]: sram_1rw_128b_1024w_1bank_scn3me_subm Geometries: 8049909 Checks: 31 Errors: 0
** SRAM creation: 3444.8 seconds
SP: Writing to ./sram_1rw_128b_1024w_1bank_scn3me_subm.sp
** Spice writing: 0.8 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 2.45605 9.8242 78.5936 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.0125 0.05 0.4 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_128b_1024w_1bank_scn3me_subm_TT_5p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_19851_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 127 data bit
[characterizer.trim_spice/trim]: Keeping bl[511] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 40.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 80.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 80.0ns feasible_delay 31.821678ns/3.9657764ns slew 1.1609314ns/2.1309127ns
[characterizer.delay/find_min_period]: MinPeriod Search: 40.0ns (ub: 80.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 60.0ns (ub: 80.0 lb: 40.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 50.0ns (ub: 60.0 lb: 40.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 55.0ns (ub: 60.0 lb: 50.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 57.5ns (ub: 60.0 lb: 55.0)
[characterizer.delay/analyze]: Min Period: 60.0n with a delay of 31.821678 / 3.9657764
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
** Characterization: 13865.7 seconds
GDS: Writing to ./sram_1rw_128b_1024w_1bank_scn3me_subm.gds
** GDS: 9.5 seconds
LEF: Writing to ./sram_1rw_128b_1024w_1bank_scn3me_subm.lef
** LEF: 24.8 seconds
Verilog: Writing to ./sram_1rw_128b_1024w_1bank_scn3me_subm.v
** Verilog: 0.0 seconds
** End: 17346.0 seconds

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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_25247_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/scn3me_subm/configs/sram_1rw_128b_1024w_2bank_scn3me_subm.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/scn3me_subm/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_25247_temp/ =========|
|==============================================================================|
Output files are sram_1rw_128b_1024w_2bank_scn3me_subm.(sp|gds|v|lib|lef)
Technology: scn3me_subm
Word size: 128
Words: 1024
Banks: 2
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-23 19:52:25.469597 seconds
[sram/compute_sizes]: Words per row: 2
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 676 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 52 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 3150 Checks: 31 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 529 Checks: 31 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 4180 Checks: 31 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 6006 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 256 x 256
[verify.calibre/run_drc]: bitcell_array Geometries: 3867777 Checks: 31 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 54 Checks: 31 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 28162 Checks: 31 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 18690 Checks: 31 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 10115 Checks: 31 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 16259 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 603 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 1396 Checks: 31 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_256rows Geometries: 43581 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 2023 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 28802 Checks: 31 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 7300 Checks: 31 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 43010 Checks: 31 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 4116360 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msb_address
[verify.calibre/run_drc]: msb_address Geometries: 227 Checks: 31 Errors: 0
[verify.calibre/run_drc]: sram_1rw_128b_1024w_2bank_scn3me_subm Geometries: 8276548 Checks: 31 Errors: 0
** SRAM creation: 1180.6 seconds
SP: Writing to ./sram_1rw_128b_1024w_2bank_scn3me_subm.sp
** Spice writing: 0.4 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 2.45605 9.8242 78.5936 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.0125 0.05 0.4 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_128b_1024w_2bank_scn3me_subm_TT_5p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_25247_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 127 data bit
[characterizer.trim_spice/trim]: Keeping bl[254] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[511] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 20.0ns feasible_delay 9.657173ns/2.0055267ns slew 1.2971991ns/1.8894848ns
[characterizer.delay/find_min_period]: MinPeriod Search: 10.0ns (ub: 20.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 15.0ns (ub: 20.0 lb: 10.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 17.5ns (ub: 20.0 lb: 15.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 16.25ns (ub: 17.5 lb: 15.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 16.875ns (ub: 17.5 lb: 16.25)
[characterizer.delay/analyze]: Min Period: 17.5n with a delay of 9.657173 / 2.0055267
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
** Characterization: 19670.7 seconds
GDS: Writing to ./sram_1rw_128b_1024w_2bank_scn3me_subm.gds
** GDS: 7.8 seconds
LEF: Writing to ./sram_1rw_128b_1024w_2bank_scn3me_subm.lef
** LEF: 32.0 seconds
Verilog: Writing to ./sram_1rw_128b_1024w_2bank_scn3me_subm.v
** Verilog: 0.1 seconds
** End: 20892.0 seconds

140
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@ -0,0 +1,140 @@
[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_27456_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/scn3me_subm/configs/sram_1rw_128b_1024w_4bank_scn3me_subm.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/scn3me_subm/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_27456_temp/ =========|
|==============================================================================|
Output files are sram_1rw_128b_1024w_4bank_scn3me_subm.(sp|gds|v|lib|lef)
Technology: scn3me_subm
Word size: 128
Words: 1024
Banks: 4
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 01:40:41.999091 seconds
[sram/compute_sizes]: Words per row: 2
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 676 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 26 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 1577 Checks: 31 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 529 Checks: 31 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 2451 Checks: 31 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 4238 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 128 x 256
[verify.calibre/run_drc]: bitcell_array Geometries: 1934273 Checks: 31 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 54 Checks: 31 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 28162 Checks: 31 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 18690 Checks: 31 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 10115 Checks: 31 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 16259 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 603 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 1396 Checks: 31 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_128rows Geometries: 38587 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 1798 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 28802 Checks: 31 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 7300 Checks: 31 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 21506 Checks: 31 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 2133105 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msb_address
[verify.calibre/run_drc]: msb_address Geometries: 451 Checks: 31 Errors: 0
[verify.calibre/run_drc]: sram_1rw_128b_1024w_4bank_scn3me_subm Geometries: 9679655 Checks: 31 Errors: 0
** SRAM creation: 442.0 seconds
SP: Writing to ./sram_1rw_128b_1024w_4bank_scn3me_subm.sp
** Spice writing: 0.2 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 2.45605 9.8242 78.5936 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.0125 0.05 0.4 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_128b_1024w_4bank_scn3me_subm_TT_5p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_27456_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 127 data bit
[characterizer.trim_spice/trim]: Keeping bl[254] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[511] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 20.0ns feasible_delay 10.525582ns/2.331161ns slew 11.807006ns/2.3103235ns
[characterizer.delay/find_min_period]: MinPeriod Search: 10.0ns (ub: 20.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 15.0ns (ub: 20.0 lb: 10.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 17.5ns (ub: 20.0 lb: 15.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 18.75ns (ub: 20.0 lb: 17.5)
[characterizer.delay/find_min_period]: MinPeriod Search: 18.125ns (ub: 18.75 lb: 17.5)
[characterizer.delay/analyze]: Min Period: 18.75n with a delay of 10.525582 / 2.331161
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
** Characterization: 24789.5 seconds
GDS: Writing to ./sram_1rw_128b_1024w_4bank_scn3me_subm.gds
** GDS: 4.3 seconds
LEF: Writing to ./sram_1rw_128b_1024w_4bank_scn3me_subm.lef
** LEF: 35.3 seconds
Verilog: Writing to ./sram_1rw_128b_1024w_4bank_scn3me_subm.v
** Verilog: 0.0 seconds
** End: 25271.7 seconds

81
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_22808_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/scn3me_subm/configs/sram_1rw_32b_1024w_1bank_scn3me_subm.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/scn3me_subm/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_22808_temp/ =========|
|==============================================================================|
Output files are sram_1rw_32b_1024w_1bank_scn3me_subm.(sp|gds|v|lib|lef)
Technology: scn3me_subm
Word size: 32
Words: 1024
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 09:46:25.030648 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 676 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 52 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 3150 Checks: 31 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 529 Checks: 31 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 4180 Checks: 31 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 6006 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 256 x 128
[verify.calibre/run_drc]: bitcell_array Geometries: 1934081 Checks: 31 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 54 Checks: 31 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 14082 Checks: 31 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 9284 Checks: 31 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 2531 Checks: 31 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 4067 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 603 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 1396 Checks: 31 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_256rows Geometries: 43581 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 2247 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 7202 Checks: 31 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 1828 Checks: 31 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 43010 Checks: 31 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 2105580 Checks: 31 Errors: 0
[verify.calibre/run_drc]: sram_1rw_32b_1024w_1bank_scn3me_subm Geometries: 2115669 Checks: 31 Errors: 0
** SRAM creation: 421.2 seconds
SP: Writing to ./sram_1rw_32b_1024w_1bank_scn3me_subm.sp
** Spice writing: 0.2 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 2.45605 9.8242 78.5936 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.0125 0.05 0.4 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_32b_1024w_1bank_scn3me_subm_TT_5p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_22808_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 31 data bit
[characterizer.trim_spice/trim]: Keeping bl[127] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 20.0ns feasible_delay 11.055371ns/2.4753907ns slew 11.149545ns/1.6377695ns
ERROR: file delay.py: line 585: Couldn't run a simulation. slew=0.0125 load=78.5936

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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_20374_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/scn3me_subm/configs/sram_1rw_32b_2048w_1bank_scn3me_subm.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/scn3me_subm/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_20374_temp/ =========|
|==============================================================================|
Output files are sram_1rw_32b_2048w_1bank_scn3me_subm.(sp|gds|v|lib|lef)
Technology: scn3me_subm
Word size: 32
Words: 2048
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 13:22:42.190930 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 676 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 103 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 6236 Checks: 31 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 529 Checks: 31 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 7573 Checks: 31 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 9476 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 512 x 128
[verify.calibre/run_drc]: bitcell_array Geometries: 3867777 Checks: 31 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 54 Checks: 31 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 14082 Checks: 31 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 9284 Checks: 31 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 2531 Checks: 31 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 4067 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 603 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 1396 Checks: 31 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_512rows Geometries: 142746 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 2472 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 7202 Checks: 31 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 1828 Checks: 31 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 86018 Checks: 31 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 4158816 Checks: 31 Errors: 0
[verify.calibre/run_drc]: sram_1rw_32b_2048w_1bank_scn3me_subm Geometries: 4175356 Checks: 31 Errors: 0
** SRAM creation: 1157.2 seconds
SP: Writing to ./sram_1rw_32b_2048w_1bank_scn3me_subm.sp
** Spice writing: 0.4 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 2.45605 9.8242 78.5936 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.0125 0.05 0.4 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_32b_2048w_1bank_scn3me_subm_TT_5p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_20374_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 11111111111 address
[characterizer.trim_spice/trim]: Keeping 31 data bit
[characterizer.trim_spice/trim]: Keeping bl[127] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[511] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 20.0ns feasible_delay 9.1997828ns/3.104732ns slew 1.153121ns/1.7189341ns
[characterizer.delay/find_min_period]: MinPeriod Search: 10.0ns (ub: 20.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 15.0ns (ub: 20.0 lb: 10.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 17.5ns (ub: 20.0 lb: 15.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 16.25ns (ub: 17.5 lb: 15.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 16.875ns (ub: 17.5 lb: 16.25)
[characterizer.delay/analyze]: Min Period: 16.875n with a delay of 9.1997828 / 3.104732
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
** Characterization: 10830.5 seconds
GDS: Writing to ./sram_1rw_32b_2048w_1bank_scn3me_subm.gds
** GDS: 5.3 seconds
LEF: Writing to ./sram_1rw_32b_2048w_1bank_scn3me_subm.lef
** LEF: 17.0 seconds
Verilog: Writing to ./sram_1rw_32b_2048w_1bank_scn3me_subm.v
** Verilog: 0.0 seconds
** End: 12010.8 seconds

138
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_18998_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/scn3me_subm/configs/sram_1rw_32b_256w_1bank_scn3me_subm.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/scn3me_subm/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_18998_temp/ =========|
|==============================================================================|
Output files are sram_1rw_32b_256w_1bank_scn3me_subm.(sp|gds|v|lib|lef)
Technology: scn3me_subm
Word size: 32
Words: 256
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-23 17:53:13.352219 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 676 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 13 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 791 Checks: 31 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 529 Checks: 31 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 1588 Checks: 31 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 3356 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 64 x 128
[verify.calibre/run_drc]: bitcell_array Geometries: 483809 Checks: 31 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 54 Checks: 31 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 14082 Checks: 31 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 9284 Checks: 31 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 2531 Checks: 31 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 4067 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 603 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 1396 Checks: 31 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_64rows Geometries: 20501 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 1798 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 7202 Checks: 31 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 1828 Checks: 31 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 10754 Checks: 31 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 569737 Checks: 31 Errors: 0
[verify.calibre/run_drc]: sram_1rw_32b_256w_1bank_scn3me_subm Geometries: 575214 Checks: 31 Errors: 0
** SRAM creation: 157.4 seconds
SP: Writing to ./sram_1rw_32b_256w_1bank_scn3me_subm.sp
** Spice writing: 0.1 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 2.45605 9.8242 78.5936 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.0125 0.05 0.4 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_32b_256w_1bank_scn3me_subm_TT_5p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_18998_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 11111111 address
[characterizer.trim_spice/trim]: Keeping 31 data bit
[characterizer.trim_spice/trim]: Keeping bl[127] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[63] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 20.0ns feasible_delay 10.777462ns/1.9428786ns slew 11.093388ns/1.6047152ns
[characterizer.delay/find_min_period]: MinPeriod Search: 10.0ns (ub: 20.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 15.0ns (ub: 20.0 lb: 10.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 17.5ns (ub: 20.0 lb: 15.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 18.75ns (ub: 20.0 lb: 17.5)
[characterizer.delay/find_min_period]: MinPeriod Search: 19.375ns (ub: 20.0 lb: 18.75)
[characterizer.delay/analyze]: Min Period: 20.0n with a delay of 10.777462 / 1.9428786
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
** Characterization: 3663.3 seconds
GDS: Writing to ./sram_1rw_32b_256w_1bank_scn3me_subm.gds
** GDS: 1.2 seconds
LEF: Writing to ./sram_1rw_32b_256w_1bank_scn3me_subm.lef
** LEF: 3.7 seconds
Verilog: Writing to ./sram_1rw_32b_256w_1bank_scn3me_subm.v
** Verilog: 0.0 seconds
** End: 3825.9 seconds

138
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_805_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/scn3me_subm/configs/sram_1rw_32b_512w_1bank_scn3me_subm.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/scn3me_subm/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_805_temp/ =========|
|==============================================================================|
Output files are sram_1rw_32b_512w_1bank_scn3me_subm.(sp|gds|v|lib|lef)
Technology: scn3me_subm
Word size: 32
Words: 512
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 22:12:44.744640 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 676 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 26 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 1577 Checks: 31 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 529 Checks: 31 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 2451 Checks: 31 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 4238 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 128 x 128
[verify.calibre/run_drc]: bitcell_array Geometries: 967233 Checks: 31 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 54 Checks: 31 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 14082 Checks: 31 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 9284 Checks: 31 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 2531 Checks: 31 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 4067 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 603 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 1396 Checks: 31 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_128rows Geometries: 38587 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 2023 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 7202 Checks: 31 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 1828 Checks: 31 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 21506 Checks: 31 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 1089225 Checks: 31 Errors: 0
[verify.calibre/run_drc]: sram_1rw_32b_512w_1bank_scn3me_subm Geometries: 1096339 Checks: 31 Errors: 0
** SRAM creation: 218.8 seconds
SP: Writing to ./sram_1rw_32b_512w_1bank_scn3me_subm.sp
** Spice writing: 0.1 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 2.45605 9.8242 78.5936 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.0125 0.05 0.4 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_32b_512w_1bank_scn3me_subm_TT_5p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_805_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 111111111 address
[characterizer.trim_spice/trim]: Keeping 31 data bit
[characterizer.trim_spice/trim]: Keeping bl[127] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[127] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 20.0ns feasible_delay 11.057892ns/2.1338514ns slew 11.154288ns/1.608879ns
[characterizer.delay/find_min_period]: MinPeriod Search: 10.0ns (ub: 20.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 15.0ns (ub: 20.0 lb: 10.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 17.5ns (ub: 20.0 lb: 15.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 18.75ns (ub: 20.0 lb: 17.5)
[characterizer.delay/find_min_period]: MinPeriod Search: 19.375ns (ub: 20.0 lb: 18.75)
[characterizer.delay/analyze]: Min Period: 20.0n with a delay of 11.057892 / 2.1338514
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
** Characterization: 4702.5 seconds
GDS: Writing to ./sram_1rw_32b_512w_1bank_scn3me_subm.gds
** GDS: 2.1 seconds
LEF: Writing to ./sram_1rw_32b_512w_1bank_scn3me_subm.lef
** LEF: 6.4 seconds
Verilog: Writing to ./sram_1rw_32b_512w_1bank_scn3me_subm.v
** Verilog: 0.0 seconds
** End: 4930.3 seconds

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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_20091_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/scn3me_subm/configs/sram_1rw_64b_1024w_1bank_scn3me_subm.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/scn3me_subm/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_20091_temp/ =========|
|==============================================================================|
Output files are sram_1rw_64b_1024w_1bank_scn3me_subm.(sp|gds|v|lib|lef)
Technology: scn3me_subm
Word size: 64
Words: 1024
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 10:31:11.409774 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 676 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 52 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 3150 Checks: 31 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 529 Checks: 31 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 4180 Checks: 31 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 6006 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 256 x 256
[verify.calibre/run_drc]: bitcell_array Geometries: 3867777 Checks: 31 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 54 Checks: 31 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 28162 Checks: 31 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 18564 Checks: 31 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 5059 Checks: 31 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 8131 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 603 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 1396 Checks: 31 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_256rows Geometries: 43581 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 2247 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 14402 Checks: 31 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 3652 Checks: 31 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 43010 Checks: 31 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 4083308 Checks: 31 Errors: 0
[verify.calibre/run_drc]: sram_1rw_64b_1024w_1bank_scn3me_subm Geometries: 4093749 Checks: 31 Errors: 0
** SRAM creation: 1133.2 seconds
SP: Writing to ./sram_1rw_64b_1024w_1bank_scn3me_subm.sp
** Spice writing: 0.4 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 2.45605 9.8242 78.5936 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.0125 0.05 0.4 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_64b_1024w_1bank_scn3me_subm_TT_5p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_20091_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 63 data bit
[characterizer.trim_spice/trim]: Keeping bl[255] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 40.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 40.0ns feasible_delay 18.100242ns/3.0216206ns slew 1.1523092ns/1.7989579ns
[characterizer.delay/find_min_period]: MinPeriod Search: 20.0ns (ub: 40.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 30.0ns (ub: 40.0 lb: 20.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 35.0ns (ub: 40.0 lb: 30.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 32.5ns (ub: 35.0 lb: 30.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 33.75ns (ub: 35.0 lb: 32.5)
[characterizer.delay/analyze]: Min Period: 33.75n with a delay of 18.100242 / 3.0216206
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
** Characterization: 9134.8 seconds
GDS: Writing to ./sram_1rw_64b_1024w_1bank_scn3me_subm.gds
** GDS: 5.1 seconds
LEF: Writing to ./sram_1rw_64b_1024w_1bank_scn3me_subm.lef
** LEF: 15.3 seconds
Verilog: Writing to ./sram_1rw_64b_1024w_1bank_scn3me_subm.v
** Verilog: 0.0 seconds
** End: 10289.1 seconds

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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_15146_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/scn3me_subm/configs/sram_1rw_64b_1024w_2bank_scn3me_subm.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/scn3me_subm/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_15146_temp/ =========|
|==============================================================================|
Output files are sram_1rw_64b_1024w_2bank_scn3me_subm.(sp|gds|v|lib|lef)
Technology: scn3me_subm
Word size: 64
Words: 1024
Banks: 2
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-23 18:57:00.595079 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 676 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 26 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 1577 Checks: 31 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 529 Checks: 31 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 2451 Checks: 31 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 4238 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 128 x 256
[verify.calibre/run_drc]: bitcell_array Geometries: 1934273 Checks: 31 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 54 Checks: 31 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 28162 Checks: 31 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 18564 Checks: 31 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 5059 Checks: 31 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 8131 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 603 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 1396 Checks: 31 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_128rows Geometries: 38587 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 2023 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 14402 Checks: 31 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 3652 Checks: 31 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 21506 Checks: 31 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 2101688 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msb_address
[verify.calibre/run_drc]: msb_address Geometries: 227 Checks: 31 Errors: 0
[verify.calibre/run_drc]: sram_1rw_64b_1024w_2bank_scn3me_subm Geometries: 4231584 Checks: 31 Errors: 0
** SRAM creation: 396.0 seconds
SP: Writing to ./sram_1rw_64b_1024w_2bank_scn3me_subm.sp
** Spice writing: 0.2 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 2.45605 9.8242 78.5936 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.0125 0.05 0.4 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_64b_1024w_2bank_scn3me_subm_TT_5p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_15146_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 63 data bit
[characterizer.trim_spice/trim]: Keeping bl[255] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 40.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 80.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 160.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 320.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 640.0ns
ERROR: file delay.py: line 309: Timed out, could not find a feasible period.

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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_19440_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/scn3me_subm/configs/sram_1rw_8b_1024w_1bank_scn3me_subm.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/scn3me_subm/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_19440_temp/ =========|
|==============================================================================|
Output files are sram_1rw_8b_1024w_4bank_scn3me_subm.(sp|gds|v|lib|lef)
Technology: scn3me_subm
Word size: 8
Words: 1024
Banks: 4
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 21:32:06.233787 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 676 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 13 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 791 Checks: 31 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 529 Checks: 31 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 1588 Checks: 31 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 3356 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 64 x 32
[verify.calibre/run_drc]: bitcell_array Geometries: 121025 Checks: 31 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 54 Checks: 31 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 3522 Checks: 31 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 2324 Checks: 31 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 635 Checks: 31 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 1019 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 603 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 1396 Checks: 31 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_64rows Geometries: 20501 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 1798 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 1802 Checks: 31 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 460 Checks: 31 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 10754 Checks: 31 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 175320 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msb_address
[verify.calibre/run_drc]: msb_address Geometries: 451 Checks: 31 Errors: 0
[verify.calibre/run_drc]: sram_1rw_8b_1024w_4bank_scn3me_subm Geometries: 878870 Checks: 31 Errors: 0
** SRAM creation: 154.5 seconds
SP: Writing to ./sram_1rw_8b_1024w_4bank_scn3me_subm.sp
** Spice writing: 0.0 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 2.45605 9.8242 78.5936 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.0125 0.05 0.4 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_8b_1024w_4bank_scn3me_subm_TT_5p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_19440_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 7 data bit
[characterizer.trim_spice/trim]: Keeping bl[31] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 40.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 80.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 160.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 320.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 640.0ns
ERROR: file delay.py: line 309: Timed out, could not find a feasible period.

137
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_3280_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/scn3me_subm/configs/sram_1rw_8b_256w_1bank_scn3me_subm.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/scn3me_subm/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_3280_temp/ =========|
|==============================================================================|
Output files are sram_1rw_8b_256w_1bank_scn3me_subm.(sp|gds|v|lib|lef)
Technology: scn3me_subm
Word size: 8
Words: 256
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 09:06:11.454798 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 676 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 13 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 791 Checks: 31 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 529 Checks: 31 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 1588 Checks: 31 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 3356 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 64 x 32
[verify.calibre/run_drc]: bitcell_array Geometries: 121025 Checks: 31 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 54 Checks: 31 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 3522 Checks: 31 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 2324 Checks: 31 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 635 Checks: 31 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 1019 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 603 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 1396 Checks: 31 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_64rows Geometries: 20501 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 1798 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 1802 Checks: 31 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 460 Checks: 31 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 10754 Checks: 31 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 173929 Checks: 31 Errors: 0
[verify.calibre/run_drc]: sram_1rw_8b_256w_1bank_scn3me_subm Geometries: 179142 Checks: 31 Errors: 0
** SRAM creation: 140.6 seconds
SP: Writing to ./sram_1rw_8b_256w_1bank_scn3me_subm.sp
** Spice writing: 0.0 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 2.45605 9.8242 78.5936 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.0125 0.05 0.4 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_8b_256w_1bank_scn3me_subm_TT_5p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_3280_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 11111111 address
[characterizer.trim_spice/trim]: Keeping 7 data bit
[characterizer.trim_spice/trim]: Keeping bl[31] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[63] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 10.0ns feasible_delay 5.0024145ns/1.5312283ns slew 6.19582ns/1.5104699ns
[characterizer.delay/find_min_period]: MinPeriod Search: 5.0ns (ub: 10.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 7.5ns (ub: 10.0 lb: 5.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 8.75ns (ub: 10.0 lb: 7.5)
[characterizer.delay/find_min_period]: MinPeriod Search: 9.375ns (ub: 10.0 lb: 8.75)
[characterizer.delay/find_min_period]: MinPeriod Search: 9.0625ns (ub: 9.375 lb: 8.75)
[characterizer.delay/analyze]: Min Period: 9.0625n with a delay of 5.0024145 / 1.5312283
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375
[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594
** Characterization: 2269.5 seconds
GDS: Writing to ./sram_1rw_8b_256w_1bank_scn3me_subm.gds
** GDS: 0.6 seconds
LEF: Writing to ./sram_1rw_8b_256w_1bank_scn3me_subm.lef
** LEF: 1.7 seconds
Verilog: Writing to ./sram_1rw_8b_256w_1bank_scn3me_subm.v
** Verilog: 0.0 seconds
** End: 2412.7 seconds

86
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_12006_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/scn3me_subm/configs/sram_1rw_8b_512w_1bank_scn3me_subm.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/scn3me_subm/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_12006_temp/ =========|
|==============================================================================|
Output files are sram_1rw_8b_512w_4bank_scn3me_subm.(sp|gds|v|lib|lef)
Technology: scn3me_subm
Word size: 8
Words: 512
Banks: 4
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 08:41:55.300132 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 676 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 7 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 428 Checks: 31 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 529 Checks: 31 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 1189 Checks: 31 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 2948 Checks: 31 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 32 x 32
[verify.calibre/run_drc]: bitcell_array Geometries: 60561 Checks: 31 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 54 Checks: 31 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 3522 Checks: 31 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 2324 Checks: 31 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 635 Checks: 31 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 1019 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 603 Checks: 31 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 1396 Checks: 31 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_32rows Geometries: 6149 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 1574 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 1802 Checks: 31 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 460 Checks: 31 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 5378 Checks: 31 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 92246 Checks: 31 Errors: 0
[ms_flop_array/__init__]: Creating msb_address
[verify.calibre/run_drc]: msb_address Geometries: 451 Checks: 31 Errors: 0
[verify.calibre/run_drc]: sram_1rw_8b_512w_4bank_scn3me_subm Geometries: 474739 Checks: 31 Errors: 0
** SRAM creation: 147.7 seconds
SP: Writing to ./sram_1rw_8b_512w_4bank_scn3me_subm.sp
** Spice writing: 0.0 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 2.45605 9.8242 78.5936 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.0125 0.05 0.4 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_8b_512w_4bank_scn3me_subm_TT_5p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_12006_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 111111111 address
[characterizer.trim_spice/trim]: Keeping 7 data bit
[characterizer.trim_spice/trim]: Keeping bl[31] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[127] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 40.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 80.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 160.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 320.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 640.0ns
ERROR: file delay.py: line 309: Timed out, could not find a feasible period.