 mrg
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a145a37cf7
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PEP8 fixes in regress.py
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2020-10-05 15:56:12 -07:00 |
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mrg
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da83824a70
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Merge branch 'wlbuffer' into dev
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2020-10-05 15:33:54 -07:00 |
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mrg
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c4952ca8be
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Skip full sram pex test too slow
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2020-10-05 13:51:20 -07:00 |
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mrg
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4a58f09c1c
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Use 4x16 decoder with dual port bitcell in tests.
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2020-10-05 10:52:56 -07:00 |
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mrg
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c06b02e6fc
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Rename single_level_column_mux to just column_mux
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2020-10-05 08:56:51 -07:00 |
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mrg
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f8146e3f69
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Add decoder4x16
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2020-10-02 15:52:09 -07:00 |
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mrg
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64cc620440
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Add sram pex test
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2020-10-02 14:55:10 -07:00 |
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mrg
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1fc4040607
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Add pand4 and pnand4
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2020-10-02 14:54:12 -07:00 |
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mrg
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a62b82128c
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Skip riscv func test because too slow
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2020-10-02 13:33:58 -07:00 |
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mrg
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1e24b780bb
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Initial pex sram test.
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2020-10-02 13:32:52 -07:00 |
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mrg
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b32c123dab
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PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable.
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2020-10-01 11:10:18 -07:00 |
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Matt Guthaus
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112d57d90a
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Enable riscv tests
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2020-09-30 12:39:40 -07:00 |
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mrg
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f4e6a8895b
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Update riscv unit test
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2020-09-30 08:50:58 -07:00 |
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mrg
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b147e8485c
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PEP8 formatting
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2020-09-29 16:52:27 -07:00 |
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mrg
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8e908f016e
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PEP8 formatting
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2020-09-29 13:43:59 -07:00 |
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mrg
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54890a8d77
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Add new golden data
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2020-09-29 13:43:34 -07:00 |
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mrg
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0c280e062a
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Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case.
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2020-09-29 11:35:58 -07:00 |
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mrg
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9032bb9869
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Add global wordline delay test
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2020-09-29 10:28:57 -07:00 |
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mrg
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1eb8798bb6
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Add global functional test
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2020-09-28 16:12:09 -07:00 |
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mrg
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6f06bb9dd5
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Create sized RBL WL driver in port_address
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2020-09-28 11:30:21 -07:00 |
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mrg
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392afd4d4b
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Add unit test for hierarchical wordline.
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2020-09-15 13:46:21 -07:00 |
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mrg
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55dd4d0c47
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Global bitcell array working
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2020-09-14 14:35:52 -07:00 |
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mrg
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12fd60e8c3
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Fix pbitcell array test
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2020-09-09 12:02:09 -07:00 |
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mrg
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7bb21fb73f
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Updates to local and global arrays to make bitline and wordlines consistent.
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2020-09-09 11:54:46 -07:00 |
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mrg
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c1c631abe1
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Global bitcell array passes LVS/DRC
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2020-09-01 10:57:49 -07:00 |
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mrg
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7bdce3ca9a
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Don't make dummy bitlines pins for simplicity
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2020-09-01 09:55:23 -07:00 |
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mrg
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11a82b7283
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Fixed local bitcell array for single and dual port
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2020-08-27 14:03:05 -07:00 |
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mrg
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e92337ddaf
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Separate get_ and get_all for bitlines and wordlines
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2020-08-25 17:08:48 -07:00 |
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mrg
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28bd93bf51
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Still working on array refactor
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2020-08-25 11:50:44 -07:00 |
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mrg
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8dee5520e0
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Standardize array names independent of bitcell
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2020-08-21 13:44:35 -07:00 |
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mrg
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b762580ee2
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Skip global test for now
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2020-08-19 11:36:21 -07:00 |
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mrg
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224e359208
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Fix pin order for replica array
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2020-08-18 15:59:05 -07:00 |
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mrg
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f58fc6579f
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Rename local/global tests
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2020-08-18 15:58:44 -07:00 |
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mrg
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e3e4bac922
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Fix replica bitcell array for right only RBL
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2020-08-18 15:47:52 -07:00 |
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mrg
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59d65c46c3
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Fix bug in not adding RBLs in local bitcell array
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2020-08-18 15:11:10 -07:00 |
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mrg
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b288bba43e
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Add global bitcell array test
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2020-08-18 14:29:23 -07:00 |
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mrg
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99e252d6d4
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Update interface of RBL array
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2020-08-17 17:19:07 -07:00 |
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mrg
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b1e55f9072
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Add local bitcell array
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2020-08-17 15:14:42 -07:00 |
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mrg
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797c41c750
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Skip local bitcell array test
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2020-08-13 14:36:39 -07:00 |
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mrg
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8e890c2014
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Replica bitcell with all the fixings
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2020-08-11 15:00:29 -07:00 |
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mrg
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eef97ff215
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Reabstracting bit and word line names.
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2020-08-06 11:17:49 -07:00 |
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mrg
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2fa561f98f
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Local bitcell array edits. Skip test by default.
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2020-07-29 10:08:13 -07:00 |
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mrg
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c260297366
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Allow replica_bitcell_array without the replica columns for local wordlines.
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2020-07-27 16:22:21 -07:00 |
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mrg
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69cab42676
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Add pbuf_dec gate
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2020-07-27 13:59:55 -07:00 |
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mrg
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26b01e37c6
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Fix pbuf test info
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2020-07-27 13:59:35 -07:00 |
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mrg
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2991534d3f
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Drafting local bitline stuff.
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2020-07-23 17:15:39 -07:00 |
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mrg
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e1967dc548
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Draft local and global arrays. Ensure rows before cols in usage.
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2020-07-23 14:43:14 -07:00 |
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mrg
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3379f46da1
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Fail unit test, but mention if LVS passes and DRC fails.
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2020-06-30 16:22:44 -07:00 |
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mrg
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0a87691176
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Run Calibre LVS even if DRC fails.
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2020-06-30 15:27:10 -07:00 |
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mrg
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4e7e0c5954
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Skip test in sky130
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2020-06-29 15:28:16 -07:00 |
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