 Matt Guthaus
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8ec10cacd7
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Merge pull request #86 from bvhoof/dev
Dev
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2020-08-03 10:19:10 -07:00 |
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 Bob Vanhoof
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9b8ef5ef57
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fix: generated pex file was not passed correctly to lib characterizer
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2020-08-03 10:16:12 +02:00 |
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Bob Vanhoof
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487bb6c6e9
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Merge branch 'dev' of github:VLSIDA/OpenRAM into CalibrePexFilesUpdate
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2020-08-03 09:32:27 +02:00 |
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Bob Vanhoof
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dc55ededc1
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fix regession tests after calibre fix
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2020-07-31 12:51:34 +02:00 |
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mrg
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487027a9f2
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Fix pex file names
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2020-07-30 11:35:13 -07:00 |
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mrg
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8fa0065aaf
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Undo PR 82 changes -- broke unit test.
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2020-07-30 11:09:19 -07:00 |
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mrg
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a663d903c5
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-07-30 08:44:25 -07:00 |
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Matt Guthaus
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68387ec525
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Merge pull request #84 from bvhoof/CalibrePexFilesUpdate
calibrepex: file copy fix
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2020-07-30 08:40:35 -07:00 |
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 Hunter Nichols
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c6f2edc20d
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Changed warning message for multiport analytical characterization.
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2020-07-29 19:50:06 -07:00 |
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mrg
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64d61f4d56
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Merge remote-tracking branch 'private/dev' into dev
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2020-07-29 12:16:41 -07:00 |
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mrg
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f23d2e36a7
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Don't obstruct control logic signals with dffs when no column mux.
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2020-07-29 10:31:18 -07:00 |
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mrg
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8a2fa90cd5
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Merge remote-tracking branch 'private/dev' into dev
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2020-07-29 10:11:26 -07:00 |
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Hunter Nichols
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b4dafac489
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Fixed issue with sen measurement not being added
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2020-07-27 23:55:03 -07:00 |
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Hunter Nichols
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9ea3616260
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Changed multiport characterization warning to better fit
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2020-07-27 15:47:02 -07:00 |
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Hunter Nichols
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c65178f86c
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Fixed issue with sen delay measure getting mixed with voltage checks
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2020-07-27 15:43:50 -07:00 |
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mrg
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317662d4aa
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-07-23 14:17:52 -07:00 |
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mrg
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b7c43ae674
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Fix 1w/1r example
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2020-07-23 14:17:13 -07:00 |
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mrg
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58846a4a25
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Limit wordline driver size. Place row addr dff near predecoders.
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2020-07-20 17:57:38 -07:00 |
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mrg
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0ed81aa923
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Removed extraneous shift from added mirroring
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2020-07-20 14:11:52 -07:00 |
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mrg
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82bbacdfb5
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Add data bus gap to dynamically computed channel width
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2020-07-20 13:43:57 -07:00 |
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mrg
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a36e89e103
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Replace data flops depending on channel width
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2020-07-20 13:26:05 -07:00 |
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mrg
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2ccf3aea3b
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Set channel route height and width (of routes, not pins)
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2020-07-20 13:25:47 -07:00 |
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mrg
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f87b427f76
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Add parent to channel route for dumpign debug gds.
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2020-07-20 12:03:25 -07:00 |
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mrg
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f35848e4f8
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Route col flops separately. Flip port 1 col flop for easier routing.
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2020-07-20 12:02:59 -07:00 |
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mrg
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7385decbff
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Add channel route cyclic VCG debugging.
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2020-07-20 12:02:30 -07:00 |
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mrg
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80070dff41
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Move write_driver din left to avoid control signal in spare columns.
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2020-07-16 14:47:14 -07:00 |
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mrg
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9d5d632d1a
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Pins may be below the channel.
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2020-07-16 14:23:48 -07:00 |
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mrg
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ba3d32fa0c
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Starting to implement minimizing channel router (not done)
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2020-07-16 13:21:44 -07:00 |
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mrg
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919e6a5027
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Merge remote-tracking branch 'private/dev' into dev
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2020-07-15 19:47:44 -07:00 |
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mrg
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c7bc01c3a9
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Clean up binning. Fix mults to 1 for certain gates.
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2020-07-15 17:15:42 -07:00 |
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Bob Vanhoof
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ee3da91232
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calibrepex: file copy fix
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2020-07-15 11:50:21 +02:00 |
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mrg
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bb8157b3b7
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Exit on DRC not run, check for LVSDRC before running in sram_base.
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2020-07-14 08:38:49 -07:00 |
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mrg
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ed9d32c7bc
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OpenRAM 1.1.6
v1.1.6
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2020-07-13 16:26:25 -07:00 |
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mrg
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b4f5dc4c6e
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OpenRAM 1.1.6
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2020-07-13 16:25:55 -07:00 |
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mrg
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e502ee02be
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Place before computing height of col mux.
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2020-07-13 15:51:46 -07:00 |
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mrg
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2b7d89d2c1
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Fix netlist_only in sky130
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2020-07-13 14:59:31 -07:00 |
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mrg
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e49236f8fc
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Default drc and lvs errors is skipped.
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2020-07-13 14:08:00 -07:00 |
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mrg
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716798baae
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Convert all DRC and LVS routines to set member variables for drc_errors and lvs_errors.
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2020-07-13 13:01:00 -07:00 |
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mrg
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2011974e01
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Make drc and lvs errors a member variable. Run only once.
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2020-07-13 12:49:24 -07:00 |
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mrg
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a3195c0827
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Add words_per_row and others in config file.
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2020-07-13 12:37:56 -07:00 |
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mrg
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f49448d0a7
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Merge remote-tracking branch 'private/dev' into dev
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2020-07-09 11:58:04 -07:00 |
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mrg
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a989ea63a0
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Move magic/netgen files to tech dir
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2020-07-09 11:33:14 -07:00 |
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mrg
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27166c75f0
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Don't remove temp files during regular openram runs.
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2020-07-03 07:00:56 -07:00 |
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mrg
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5dde466ab9
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-07-03 06:55:45 -07:00 |
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mrg
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282f944b2f
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Also write .lvs file since it can be different the .sp
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2020-07-03 06:55:35 -07:00 |
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mrg
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ffcf762784
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Merge remote-tracking branch 'private/dev' into dev
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2020-07-03 06:47:37 -07:00 |
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Hunter Nichols
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206b02a7ee
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Merge branch 'dev' into characterizer_bug_fixes
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2020-07-02 18:00:41 -07:00 |
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Hunter Nichols
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fb34338fdf
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Removed debug statements
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2020-07-02 18:00:02 -07:00 |
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mrg
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2a86f9015b
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Merge remote-tracking branch 'private/dev' into dev
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2020-07-02 16:51:06 -07:00 |
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Hunter Nichols
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119bd94689
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Fixed warnings with single port characterization. Cleaned up some signal names.
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2020-07-02 15:43:23 -07:00 |
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