4342 Commits

This Branch

This Branch

All Branches

Author	SHA1	Message	Date
Eren Dogan	688069cded	Fix typo	2023-04-12 13:18:00 -07:00
Eren Dogan	fc8ea97254	Update documentation for clarity	2023-04-12 13:18:00 -07:00
Eren Dogan	71a8394cf8	Add note on how to uninstall conda	2023-04-10 14:30:30 -07:00
Eren Dogan	f7a24aafb7	Ignore coverage files	2023-04-10 10:29:21 -07:00
Eren Dogan	7af2badf31	Fix path search in custom module finder	2023-04-10 10:28:15 -07:00
Eren Dogan	095e0baddd	Remove CHECKPOINT_OPTS since it is not used	2023-04-07 12:32:29 -07:00
Eren Dogan	86372bbeb7	Add meta path finder for custom modules	2023-04-07 12:27:58 -07:00
vlsida-bot	85db2043b2	Bump version: 1.2.7 -> 1.2.8 v1.2.8	2023-03-31 06:10:25 +00:00
Jacob Walker	0b056dca54	fixed rom bank test name	2023-03-30 18:44:55 -07:00
Jacob Walker	52791a2719	a space	2023-03-30 11:30:50 -07:00
Jacob Walker	c1fb3cab6c	1kb rom DRC clean	2023-03-30 11:30:50 -07:00
Jacob Walker	7805fcb21e	more top level routing cleanup	2023-03-30 11:30:50 -07:00
Jacob Walker	fef9902c45	rom base passing tests with top level routing	2023-03-30 11:30:50 -07:00
mrg	7c453e80be	Simplify ROM test.	2023-03-30 11:30:50 -07:00
mrg	af0a6d32fb	Remove old skip tests	2023-03-30 11:30:50 -07:00
mrg	2075d244cb	Change ROM test permissions to include x	2023-03-30 11:30:50 -07:00
Jacob Walker	4c34a54d32	top level boundary fixes	2023-03-30 11:30:50 -07:00
Jacob Walker	7fe5ed5c41	edge routing	2023-03-30 11:30:50 -07:00
Jacob Walker	09f9c4cc20	some rom bank cleanup	2023-03-30 11:30:50 -07:00
mrg	56e14113aa	Change rom_base_bank name and top pin names	2023-03-30 11:30:50 -07:00
mrg	d2b5be0130	Add exclude tests for ROMs	2023-03-30 11:30:50 -07:00
mrg	fe65a20431	Rename ROM unit tests.	2023-03-30 11:30:50 -07:00
mrg	041c738cb2	Rework macros to run ROM tests too.	2023-03-30 11:30:50 -07:00
Jacob Walker	eec0f02bb8	skip test file	2023-03-30 11:30:50 -07:00
Jacob Walker	b50ec272da	updated top level rom unit tests	2023-03-30 11:30:50 -07:00
Jacob Walker	cd2314f008	better name	2023-03-30 11:30:50 -07:00
Jacob Walker	879c14b828	sky130 only	2023-03-30 11:30:50 -07:00
Jacob Walker	577cdcb232	example configs	2023-03-30 11:30:50 -07:00
Jacob Walker	41f0b9a412	rom compiler top level	2023-03-30 11:30:50 -07:00
Jacob Walker	2d5199961d	revert changes to pinvbuf	2023-03-30 11:30:50 -07:00
Jacob Walker	382c91f342	precharge array test passing sky130	2023-03-30 11:30:50 -07:00
Jacob Walker	92251fe61e	more code cleaning	2023-03-30 11:30:50 -07:00
Jacob Walker	90cf382a43	removed hardcoded DRC rule	2023-03-30 11:30:50 -07:00
Jacob Walker	0cb4459b4b	changed ROM test data path	2023-03-30 11:30:50 -07:00
Jacob Walker	af0209ec96	passing code style	2023-03-30 11:30:50 -07:00
Jacob Walker	79efff9ca6	code cleanup and updated copyright	2023-03-30 11:30:50 -07:00
Jacob Walker	ab955f0da8	removed data files	2023-03-30 11:30:50 -07:00
Jacob Walker	bbf2cd2913	Changes for test generation and simulation	2023-03-30 11:30:50 -07:00
Jacob Walker	89c7d50bd1	added row of nmos to end of array for precharge	2023-03-30 11:30:50 -07:00
SWalker	f847721500	changes to control logic, invert polarity of precharge	2023-03-30 11:30:50 -07:00
SWalker	9cefe5da7c	added unrouted output buffers	2023-03-30 11:30:50 -07:00
SWalker	764601a721	added binning to precharge pmos	2023-03-30 11:30:50 -07:00
Jesse Cirimelli-Low	6981cfa58b	add example of writing out simulation netlist	2023-03-30 11:30:50 -07:00
Jacob Walker	a64361b9d1	testing data for rom tests	2023-03-30 11:30:50 -07:00
Jacob Walker	736bd51fe1	add top level pins for sim	2023-03-30 11:30:50 -07:00
Jacob Walker	81bf2d7ae7	fixed decode lvs	2023-03-30 11:30:50 -07:00
Jacob Walker	16df8e0e43	fixing decoder lvs	2023-03-30 11:30:50 -07:00
Jacob Walker	559300e5cc	taps in main array and decoder	2023-03-30 11:30:50 -07:00
Jacob Walker	f7aed247fd	column control and address precharge	2023-03-30 11:30:50 -07:00
Jacob Walker	ce8197d206	pitch match decoder and array	2023-03-30 11:30:50 -07:00