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OpenRAM
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4,930 Commits 5 Branches 63 Tags 79 MiB
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120 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low 515591a422 dual port rba lvs clean again with cell library changes 2026-04-14 14:48:26 -07:00
Jesse Cirimelli-Low 5a74605117 single port fixes 2025-09-12 11:25:03 -07:00
Jesse Cirimelli-Low f3c1c5fbb2 Merge branch 'singleport_refactor' into array_gen 2025-02-24 23:26:28 -08:00
Eren Dogan 0a1de57cae Update copyright year 2024-01-03 14:32:44 -08:00
Jesse Cirimelli-Low 9ac894e2ef update bitcell array trimming 2023-08-15 11:30:16 -07:00
Jesse Cirimelli-Low 74c12f944f mirror skywater dp 2023-08-14 13:59:31 -07:00
Jesse Cirimelli-Low be72bcfa01 trim bitcells and fix replica column excluding 2023-08-10 00:34:16 -07:00
Jesse Cirimelli-Low 1aa04db2b6 add isntance naming templates 2023-08-03 16:24:24 -07:00
Jesse Cirimelli-Low 5e01bad2ee remove whitespace 2023-08-03 00:42:42 -07:00
Jesse Cirimelli-Low 61cfa55d75 fix replica col 2023-08-02 15:19:48 -07:00
Jesse Cirimelli-Low 5a764c9d43 remove MY mirroring in scmos 2023-08-01 19:05:55 -07:00
Jesse Cirimelli-Low d9d8cb2983 capped norbl scmos passing 2023-07-30 22:39:23 -07:00
Jesse Cirimelli-Low 811eb43459 working on updated placemet code 2023-07-30 20:06:40 -07:00
Jesse Cirimelli-Low 6f9618f28a fix 2023-07-28 21:46:07 -07:00
Jesse Cirimelli-Low 8d8f243f99 scmos passing with odd sizses again 2023-07-27 18:39:18 -07:00
Jesse Cirimelli-Low a6e07aa364 cleanup 2023-07-26 18:53:39 -07:00
Jesse Cirimelli-Low dde4103d49 scmos pass 2023-07-26 18:40:37 -07:00
Jesse Cirimelli-Low 8a4b34dee1 proper tiling 2023-07-26 18:05:36 -07:00
Jesse Cirimelli-Low 4cf3ea91ff scmos array connecting 2023-07-25 15:02:06 -07:00
Jesse Cirimelli-Low cb21443e2d start of pattern refactor 2023-07-24 23:25:35 -07:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg 5e546ee974 New power strapping mostly working. 
Each module uses M3/M4 power straps with pins on the ends.
Works in all technologies for a single no mux, dual port SRAM.
 2022-04-05 13:51:55 -07:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
mrg 3abebe4068 Add hierarchical seperator option to work with Xyce measurements. 2021-05-14 16:16:25 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg 8be1436d51 Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg 6a1f12b62d Refactored to utilize OOP 2020-10-13 11:07:31 -07:00
jcirimel 05667d784f move sky130 specific stuff to tech module lib 2020-10-13 04:48:10 -07:00
jcirimel 888646cdf9 merge in wlbuf and begin work on 32kb memory 2020-10-06 05:03:59 -07:00
jcirimel 7cbf456a4f sky130 rba done 2020-09-30 07:34:05 -07:00
mrg 449a4c2660 Exclude bitcells in other local areas not of interest 2020-09-29 12:15:42 -07:00
mrg d7e2340e62 Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
jcirimel 7afe3ea52c replica col arrangement done 2020-09-23 04:51:09 -07:00
jcirimel efdc171b14 make split wl specific to each port 2020-09-23 00:08:34 -07:00
jcirimel fb6a665514 removed references to technology name 2020-09-22 18:33:03 -07:00
jcirimel de33ab3761 fix single port bitcell pattern 2020-09-22 15:08:53 -07:00
jcirimel 559dfbc7a6 single port bitcell array done 2020-09-16 05:46:14 -07:00
jcirimel d22164bd48 single port progess 2020-09-14 18:11:38 -07:00
mrg 71d86f88b0 Merge branch 'dev' into wlbuffer 2020-09-10 13:05:14 -07:00
mrg 7bb21fb73f Updates to local and global arrays to make bitline and wordlines consistent. 2020-09-09 11:54:46 -07:00
Hunter Nichols 73b2277daa Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
mrg eef97ff215 Reabstracting bit and word line names. 2020-08-06 11:17:49 -07:00
mrg e1967dc548 Draft local and global arrays. Ensure rows before cols in usage. 2020-07-23 14:43:14 -07:00
mrg 7f65176908 Configured bitline directions into prot_data 2020-04-20 14:23:40 -07:00