 Jesse Cirimelli-Low
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6705f99855
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merge in dev
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2021-05-28 14:06:23 -07:00 |
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 mrg
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3abebe4068
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Add hierarchical seperator option to work with Xyce measurements.
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2021-05-14 16:16:25 -07:00 |
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Jesse Cirimelli-Low
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4ea0fcd068
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support multi cell wide precharge cells
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2021-04-23 22:49:29 -07:00 |
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Matt Guthaus
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30fc81a1f0
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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mrg
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01d312d65c
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Refactor add power pins
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2021-01-13 10:57:12 -08:00 |
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mrg
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47cc4cbfca
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Remove extra debug statement
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2020-12-08 11:55:53 -08:00 |
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mrg
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0100ae57a3
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Fix mirror with odd number of rows
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2020-12-08 10:31:22 -08:00 |
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mrg
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3829213afe
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Use and2_dec instead of buf_dec for better wldriver layout
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2020-12-01 11:19:12 -08:00 |
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mrg
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aa03eec943
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Fix syntax error.
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2020-11-21 07:16:45 -08:00 |
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mrg
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4c75bc003e
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Fix bounding box of replica array to include wordline grounds.
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2020-11-21 07:03:59 -08:00 |
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mrg
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f729e9fca7
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Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions.
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2020-11-20 16:56:07 -08:00 |
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mrg
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8021430122
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Fix pbitcell erros
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2020-11-13 15:55:55 -08:00 |
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mrg
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8be1436d51
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Use OPTS.bitcell everywhere
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2020-11-05 16:55:08 -08:00 |
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mrg
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da721a677d
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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mrg
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804814d18d
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Add bitlines to dummy modules
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2020-10-16 13:43:56 -07:00 |
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mrg
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20be7caf98
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Make conditional wl and bl for dummy rows/cols.
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2020-10-15 13:56:37 -07:00 |
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mrg
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6a1f12b62d
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Refactored to utilize OOP
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2020-10-13 11:07:31 -07:00 |
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jcirimel
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05667d784f
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move sky130 specific stuff to tech module lib
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2020-10-13 04:48:10 -07:00 |
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mrg
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8d5db50062
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Fix missing update for left RBL offset
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2020-10-08 16:40:53 -07:00 |
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mrg
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b0b15e8151
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Fix indent bug that failed to create rbl wl pin labels.
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2020-10-08 15:28:01 -07:00 |
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mrg
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01fe02bd90
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Fixes to replica bitline array.
Copy pasta error for right dummy column offset.
Put end_caps in try/except block.
PEP 8 formatting
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2020-10-08 14:53:44 -07:00 |
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jcirimel
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1e7ae06b7e
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fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end
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2020-10-08 05:32:03 -07:00 |
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jcirimel
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d40c3588ed
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no wl for col end
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2020-10-08 03:34:16 -07:00 |
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jcirimel
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13e2a9f5f7
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fix missed self.left_rbl refactor
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2020-10-06 05:11:15 -07:00 |
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jcirimel
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888646cdf9
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merge in wlbuf and begin work on 32kb memory
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2020-10-06 05:03:59 -07:00 |
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jcirimel
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7cbf456a4f
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sky130 rba done
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2020-09-30 07:34:05 -07:00 |
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mrg
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449a4c2660
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Exclude bitcells in other local areas not of interest
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2020-09-29 12:15:42 -07:00 |
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mrg
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d7e2340e62
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Lots of PEP8 cleanup. Refactor path graph to simulation class.
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2020-09-29 10:26:31 -07:00 |
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mrg
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70c90ca7fb
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Replica bitcell array bbox to include unused WL gnd pins.
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2020-09-28 14:49:33 -07:00 |
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jcirimel
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3dd72cdeac
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progress with rba pin mismatch
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2020-09-23 08:37:32 -07:00 |
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jcirimel
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17e6e5eb16
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row end col done
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2020-09-23 08:02:56 -07:00 |
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jcirimel
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5c263e0001
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rep col done w/o power pins
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2020-09-23 06:24:52 -07:00 |
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mrg
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e7ad22ff69
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Separate WL via from bitell array to avoid grounded WLs
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2020-09-15 13:38:28 -07:00 |
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jcirimel
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d22164bd48
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single port progess
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2020-09-14 18:11:38 -07:00 |
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mrg
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e95ab66916
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Update to space according to the bitcell array.
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2020-09-14 12:05:45 -07:00 |
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mrg
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8909ad7165
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Update modules to use variable bit offsets.
Bitcell arrays can return the bit offsets.
Port data and submodules can use offsets for spacing.
Default spacing for port data if no offsets given.
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2020-09-11 15:36:22 -07:00 |
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mrg
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c58741c44f
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Updates to global array.
Standardize bitcell array main array offsets.
Duplicate replica interface pins in global interface pins.
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2020-09-10 16:44:54 -07:00 |
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mrg
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9c762634a5
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Change default options for replica_bitcell_array
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2020-09-10 15:11:48 -07:00 |
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mrg
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71d86f88b0
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Merge branch 'dev' into wlbuffer
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2020-09-10 13:05:14 -07:00 |
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mrg
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f2313d0c73
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Use default names for replica_column too
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2020-09-10 12:04:46 -07:00 |
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mrg
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3c0707e5d1
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Consistents of bl x port then br x port
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2020-09-09 13:38:13 -07:00 |
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mrg
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3062aba214
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Fix update to exclude bits with RBLs
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2020-09-09 13:03:05 -07:00 |
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mrg
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7bb21fb73f
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Updates to local and global arrays to make bitline and wordlines consistent.
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2020-09-09 11:54:46 -07:00 |
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mrg
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1269bf6e16
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Global bitcell working
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2020-09-04 13:06:58 -07:00 |
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 Hunter Nichols
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8bcbf005bf
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Merge branch 'dev' into characterizer_bug_fixes
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2020-09-04 02:25:01 -07:00 |
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mrg
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f6f6242d68
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Ground dummy lines in replica bitcell array
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2020-09-03 10:45:28 -07:00 |
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mrg
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4ec47d8ee1
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Refactor global and local to be a bitcell_base_array
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2020-09-01 11:59:01 -07:00 |
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mrg
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7bdce3ca9a
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Don't make dummy bitlines pins for simplicity
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2020-09-01 09:55:23 -07:00 |
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Hunter Nichols
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73b2277daa
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Removed dead code related to older characterization scheme
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2020-08-27 17:30:58 -07:00 |
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mrg
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11a82b7283
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Fixed local bitcell array for single and dual port
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2020-08-27 14:03:05 -07:00 |
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