luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,502 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

1052 Commits

Author SHA1 Message Date
Samuel Crow 042a3ed14f
skip non-scmos delay control tests for now 2023-07-10 14:28:19 -07:00
Sam Crow 96a1d400fa add single port bank test for norbl 2023-06-12 12:50:50 -07:00
Sam Crow 266bcd9cf2 consolidate failing xyce delay tests to one in skip list 2023-06-11 14:52:26 -07:00
Sam Crow 854bff9dce add norbl bank tests to sky130 skipped tests 2023-06-08 13:22:12 -07:00
Sam Crow 7048a072e2 add local/global array sky130 skipped tests 2023-06-08 13:16:27 -07:00
Sam Crow 44ed72b50d add has_rbl=True arg to tests 2023-06-08 13:10:03 -07:00
Sam Crow a51b71d460 update copyright 2023-06-08 12:36:12 -07:00
Sam Crow 973b5512f0 add new failing sky130 tests to skip list 2023-06-07 17:29:58 -07:00
Sam Crow dcf95460d0 sort sky130 skipped tests numerically 2023-06-07 16:09:18 -07:00
Sam Crow 9256ae8c00 fix typos and standardize multiport control logic tests 2023-06-07 16:04:54 -07:00
Sam Crow 157935c915 update test/module imports related to delay control 2023-06-06 13:12:20 -07:00
Sam Crow 5fef78dbfa Merge branch 'no_rbl' into delay_ctrl 2023-06-05 16:31:07 -07:00
Sam Crow 2f5d3b6faf Merge branch 'dev' into delay_ctrl 2023-06-05 16:24:48 -07:00
Sam Crow df827fbd3d add norbl whole sram test 2023-06-05 15:26:26 -07:00
Sam Crow 0b5039cc89 make norbl bank test executable 2023-06-05 12:08:22 -07:00
Sam Crow 79e5c1ad86 add dp norbl bank test 2023-05-16 14:36:58 -07:00
Sam Crow f5bc031d83 Merge branch 'dev' into no_rbl 2023-05-03 15:24:03 -07:00
Sam Crow 123149503b add a bank test with no rbl 2023-04-25 09:27:56 -07:00
Eren Dogan 51ddb08385 Enable sky130 regression but disable failing tests 2023-04-13 22:12:46 -07:00
Sam Crow eea748ff3e remove test for unsupported config 2023-04-10 11:16:10 -07:00
Sam Crow 670b40642b add no rbl tests to 15 global array tests 2023-04-10 10:38:52 -07:00
Sam Crow dff94a032e fix bug in right rbl dual port replica array test 2023-04-07 11:30:15 -07:00
Sam Crow 83b25138d0 apply 14* standard to 15_local tests 2023-04-03 10:11:49 -07:00
Sam Crow 9181f6a218 standardize 14* test structure 2023-04-03 10:08:57 -07:00
Jacob Walker 0b056dca54 fixed rom bank test name 2023-03-30 18:44:55 -07:00
mrg 7c453e80be Simplify ROM test. 2023-03-30 11:30:50 -07:00
mrg af0a6d32fb Remove old skip tests 2023-03-30 11:30:50 -07:00
mrg 2075d244cb Change ROM test permissions to include x 2023-03-30 11:30:50 -07:00
mrg d2b5be0130 Add exclude tests for ROMs 2023-03-30 11:30:50 -07:00
mrg fe65a20431 Rename ROM unit tests. 2023-03-30 11:30:50 -07:00
Jacob Walker eec0f02bb8 skip test file 2023-03-30 11:30:50 -07:00
Jacob Walker b50ec272da updated top level rom unit tests 2023-03-30 11:30:50 -07:00
Jacob Walker 382c91f342 precharge array test passing sky130 2023-03-30 11:30:50 -07:00
Jacob Walker 0cb4459b4b changed ROM test data path 2023-03-30 11:30:50 -07:00
Jacob Walker af0209ec96 passing code style 2023-03-30 11:30:50 -07:00
Jacob Walker 79efff9ca6 code cleanup and updated copyright 2023-03-30 11:30:50 -07:00
Jacob Walker bbf2cd2913 Changes for test generation and simulation 2023-03-30 11:30:50 -07:00
SWalker 764601a721 added binning to precharge pmos 2023-03-30 11:30:50 -07:00
Jesse Cirimelli-Low 6981cfa58b add example of writing out simulation netlist 2023-03-30 11:30:50 -07:00
Jacob Walker 736bd51fe1 add top level pins for sim 2023-03-30 11:30:50 -07:00
Jacob Walker 16df8e0e43 fixing decoder lvs 2023-03-30 11:30:50 -07:00
Jacob Walker 559300e5cc taps in main array and decoder 2023-03-30 11:30:50 -07:00
Jacob Walker f7aed247fd column control and address precharge 2023-03-30 11:30:50 -07:00
Jacob Walker ce8197d206 pitch match decoder and array 2023-03-30 11:30:50 -07:00
Jacob Walker e697efa5f6 fixed base array lvs 2023-03-30 11:30:50 -07:00
Jacob Walker b2631b60ff updated imports to match upstream dev openram 2023-03-30 11:30:50 -07:00
Jacob Walker 63925bd48e Decoder array and start of rom bank 2023-03-30 11:30:50 -07:00
Jacob Walker bc8d564dbf array with poly straps passing drc/lvs 2023-03-30 11:30:50 -07:00
Jacob Walker 7309af7e29 base and dummy array alignment in sky130 2023-03-30 11:30:50 -07:00
Jacob Walker d7ac26a053 array generation and bitline routing with array module 2023-03-30 11:30:50 -07:00