 Bugra Onal
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2c6d3223ea
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Added conditional sections to template
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2022-07-08 13:51:07 -07:00 |
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Bugra Onal
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34f28554ad
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Multibank file generation (messy)
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2022-07-08 13:51:07 -07:00 |
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Bugra Onal
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3b43cefdc5
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modified template engine & sram multibank class
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2022-07-08 13:51:07 -07:00 |
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Bugra Onal
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3805db072a
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Template section clone method
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2022-07-08 13:51:07 -07:00 |
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Bugra Onal
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a7db6d182e
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Template section clone method
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2022-07-08 13:51:07 -07:00 |
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Bugra Onal
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5bbb8eae4c
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TEmplate rework
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2022-07-08 13:51:07 -07:00 |
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Bugra Onal
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41d04f88f4
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Base-verilog
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2022-07-08 13:51:07 -07:00 |
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Bugra Onal
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4afa391a87
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Base template additions
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2022-07-08 13:51:07 -07:00 |
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Bugra Onal
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e6ca67e945
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Verilog Template additions
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2022-07-08 13:51:07 -07:00 |
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Bugra Onal
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31bf5364ee
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Base verilog template init
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2022-07-08 13:51:07 -07:00 |
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Bugra Onal
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16512bc4ee
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Template module done
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2022-07-08 13:51:07 -07:00 |
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Bugra Onal
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a69a016d9f
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Bank select
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2022-07-08 13:51:07 -07:00 |
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Bugra Onal
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38a035a7da
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Templatable verilog file
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2022-07-08 13:51:07 -07:00 |
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 mrg
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ac86ad0e8a
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Move pdk installation inside docker to use Magic from docker image.
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2022-06-21 12:10:15 -07:00 |
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mrg
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dc9ae6cd1a
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Increase column width in netgen LVS scripts
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2022-06-16 10:30:58 -07:00 |
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mrg
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cf03454ecf
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Don't add wdriver_sel_n pins which aren't used.
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2022-06-10 09:18:40 -07:00 |
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mrg
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e744ffd6ea
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Move mount to shared target in openram.mk
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2022-06-09 06:44:23 -07:00 |
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mrg
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d30f05a1ae
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Update power layer on li for sky130
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2022-06-08 17:19:26 -07:00 |
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mrg
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9e3a28237f
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Update port data test for sky130 single port
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2022-06-08 17:18:53 -07:00 |
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mrg
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00ca2d45b6
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Extract unique is option not command.
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2022-06-08 15:06:06 -07:00 |
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mrg
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4814cf6eac
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Merge branch 'sky130_fixes' into dev
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2022-06-08 14:27:30 -07:00 |
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mrg
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280582d4d6
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Add missing via in dff array
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2022-06-08 14:24:17 -07:00 |
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mrg
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76bc4e1fc2
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Only do one extract. Flatten transistors since bug fixed in magic.
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2022-06-08 14:23:50 -07:00 |
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mrg
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ad6633ddca
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Update versions of tools. Fix supply bug in predecode.
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2022-06-08 13:50:25 -07:00 |
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 Jesse Cirimelli-Low
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fbe3032246
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add case for single spare col spare_wen_dff i/o
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2022-05-26 12:18:47 -07:00 |
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mrg
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1bab395946
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Merge branch 'sky130_fixes' into dev
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2022-05-24 09:12:37 -07:00 |
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mrg
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cb3d7b9d5d
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Add spares for sky130 unit tests.
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2022-05-23 17:27:26 -07:00 |
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mrg
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b84b4dab43
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Fail on pin mismatch too.
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2022-05-23 16:28:28 -07:00 |
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mrg
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8c85230033
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Remove experimental power option.
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2022-05-23 10:08:35 -07:00 |
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mrg
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51b0f125fb
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Add offset to 0,0 that was inadvertantly removed for router debug.
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2022-05-23 09:59:41 -07:00 |
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mrg
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735d66c9f1
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Start dff array supplies on first rather than second bit.
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2022-05-17 15:54:54 -07:00 |
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mrg
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3e02a0e7df
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Update column decoder and dff array supplies
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2022-05-17 15:49:50 -07:00 |
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mrg
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c8905c410a
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Fix case where distance is zero length comparison
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2022-05-17 15:49:06 -07:00 |
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mrg
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f1f4453d14
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Add column decoder module with power supply straps.
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2022-05-17 13:32:19 -07:00 |
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mrg
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8217a84165
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Uniquify overlap points during segment overlap computation.
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2022-05-17 13:31:23 -07:00 |
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mrg
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9b592ab432
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Fix missing hash recompute in vector class.
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2022-05-17 13:30:41 -07:00 |
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mrg
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bed12d2a9e
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pbitcell vdd/gnd are on layer m1 only.
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2022-05-16 17:02:53 -07:00 |
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mrg
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bdd334bce9
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Add layer and directions to pbitcell
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2022-05-16 16:11:13 -07:00 |
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mrg
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4be075e586
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Overlap length can include a rectangle overlap.
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2022-05-16 14:57:32 -07:00 |
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mrg
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3101643964
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Check for no pins and fix closest pin return type
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2022-05-13 14:34:26 -07:00 |
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mrg
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74c2c5ae0e
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Don't double prefix a name
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2022-05-13 14:32:52 -07:00 |
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mrg
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fbb2ea5fb6
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Intersection now returns a pin_layout fixed during LEF computation.
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2022-05-13 13:56:16 -07:00 |
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mrg
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4345136d1a
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Fix offsets for local bitcell arrays.
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2022-05-13 10:46:00 -07:00 |
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mrg
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357f967a93
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Leave supply routing to new helper functions.
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2022-05-11 11:01:14 -07:00 |
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mrg
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8f2d787d53
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Add min area metal in preferred direction
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2022-05-11 10:50:32 -07:00 |
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mrg
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b6c3580e24
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Fix width of replica routes. Don't enclose pins if they overlap sufficiently.
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2022-05-09 11:44:46 -07:00 |
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mrg
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50045e54e8
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Fix a couple supply routing issues.
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2022-05-03 11:45:51 -07:00 |
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mrg
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f8f3f16b1f
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Move delay line supply strap for pin access.
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2022-05-02 16:42:14 -07:00 |
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mrg
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942ab89754
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Remove debug output.
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2022-05-02 16:42:04 -07:00 |
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mrg
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3e48991acb
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Skip partial pins if they are too small to prevent DRC overlap errors.
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2022-05-02 16:07:05 -07:00 |
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