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https://github.com/VLSIDA/OpenRAM.git
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Merge branch 'sky130_fixes' into dev
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@@ -119,12 +119,12 @@ class dff_array(design.design):
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# Add connections every 4 cells
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for col in range(0, self.columns, 4):
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vdd_pin=self.dff_insts[0, col].get_pin("vdd")
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self.add_power_pin("vdd", vdd_pin.lc())
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self.add_power_pin("vdd", vdd_pin.lc(), start_layer=vdd_pin.layer)
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# Add connections every 4 cells
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for col in range(0, self.columns, 4):
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gnd_pin=self.dff_insts[0, col].get_pin("gnd")
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self.add_power_pin("gnd", gnd_pin.rc())
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self.add_power_pin("gnd", gnd_pin.rc(), start_layer=vdd_pin.layer)
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def add_layout_pins(self):
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for row in range(self.rows):
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@@ -416,4 +416,4 @@ class hierarchical_predecode(design.design):
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else:
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xoffset = self.inv_inst[0].lx() - self.bus_space
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pin_pos = vector(xoffset, and_pin.cy())
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self.add_power_pin(n, pin_pos)
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self.add_power_pin(n, pin_pos, start_layer=and_pin.layer)
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@@ -95,6 +95,7 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
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#f.write("gds polygon subcell true\n")
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f.write("gds warning default\n")
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# Flatten the transistors
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# Bug in Netgen 1.5.194 when using this...
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f.write("gds flatglob *_?mos_m*\n")
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# These two options are temporarily disabled until Tim fixes a bug in magic related
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# to flattening channel routes and vias (hierarchy with no devices in it). Otherwise,
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@@ -118,12 +119,13 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
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pre = "#"
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else:
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pre = ""
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if final_verification and OPTS.route_supplies:
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f.write(pre + "extract unique all\n")
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# Hack to work around unit scales in SkyWater
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if OPTS.tech_name=="sky130":
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f.write(pre + "extract style ngspice(si)\n")
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f.write(pre + "extract\n")
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if final_verification and OPTS.route_supplies:
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f.write(pre + "extract unique all\n")
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else:
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f.write(pre + "extract all\n")
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f.write(pre + "select top cell\n")
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f.write(pre + "feedback why\n")
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f.write('puts "Finished extract"\n')
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