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base
|
Base-verilog
|
2022-07-08 13:51:07 -07:00 |
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bitcells
|
pbitcell vdd/gnd are on layer m1 only.
|
2022-05-16 17:02:53 -07:00 |
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modules
|
Don't add wdriver_sel_n pins which aren't used.
|
2022-06-10 09:18:40 -07:00 |
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pgates
|
Leave supply routing to new helper functions.
|
2022-05-11 11:01:14 -07:00 |
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router
|
Fix case where distance is zero length comparison
|
2022-05-17 15:49:06 -07:00 |
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sram
|
Template module done
|
2022-07-08 13:51:07 -07:00 |
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verify
|
Increase column width in netgen LVS scripts
|
2022-06-16 10:30:58 -07:00 |
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verilogTemplate
|
Template module done
|
2022-07-08 13:51:07 -07:00 |
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Makefile
|
Move tests to test Makefile
|
2021-11-03 11:36:19 -07:00 |
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debug.py
|
Skywater changes.
|
2021-03-22 15:48:14 -07:00 |
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openram.py
|
Rework replica_bitcell_array supplies
|
2022-04-19 08:50:11 -07:00 |
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options.py
|
Remove experimental power option.
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2022-05-23 10:08:35 -07:00 |